Merge branch 'bugfix/move_adc_onshot_power_management_to_shot_read_func_v5.1' into 'release/v5.1'

Sleep: Fixed abnormal deepsleep base current of ULP ADC on esp32s2/esp32s3 chips (backport v5.1)

See merge request espressif/esp-idf!23828

components/esp_adc/adc_oneshot.c

@@ -122,8 +122,6 @@ esp_err_t adc_oneshot_new_unit(const adc_oneshot_unit_init_cfg_t *init_config, a
     _lock_release(&s_ctx.mutex);
 #endif
 
-    sar_periph_ctrl_adc_oneshot_power_acquire();
-
     ESP_LOGD(TAG, "new adc unit%"PRId32" is created", unit->unit_id);
     *ret_unit = unit;
     return ESP_OK;
@@ -169,6 +167,7 @@ esp_err_t adc_oneshot_read(adc_oneshot_unit_handle_t handle, adc_channel_t chan,
     }
     portENTER_CRITICAL(&rtc_spinlock);
 
+    sar_periph_ctrl_adc_oneshot_power_acquire();
     adc_oneshot_hal_setup(&(handle->hal), chan);
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
     adc_atten_t atten = adc_ll_get_atten(handle->unit_id, chan);
@@ -177,6 +176,7 @@ esp_err_t adc_oneshot_read(adc_oneshot_unit_handle_t handle, adc_channel_t chan,
 #endif
     bool valid = false;
     valid = adc_oneshot_hal_convert(&(handle->hal), out_raw);
+    sar_periph_ctrl_adc_oneshot_power_release();
 
     portEXIT_CRITICAL(&rtc_spinlock);
     adc_lock_release(handle->unit_id);
@@ -192,14 +192,15 @@ esp_err_t adc_oneshot_read_isr(adc_oneshot_unit_handle_t handle, adc_channel_t c
 
     portENTER_CRITICAL_SAFE(&rtc_spinlock);
 
+    sar_periph_ctrl_adc_oneshot_power_acquire();
     adc_oneshot_hal_setup(&(handle->hal), chan);
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
     adc_atten_t atten = adc_ll_get_atten(handle->unit_id, chan);
     adc_hal_calibration_init(handle->unit_id);
     adc_set_hw_calibration_code(handle->unit_id, atten);
 #endif
-
     adc_oneshot_hal_convert(&(handle->hal), out_raw);
+    sar_periph_ctrl_adc_oneshot_power_release();
 
     portEXIT_CRITICAL_SAFE(&rtc_spinlock);
 
@@ -219,8 +220,6 @@ esp_err_t adc_oneshot_del_unit(adc_oneshot_unit_handle_t handle)
     ESP_LOGD(TAG, "adc unit%"PRId32" is deleted", handle->unit_id);
     free(handle);
 
-    sar_periph_ctrl_adc_oneshot_power_release();
-
 #if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
     //To free the APB_SARADC periph if needed
     _lock_acquire(&s_ctx.mutex);

components/esp_hw_support/linker.lf

@@ -41,3 +41,5 @@ entries:
     if SOC_MEMSPI_SRC_FREQ_120M = y:
         mspi_timing_tuning (noflash)
         mspi_timing_config (noflash)
+    if ADC_ONESHOT_CTRL_FUNC_IN_IRAM = y:
+        sar_periph_ctrl (noflash)

components/esp_hw_support/port/esp32s3/sar_periph_ctrl.c

@@ -29,7 +29,7 @@ extern portMUX_TYPE rtc_spinlock;
 void sar_periph_ctrl_init(void)
 {
     //Put SAR control mux to FSM state
-    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_ON);
+    sar_ctrl_ll_set_power_mode(SAR_CTRL_LL_POWER_FSM);
 
     //Add other periph power control initialisation here
 }

components/esp_hw_support/sleep_modes.c

@@ -439,6 +439,8 @@ inline static void IRAM_ATTR misc_modules_sleep_prepare(bool deep_sleep)
         regi2c_analog_cali_reg_read();
 #endif
     }
+
+    // TODO: IDF-7370
     if (!(deep_sleep && s_adc_tsen_enabled)){
         sar_periph_ctrl_power_disable();
     }

components/hal/esp32/include/hal/sar_ctrl_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -39,6 +39,7 @@ typedef enum {
  *
  * @param mode  See `sar_ctrl_ll_power_t`
  */
+__attribute__((always_inline))
 static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
 {
     if (mode == SAR_CTRL_LL_POWER_FSM) {

components/hal/esp32c2/include/hal/adc_ll.h

@@ -327,6 +327,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  *
  * @param manage Set ADC power status.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_power_manage(adc_ll_power_t manage)
 {
     /* Bit1  0:Fsm  1: SW mode

components/hal/esp32c3/include/hal/adc_ll.h

@@ -497,6 +497,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  *
  * @param manage Set ADC power status.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_power_manage(adc_ll_power_t manage)
 {
     /* Bit1  0:Fsm  1: SW mode

components/hal/esp32c6/include/hal/sar_ctrl_ll.h

@@ -44,6 +44,7 @@ typedef enum {
  *
  * @param[in] mode  See `sar_ctrl_ll_power_t`
  */
+__attribute__((always_inline))
 static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
 {
     if (mode == SAR_CTRL_LL_POWER_FSM) {

components/hal/esp32h2/include/hal/sar_ctrl_ll.h

@@ -44,6 +44,7 @@ typedef enum {
  *
  * @param[in] mode  See `sar_ctrl_ll_power_t`
  */
+__attribute__((always_inline))
 static inline void sar_ctrl_ll_set_power_mode_from_pwdet(sar_ctrl_ll_power_t mode)
 {
     if (mode == SAR_CTRL_LL_POWER_FSM) {

components/hal/esp32s2/include/hal/adc_ll.h

@@ -877,6 +877,7 @@ static inline void adc_oneshot_ll_disable_all_unit(void)
  *
  * @param manage Set ADC power status.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_power_manage(adc_ll_power_t manage)
 {
     if (manage == ADC_LL_POWER_SW_ON) {

components/hal/esp32s3/include/hal/adc_ll.h

@@ -562,6 +562,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  *
  * @param manage Set ADC power status.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_power_manage(adc_ll_power_t manage)
 {
     if (manage == ADC_LL_POWER_SW_ON) {

components/hal/esp32s3/include/hal/sar_ctrl_ll.h

@@ -45,6 +45,7 @@ typedef enum {
  *
  * @param mode  See `sar_ctrl_ll_power_t`
  */
+__attribute__((always_inline))
 static inline void sar_ctrl_ll_set_power_mode(sar_ctrl_ll_power_t mode)
 {
     if (mode == SAR_CTRL_LL_POWER_FSM) {