Merge branch 'refactor/split_esp32c61_soc_include_folder' into 'master'

refactor(soc): sort esp32c61 soc headers

See merge request espressif/esp-idf!33322

components/soc/esp32c61/include/soc/dport_access.h

@@ -9,7 +9,6 @@
 
 #include <stdint.h>
 #include "soc.h"
-#include "uart_reg.h"
 
 #ifdef __cplusplus
 extern "C" {

components/soc/esp32c61/include/soc/soc.h

@@ -12,7 +12,7 @@
 #endif
 
 #include "esp_bit_defs.h"
-#include "reg_base.h"
+#include "soc/reg_base.h"
 
 #define PRO_CPU_NUM (0)
 

components/soc/esp32c61/include/soc/system_reg.h

@@ -6,6 +6,6 @@
 
 #include "soc/hp_system_reg.h"
 
-#include "intpri_reg.h"
+#include "soc/intpri_reg.h"
 #define SYSTEM_CPU_INTR_FROM_CPU_0_REG INTPRI_CPU_INTR_FROM_CPU_0_REG
 #define SYSTEM_CPU_INTR_FROM_CPU_0 INTPRI_CPU_INTR_FROM_CPU_0

components/soc/esp32c61/register/soc/assist_debug_reg.h

@@ -115,7 +115,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S  10
 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor enbale
+ *  DBUS busy monitor enable
  */
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA    (BIT(11))
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
@@ -295,7 +295,7 @@ extern "C" {
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V  0x00000001U
 #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S  10
 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [11]; default: 0;
- *  DBUS busy monitor interrupt enbale
+ *  DBUS busy monitor interrupt enable
  */
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA    (BIT(11))
 #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_M  (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S)

components/soc/esp32c61/register/soc/assist_debug_struct.h

@@ -83,7 +83,7 @@ typedef union {
          */
         uint32_t core_0_iram0_exception_monitor_ena:1;
         /** core_0_dram0_exception_monitor_ena : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor enbale
+         *  DBUS busy monitor enable
          */
         uint32_t core_0_dram0_exception_monitor_ena:1;
         uint32_t reserved_12:20;
@@ -372,7 +372,7 @@ typedef union {
          */
         uint32_t core_0_iram0_exception_monitor_intr_ena:1;
         /** core_0_dram0_exception_monitor_intr_ena : R/W; bitpos: [11]; default: 0;
-         *  DBUS busy monitor interrupt enbale
+         *  DBUS busy monitor interrupt enable
          */
         uint32_t core_0_dram0_exception_monitor_intr_ena:1;
         uint32_t reserved_12:20;
@@ -441,7 +441,7 @@ typedef union {
 } assist_debug_core_0_intr_clr_reg_t;
 
 
-/** Group: pc reording configuration register */
+/** Group: pc recording configuration register */
 /** Type of core_0_rcd_en register
  *  HP CPU PC logging enable register
  */
@@ -465,7 +465,7 @@ typedef union {
 } assist_debug_core_0_rcd_en_reg_t;
 
 
-/** Group: pc reording status register */
+/** Group: pc recording status register */
 /** Type of core_0_rcd_pdebugpc register
  *  PC logging register
  */
@@ -493,7 +493,7 @@ typedef union {
 } assist_debug_core_0_rcd_pdebugsp_reg_t;
 
 
-/** Group: exception monitor regsiter */
+/** Group: exception monitor register */
 /** Type of core_0_iram0_exception_monitor_0 register
  *  exception monitor status register0
  */

components/soc/esp32c61/register/soc/cache_reg.h

@@ -4077,7 +4077,7 @@ extern "C" {
 #define CACHE_L1_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x254)
 /** CACHE_L1_ICACHE0_UNALLOC_CLR : HRO; bitpos: [0]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request is responded but not completed.
  */
 #define CACHE_L1_ICACHE0_UNALLOC_CLR    (BIT(0))
 #define CACHE_L1_ICACHE0_UNALLOC_CLR_M  (CACHE_L1_ICACHE0_UNALLOC_CLR_V << CACHE_L1_ICACHE0_UNALLOC_CLR_S)
@@ -4085,7 +4085,7 @@ extern "C" {
 #define CACHE_L1_ICACHE0_UNALLOC_CLR_S  0
 /** CACHE_L1_ICACHE1_UNALLOC_CLR : HRO; bitpos: [1]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request is responded but not completed.
  */
 #define CACHE_L1_ICACHE1_UNALLOC_CLR    (BIT(1))
 #define CACHE_L1_ICACHE1_UNALLOC_CLR_M  (CACHE_L1_ICACHE1_UNALLOC_CLR_V << CACHE_L1_ICACHE1_UNALLOC_CLR_S)
@@ -4107,7 +4107,7 @@ extern "C" {
 #define CACHE_L1_ICACHE3_UNALLOC_CLR_S  3
 /** CACHE_L1_CACHE_UNALLOC_CLR : R/W; bitpos: [4]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l1 cache where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request is responded but not completed.
  */
 #define CACHE_L1_CACHE_UNALLOC_CLR    (BIT(4))
 #define CACHE_L1_CACHE_UNALLOC_CLR_M  (CACHE_L1_CACHE_UNALLOC_CLR_V << CACHE_L1_CACHE_UNALLOC_CLR_S)
@@ -5937,7 +5937,7 @@ extern "C" {
 #define CACHE_L2_UNALLOCATE_BUFFER_CLEAR_REG (DR_REG_CACHE_BASE + 0x3b0)
 /** CACHE_L2_CACHE_UNALLOC_CLR : HRO; bitpos: [5]; default: 0;
  *  The bit is used to clear the unallocate request buffer of l2 icache where the
- *  unallocate request is responsed but not completed.
+ *  unallocate request is responded but not completed.
  */
 #define CACHE_L2_CACHE_UNALLOC_CLR    (BIT(5))
 #define CACHE_L2_CACHE_UNALLOC_CLR_M  (CACHE_L2_CACHE_UNALLOC_CLR_V << CACHE_L2_CACHE_UNALLOC_CLR_S)

components/soc/esp32c61/register/soc/cache_struct.h

@@ -5100,12 +5100,12 @@ typedef union {
     struct {
         /** l1_icache0_unalloc_clr : HRO; bitpos: [0]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 icache0 where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l1_icache0_unalloc_clr:1;
         /** l1_icache1_unalloc_clr : HRO; bitpos: [1]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 icache1 where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l1_icache1_unalloc_clr:1;
         /** l1_icache2_unalloc_clr : HRO; bitpos: [2]; default: 0;
@@ -5118,7 +5118,7 @@ typedef union {
         uint32_t l1_icache3_unalloc_clr:1;
         /** l1_cache_unalloc_clr : R/W; bitpos: [4]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l1 cache where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l1_cache_unalloc_clr:1;
         uint32_t reserved_5:27;
@@ -5134,7 +5134,7 @@ typedef union {
         uint32_t reserved_0:5;
         /** l2_cache_unalloc_clr : HRO; bitpos: [5]; default: 0;
          *  The bit is used to clear the unallocate request buffer of l2 icache where the
-         *  unallocate request is responsed but not completed.
+         *  unallocate request is responded but not completed.
          */
         uint32_t l2_cache_unalloc_clr:1;
         uint32_t reserved_6:26;

components/soc/esp32c61/register/soc/ecdsa_reg.h

@@ -211,7 +211,7 @@ extern "C" {
  */
 #define ECDSA_START_REG (DR_REG_ECDSA_BASE + 0x1c)
 /** ECDSA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
+ *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
  *  after configuration.
  */
 #define ECDSA_START    (BIT(0))
@@ -299,7 +299,7 @@ extern "C" {
  */
 #define ECDSA_SHA_START_REG (DR_REG_ECDSA_BASE + 0x210)
 /** ECDSA_SHA_START : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
+ *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
  *  bit will be self-cleared after configuration.
  */
 #define ECDSA_SHA_START    (BIT(0))
@@ -312,7 +312,7 @@ extern "C" {
  */
 #define ECDSA_SHA_CONTINUE_REG (DR_REG_ECDSA_BASE + 0x214)
 /** ECDSA_SHA_CONTINUE : WT; bitpos: [0]; default: 0;
- *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
+ *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
  *  bit will be self-cleared after configuration.
  */
 #define ECDSA_SHA_CONTINUE    (BIT(0))

components/soc/esp32c61/register/soc/ecdsa_struct.h

@@ -57,7 +57,7 @@ typedef union {
 typedef union {
     struct {
         /** start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start caculation of ECDSA Accelerator. This bit will be self-cleared
+         *  Write 1 to start calculation of ECDSA Accelerator. This bit will be self-cleared
          *  after configuration.
          */
         uint32_t start:1;
@@ -260,7 +260,7 @@ typedef union {
 typedef union {
     struct {
         /** sha_start : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the first caculation of SHA Calculator in ECDSA Accelerator. This
+         *  Write 1 to start the first calculation of SHA Calculator in ECDSA Accelerator. This
          *  bit will be self-cleared after configuration.
          */
         uint32_t sha_start:1;
@@ -275,7 +275,7 @@ typedef union {
 typedef union {
     struct {
         /** sha_continue : WT; bitpos: [0]; default: 0;
-         *  Write 1 to start the latter caculation of SHA Calculator in ECDSA Accelerator. This
+         *  Write 1 to start the latter calculation of SHA Calculator in ECDSA Accelerator. This
          *  bit will be self-cleared after configuration.
          */
         uint32_t sha_continue:1;

components/soc/esp32c61/register/soc/gpio_ext_reg.h

@@ -37,7 +37,7 @@ extern "C" {
 #define GPIO_EXT_XPD_COMP_0_V  0x00000001U
 #define GPIO_EXT_XPD_COMP_0_S  0
 /** GPIO_EXT_MODE_COMP_0 : R/W; bitpos: [1]; default: 0;
- *  Configures the reference voltage for analog PAD voltage comparater.. \\
+ *  Configures the reference voltage for analog PAD voltage comparator.. \\
  *  0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be
  *  used as a regular GPIO\\
  *  1: Reference voltage is the voltage on the GPIO8 PAD\\

components/soc/esp32c61/register/soc/gpio_ext_struct.h

@@ -39,7 +39,7 @@ typedef union {
          */
         uint32_t xpd_comp_0:1;
         /** mode_comp_0 : R/W; bitpos: [1]; default: 0;
-         *  Configures the reference voltage for analog PAD voltage comparater.. \\
+         *  Configures the reference voltage for analog PAD voltage comparator.. \\
          *  0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be
          *  used as a regular GPIO\\
          *  1: Reference voltage is the voltage on the GPIO8 PAD\\

components/soc/esp32c61/register/soc/i2s_reg.h

@@ -320,7 +320,7 @@ extern "C" {
 #define I2S_TX_SLAVE_MOD_V  0x00000001U
 #define I2S_TX_SLAVE_MOD_S  3
 /** I2S_TX_STOP_EN : R/W; bitpos: [4]; default: 1;
- *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
+ *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
  */
 #define I2S_TX_STOP_EN    (BIT(4))
 #define I2S_TX_STOP_EN_M  (I2S_TX_STOP_EN_V << I2S_TX_STOP_EN_S)

components/soc/esp32c61/register/soc/i2s_struct.h

@@ -410,7 +410,7 @@ typedef union {
          */
         uint32_t tx_slave_mod:1;
         /** tx_stop_en : R/W; bitpos: [4]; default: 1;
-         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
+         *  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is empty
          */
         uint32_t tx_stop_en:1;
         /** tx_chan_equal : R/W; bitpos: [5]; default: 0;

components/soc/esp32c61/register/soc/lp_clkrst_reg.h

@@ -211,7 +211,7 @@ extern "C" {
 #define LP_CLKRST_ANA_PERI_RESET_EN_S  31
 
 /** LP_CLKRST_RESET_CAUSE_REG register
- *  Represents the reset casue
+ *  Represents the reset cause
  */
 #define LP_CLKRST_RESET_CAUSE_REG (DR_REG_LP_CLKRST_BASE + 0x10)
 /** LP_CLKRST_RESET_CAUSE : RO; bitpos: [4:0]; default: 0;

components/soc/esp32c61/register/soc/lp_clkrst_struct.h

@@ -171,7 +171,7 @@ typedef union {
 } lp_clkrst_lp_rst_en_reg_t;
 
 /** Type of reset_cause register
- *  Represents the reset casue
+ *  Represents the reset cause
  */
 typedef union {
     struct {

components/soc/esp32c61/register/soc/pmu_struct.h

@@ -11,7 +11,7 @@
 extern "C" {
 #endif
 
-#include "soc.h"
+#include "soc/soc.h"
 #include "soc/pmu_reg.h"
 
 typedef union {

components/soc/esp32c61/register/soc/sha_reg.h

@@ -161,7 +161,7 @@ extern "C" {
 #define SHA_DATE_S  0
 
 /** SHA_H_MEM register
- *  Sha H memory which contains intermediate hash or finial hash.
+ *  Sha H memory which contains intermediate hash or final hash.
  */
 #define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
 #define SHA_H_MEM_SIZE_BYTES 64

components/soc/esp32c61/register/soc/spi_reg.h

@@ -273,7 +273,7 @@ extern "C" {
 /** SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1;
  *  Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\
  *  0: SPI_CLK is divided from APB_CLK.\\
- *  1: SPI_CLK is eqaul to APB_CLK.\\
+ *  1: SPI_CLK is equal to APB_CLK.\\
  *  Can be configured in CONF state.
  */
 #define SPI_CLK_EQU_SYSCLK    (BIT(31))

components/soc/esp32c61/register/soc/spi_struct.h

@@ -819,7 +819,7 @@ typedef union {
         /** clk_equ_sysclk : R/W; bitpos: [31]; default: 1;
          *  Configures whether or not the SPI_CLK is equal to APB_CLK in master transfer.\\
          *  0: SPI_CLK is divided from APB_CLK.\\
-         *  1: SPI_CLK is eqaul to APB_CLK.\\
+         *  1: SPI_CLK is equal to APB_CLK.\\
          *  Can be configured in CONF state.
          */
         uint32_t clk_equ_sysclk:1;

components/soc/esp32c61/register/soc/trace_reg.h

@@ -76,7 +76,7 @@ extern "C" {
 #define TRACE_FIFO_EMPTY_S  0
 /** TRACE_WORK_STATUS : RO; bitpos: [2:1]; default: 0;
  *  Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait
- *  state becasue hart is halted or in reset \\3: Lost state\\
+ *  state because hart is halted or in reset \\3: Lost state\\
  */
 #define TRACE_WORK_STATUS    0x00000003U
 #define TRACE_WORK_STATUS_M  (TRACE_WORK_STATUS_V << TRACE_WORK_STATUS_S)
@@ -186,7 +186,7 @@ extern "C" {
 #define TRACE_DM_TRIGGER_ENA_V  0x00000001U
 #define TRACE_DM_TRIGGER_ENA_S  0
 /** TRACE_RESET_ENA : R/W; bitpos: [1]; default: 0;
- *  Configure whether to reset, when enabeld, if cpu have reset, the encoder will
+ *  Configure whether to reset, when enabled, if cpu have reset, the encoder will
  *  output a packet to report the address of the last instruction, and upon reset
  *  deassertion, the encoder start again.\\0: Disable\\0: Enable\\
  */
@@ -216,7 +216,7 @@ extern "C" {
 #define TRACE_FULL_ADDRESS_V  0x00000001U
 #define TRACE_FULL_ADDRESS_S  4
 /** TRACE_IMPLICIT_EXCEPT : R/W; bitpos: [5]; default: 0;
- *  Configure whether or not enabel implicit exception mode. When enabled,, do not sent
+ *  Configure whether or not enable implicit exception mode. When enabled,, do not sent
  *  exception address, only exception cause in exception packets.\\1: enabled\\0:
  *  disabled\\
  */
@@ -418,7 +418,7 @@ extern "C" {
  */
 #define TRACE_AHB_CONFIG_REG (DR_REG_TRACE_BASE + 0x40)
 /** TRACE_HBURST : R/W; bitpos: [2:0]; default: 0;
- *  Configures the AHB burst mode. \\0: SIGNLE \\1: INCR(length not defined) \\2:INCR4
+ *  Configures the AHB burst mode. \\0: SINGLE \\1: INCR(length not defined) \\2:INCR4
  *  \\4:INCR8 \\Others:Invalid
  */
 #define TRACE_HBURST    0x00000007U
@@ -440,7 +440,7 @@ extern "C" {
 /** TRACE_CLK_EN : R/W; bitpos: [0]; default: 1;
  *  Configures register clock gating. \\0: Support clock only when the application
  *  writes registers to save power. \\1:Always force the clock on for registers \\ This
- *  bit does't affect register access.
+ *  bit doesn't affect register access.
  */
 #define TRACE_CLK_EN    (BIT(0))
 #define TRACE_CLK_EN_M  (TRACE_CLK_EN_V << TRACE_CLK_EN_S)

components/soc/esp32c61/register/soc/trace_struct.h

@@ -81,7 +81,7 @@ typedef union {
         uint32_t fifo_empty:1;
         /** work_status : RO; bitpos: [2:1]; default: 0;
          *  Represent the state of the encoder: \\0: Idle state \\1: Working state\\ 2: Wait
-         *  state becasue hart is halted or in reset \\3: Lost state\\
+         *  state because hart is halted or in reset \\3: Lost state\\
          */
         uint32_t work_status:2;
         uint32_t reserved_3:29;
@@ -184,7 +184,7 @@ typedef union {
          */
         uint32_t dm_trigger_ena:1;
         /** reset_ena : R/W; bitpos: [1]; default: 0;
-         *  Configure whether to reset, when enabeld, if cpu have reset, the encoder will
+         *  Configure whether to reset, when enabled, if cpu have reset, the encoder will
          *  output a packet to report the address of the last instruction, and upon reset
          *  deassertion, the encoder start again.\\0: Disable\\0: Enable\\
          */
@@ -202,7 +202,7 @@ typedef union {
          */
         uint32_t full_address:1;
         /** implicit_except : R/W; bitpos: [5]; default: 0;
-         *  Configure whether or not enabel implicit exception mode. When enabled,, do not sent
+         *  Configure whether or not enable implicit exception mode. When enabled,, do not sent
          *  exception address, only exception cause in exception packets.\\1: enabled\\0:
          *  disabled\\
          */
@@ -381,7 +381,7 @@ typedef union {
 typedef union {
     struct {
         /** hburst : R/W; bitpos: [2:0]; default: 0;
-         *  Configures the AHB burst mode. \\0: SIGNLE \\1: INCR(length not defined) \\2:INCR4
+         *  Configures the AHB burst mode. \\0: SINGLE \\1: INCR(length not defined) \\2:INCR4
          *  \\4:INCR8 \\Others:Invalid
          */
         uint32_t hburst:3;
@@ -404,7 +404,7 @@ typedef union {
         /** clk_en : R/W; bitpos: [0]; default: 1;
          *  Configures register clock gating. \\0: Support clock only when the application
          *  writes registers to save power. \\1:Always force the clock on for registers \\ This
-         *  bit does't affect register access.
+         *  bit doesn't affect register access.
          */
         uint32_t clk_en:1;
         uint32_t reserved_1:31;

components/soc/esp32c61/register/soc/usb_serial_jtag_reg.h

@@ -1144,7 +1144,7 @@ extern "C" {
 #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_V  0x00000001U
 #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_RESET_RD_S  3
 /** USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY : RO; bitpos: [4]; default: 1;
- *  CDC_ACM OUTOUT async FIFO empty signal in read clock domain.
+ *  CDC_ACM OUTPUT async FIFO empty signal in read clock domain.
  */
 #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY    (BIT(4))
 #define USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_M  (USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_V << USB_SERIAL_JTAG_SERIAL_OUT_AFIFO_REMPTY_S)

components/soc/esp32c61/register/soc/xts_aes_reg.h

@@ -32,7 +32,7 @@ s. Please do not use this field..*/
 
 #define XTS_AES_DESTINATION_REG(i)          (REG_SPI_MEM_BASE(i) + 0x344)
 /* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
-/*description: This bit stores the destination parameter which will be used in manual encryptio
+/*description: This bit stores the destination parameter which will be used in manual encryption
 n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
 used..*/
 #define XTS_AES_DESTINATION    (BIT(0))
@@ -54,7 +54,7 @@ size parameter..*/
 /* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
 /*description: Set this bit to trigger the process of manual encryption calculation. This actio
 n should only be asserted when manual encryption status is 0. After this action,
- manual encryption status becomes 1. After calculation is done, manual encryptio
+ manual encryption status becomes 1. After calculation is done, manual encryption
 n status becomes 2..*/
 #define XTS_AES_TRIGGER    (BIT(0))
 #define XTS_AES_TRIGGER_M  (BIT(0))
@@ -115,7 +115,7 @@ ing key 1..*/
 #define XTS_AES_CRYPT_CALC_D_DPA_EN_V  0x1
 #define XTS_AES_CRYPT_CALC_D_DPA_EN_S  3
 /* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
-/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
+/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-
 7: The bigger the number is, the more secure the cryption is. (Note that the per
 formance of cryption will decrease together with this number increasing).*/
 #define XTS_AES_CRYPT_SECURITY_LEVEL    0x00000007