From f1b0c5dcb4e3669edb7e0e380bb930e35a4d3f9b Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 18 Dec 2024 11:30:51 +0800 Subject: [PATCH] feat(cache): added cache invalidate all ll apis --- components/hal/esp32c2/include/hal/cache_ll.h | 15 +++- components/hal/esp32c3/include/hal/cache_ll.h | 15 +++- components/hal/esp32c5/include/hal/cache_ll.h | 13 ++++ components/hal/esp32c6/include/hal/cache_ll.h | 15 +++- .../hal/esp32c61/include/hal/cache_ll.h | 13 ++++ components/hal/esp32h2/include/hal/cache_ll.h | 15 +++- components/hal/esp32p4/include/hal/cache_ll.h | 74 +++++++++++++++++++ components/hal/esp32s2/include/hal/cache_ll.h | 25 +++++++ components/hal/esp32s3/include/hal/cache_ll.h | 26 +++++++ 9 files changed, 207 insertions(+), 4 deletions(-) diff --git a/components/hal/esp32c2/include/hal/cache_ll.h b/components/hal/esp32c2/include/hal/cache_ll.h index ba192c98b6..50a3952302 100644 --- a/components/hal/esp32c2/include/hal/cache_ll.h +++ b/components/hal/esp32c2/include/hal/cache_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -149,6 +149,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + Cache_Invalidate_ICache_All(); +} + /** * @brief Get Cache line size, in bytes * diff --git a/components/hal/esp32c3/include/hal/cache_ll.h b/components/hal/esp32c3/include/hal/cache_ll.h index 71022d0121..748548079a 100644 --- a/components/hal/esp32c3/include/hal/cache_ll.h +++ b/components/hal/esp32c3/include/hal/cache_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -152,6 +152,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + Cache_Invalidate_ICache_All(); +} + /** * @brief Get Cache line size, in bytes * diff --git a/components/hal/esp32c5/include/hal/cache_ll.h b/components/hal/esp32c5/include/hal/cache_ll.h index 01b0a0097a..642de58d11 100644 --- a/components/hal/esp32c5/include/hal/cache_ll.h +++ b/components/hal/esp32c5/include/hal/cache_ll.h @@ -129,6 +129,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + Cache_Invalidate_All(); +} + /** * @brief Writeback cache supported addr * diff --git a/components/hal/esp32c6/include/hal/cache_ll.h b/components/hal/esp32c6/include/hal/cache_ll.h index 6aa203eb45..683aa3205b 100644 --- a/components/hal/esp32c6/include/hal/cache_ll.h +++ b/components/hal/esp32c6/include/hal/cache_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -127,6 +127,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + Cache_Invalidate_ICache_All(); +} + /** * @brief Freeze Cache * diff --git a/components/hal/esp32c61/include/hal/cache_ll.h b/components/hal/esp32c61/include/hal/cache_ll.h index b324b26792..b636530415 100644 --- a/components/hal/esp32c61/include/hal/cache_ll.h +++ b/components/hal/esp32c61/include/hal/cache_ll.h @@ -128,6 +128,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + Cache_Invalidate_All(); +} + /** * @brief Writeback cache supported addr * diff --git a/components/hal/esp32h2/include/hal/cache_ll.h b/components/hal/esp32h2/include/hal/cache_ll.h index 280e4a489a..f628fdea23 100644 --- a/components/hal/esp32h2/include/hal/cache_ll.h +++ b/components/hal/esp32h2/include/hal/cache_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -127,6 +127,19 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + Cache_Invalidate_ICache_All(); +} + /** * @brief Freeze Cache * diff --git a/components/hal/esp32p4/include/hal/cache_ll.h b/components/hal/esp32p4/include/hal/cache_ll.h index 5e1a07130e..03a5658008 100644 --- a/components/hal/esp32p4/include/hal/cache_ll.h +++ b/components/hal/esp32p4/include/hal/cache_ll.h @@ -556,6 +556,80 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t } } +/** + * @brief Invalidate L1 ICache all + * + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_l1_invalidate_icache_all(uint32_t cache_id) +{ + if (cache_id == 0) { + Cache_Invalidate_All(CACHE_MAP_L1_ICACHE_0); + } else if (cache_id == 1) { + Cache_Invalidate_All(CACHE_MAP_L1_ICACHE_1); + } else if (cache_id == CACHE_LL_ID_ALL) { + Cache_Invalidate_All(CACHE_MAP_L1_ICACHE_MASK); + } +} + +/** + * @brief Invalidate L1 DCache all + * + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_l1_invalidate_dcache_all(uint32_t cache_id) +{ + if (cache_id == 0 || cache_id == CACHE_LL_ID_ALL) { + Cache_Invalidate_All(CACHE_MAP_L1_DCACHE); + } +} + +/** + * @brief Invalidate L2 Cache all + * + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_l2_invalidate_cache_all(uint32_t cache_id) +{ + if (cache_id == 0 || cache_id == CACHE_LL_ID_ALL) { + Cache_Invalidate_All(CACHE_MAP_L2_CACHE); + } +} + +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + if (cache_level == 1 || cache_level == 2 || cache_level == CACHE_LL_LEVEL_ALL) { + switch (type) { + case CACHE_TYPE_INSTRUCTION: + cache_ll_l1_invalidate_icache_all(cache_id); + break; + case CACHE_TYPE_DATA: + cache_ll_l1_invalidate_dcache_all(cache_id); + break; + case CACHE_TYPE_ALL: + default: + cache_ll_l1_invalidate_icache_all(cache_id); + cache_ll_l1_invalidate_dcache_all(cache_id); + break; + } + } + + if (cache_level == 2 || cache_level == CACHE_LL_LEVEL_ALL) { + cache_ll_l2_invalidate_cache_all(cache_id); + } +} + /*------------------------------------------------------------------------------ * Writeback *----------------------------------------------------------------------------*/ diff --git a/components/hal/esp32s2/include/hal/cache_ll.h b/components/hal/esp32s2/include/hal/cache_ll.h index 16f7a7fe90..0bccb5d3d4 100644 --- a/components/hal/esp32s2/include/hal/cache_ll.h +++ b/components/hal/esp32s2/include/hal/cache_ll.h @@ -350,6 +350,31 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + switch (type) + { + case CACHE_TYPE_DATA: + Cache_Invalidate_DCache_All(); + break; + case CACHE_TYPE_INSTRUCTION: + Cache_Invalidate_ICache_All(); + break; + default: //CACHE_TYPE_ALL + Cache_Invalidate_ICache_All(); + Cache_Invalidate_DCache_All(); + break; + } +} + /** * @brief Writeback cache supported addr * diff --git a/components/hal/esp32s3/include/hal/cache_ll.h b/components/hal/esp32s3/include/hal/cache_ll.h index 9ab5b7f5ff..b76e9fc816 100644 --- a/components/hal/esp32s3/include/hal/cache_ll.h +++ b/components/hal/esp32s3/include/hal/cache_ll.h @@ -360,6 +360,32 @@ static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t t Cache_Invalidate_Addr(vaddr, size); } +/** + * @brief Invalidate all + * + * @param cache_level level of the cache + * @param type see `cache_type_t` + * @param cache_id id of the cache in this type and level + */ +__attribute__((always_inline)) +static inline void cache_ll_invalidate_all(uint32_t cache_level, cache_type_t type, uint32_t cache_id) +{ + switch (type) + { + case CACHE_TYPE_DATA: + Cache_Invalidate_DCache_All(); + break; + case CACHE_TYPE_INSTRUCTION: + Cache_Invalidate_ICache_All(); + break; + default: //CACHE_TYPE_ALL + Cache_Invalidate_ICache_All(); + Cache_Invalidate_DCache_All(); + break; + } +} + + /** * @brief Writeback cache supported addr *