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Merge branch 'bugfix/fix_i2s_ll_cpp_compilation_failure_v5.0' into 'release/v5.0'

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i2s: fixed i2s_ll compiling failure under C++ environment (v5.0)

See merge request espressif/esp-idf!24402
This commit is contained in:
morris 2023-07-12 10:08:23 +08:00
commit f7b97b53c6
11 changed files with 396 additions and 540 deletions
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2
components/driver/i2s/i2s_pdm.c
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@ -74,7 +74,7 @@ static esp_err_t i2s_pdm_tx_set_clock(i2s_chan_handle_t handle, const i2s_pdm_tx
#if SOC_I2S_HW_VERSION_2 #if SOC_I2S_HW_VERSION_2
/* Work around for PDM TX clock, overwrite the raw division directly to reduce the noise /* Work around for PDM TX clock, overwrite the raw division directly to reduce the noise
* This set of coefficients is a special division to reduce the background noise in PDM TX mode */ * This set of coefficients is a special division to reduce the background noise in PDM TX mode */
i2s_ll_tx_set_raw_clk_div(handle->controller->hal.dev, 1, 1, 0, 0); i2s_ll_tx_set_raw_clk_div(handle->controller->hal.dev, clk_info.mclk_div, 1, 1, 0, 0);
#endif #endif
portEXIT_CRITICAL(&g_i2s.spinlock); portEXIT_CRITICAL(&g_i2s.spinlock);

9
components/hal/adc_hal.c
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -14,7 +14,7 @@
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
//ADC utilises I2S0 DMA on ESP32 //ADC utilises I2S0 DMA on ESP32
#include "hal/i2s_ll.h" #include "hal/i2s_hal.h"
#include "hal/i2s_types.h" #include "hal/i2s_types.h"
#include "soc/i2s_struct.h" #include "soc/i2s_struct.h"
#endif #endif
@ -184,8 +184,9 @@ static void adc_hal_digi_sample_freq_config(adc_hal_dma_ctx_t *hal, uint32_t fre
uint32_t bclk_div = 16; uint32_t bclk_div = 16;
uint32_t bclk = freq * 2; uint32_t bclk = freq * 2;
uint32_t mclk = bclk * bclk_div; uint32_t mclk = bclk * bclk_div;
uint32_t mclk_div = I2S_BASE_CLK / mclk; i2s_ll_mclk_div_t mclk_div = {};
i2s_ll_rx_set_mclk(hal->dev, I2S_BASE_CLK, mclk, mclk_div); i2s_hal_calc_mclk_precise_division(I2S_BASE_CLK, mclk, &mclk_div);
i2s_ll_rx_set_mclk(hal->dev, &mclk_div);
i2s_ll_rx_set_bck_div_num(hal->dev, bclk_div); i2s_ll_rx_set_bck_div_num(hal->dev, bclk_div);
#endif #endif
} }

93
components/hal/esp32/include/hal/i2s_ll.h
View File

@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -45,11 +45,14 @@ extern "C" {
#define I2S_LL_TX_EVENT_MASK I2S_LL_EVENT_TX_EOF #define I2S_LL_TX_EVENT_MASK I2S_LL_EVENT_TX_EOF
#define I2S_LL_RX_EVENT_MASK I2S_LL_EVENT_RX_EOF #define I2S_LL_RX_EVENT_MASK I2S_LL_EVENT_RX_EOF
/* I2S clock configuration structure */ /**
* @brief I2S clock configuration structure
* @note Fmclk = Fsclk /(integ+numer/denom)
*/
typedef struct { typedef struct {
uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a) uint16_t integ; // Integer part of I2S module clock divider
uint16_t a; uint16_t denom; // Denominator part of I2S module clock divider
uint16_t b; // The decimal part of module clock divider, the decimal is: b/a uint16_t numer; // Numerator part of I2S module clock divider
} i2s_ll_mclk_div_t; } i2s_ll_mclk_div_t;
/** /**
@ -282,54 +285,6 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
hw->sample_rate_conf.tx_bck_div_num = val; hw->sample_rate_conf.tx_bck_div_num = val;
} }
/**
* @brief Configure I2S TX module clock divider
* @note mclk on ESP32 is shared by both TX and RX channel
*
* @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll
* @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk
*/
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
{
int ma = 0;
int mb = 0;
int denominator = 1;
int numerator = 0;
uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
if (!freq_diff) {
goto finish;
}
float decimal = freq_diff / (float)mclk;
// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
if (decimal > 125.0 / 126.0) {
mclk_div++;
goto finish;
}
uint32_t min = ~0;
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
ma = freq_diff * a;
mb = mclk * b;
if (ma == mb) {
denominator = a;
numerator = b;
goto finish;
}
if (abs((mb - ma)) < min) {
denominator = a;
numerator = b;
min = abs(mb - ma);
}
}
finish:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkm_conf, clkm_div_num, mclk_div);
hw->clkm_conf.clkm_div_b = numerator;
hw->clkm_conf.clkm_div_a = denominator;
}
/** /**
* @brief Configure I2S module clock divider * @brief Configure I2S module clock divider
* @note mclk on ESP32 is shared by both TX and RX channel * @note mclk on ESP32 is shared by both TX and RX channel
@ -347,6 +302,23 @@ static inline void i2s_ll_set_raw_mclk_div(i2s_dev_t *hw, uint32_t mclk_div, uin
hw->clkm_conf.clkm_div_a = a; hw->clkm_conf.clkm_div_a = a;
} }
/**
* @brief Configure I2S TX module clock divider
* @note mclk on ESP32 is shared by both TX and RX channel
*
* @param hw Peripheral I2S hardware instance address.
* @param mclk_div The mclk division coefficients
*/
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
{
/* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
* Set to particular coefficients first then update to the target coefficients,
* otherwise the clock division might be inaccurate.
* the general idea is to set a value that unlike to calculate from the regular decimal */
i2s_ll_set_raw_mclk_div(hw, 7, 47, 3);
i2s_ll_set_raw_mclk_div(hw, mclk_div->integ, mclk_div->denom, mclk_div->numer);
}
/** /**
* @brief Set I2S rx bck div num * @brief Set I2S rx bck div num
* *
@ -363,13 +335,12 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
* @note mclk on ESP32 is shared by both TX and RX channel * @note mclk on ESP32 is shared by both TX and RX channel
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll * @param mclk_div The mclk division coefficients
* @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk
*/ */
static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div) static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
{ {
i2s_ll_tx_set_mclk(hw, sclk, mclk, mclk_div); // TX and RX channel on ESP32 shares a same mclk
i2s_ll_tx_set_mclk(hw, mclk_div);
} }
/** /**
@ -381,11 +352,13 @@ static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mcl
*/ */
static inline void i2s_ll_enable_intr(i2s_dev_t *hw, uint32_t mask, bool en) static inline void i2s_ll_enable_intr(i2s_dev_t *hw, uint32_t mask, bool en)
{ {
uint32_t int_ena_mask = hw->int_ena.val;
if (en) { if (en) {
hw->int_ena.val |= mask; int_ena_mask |= mask;
} else { } else {
hw->int_ena.val &= ~mask; int_ena_mask &= ~mask;
} }
hw->int_ena.val = int_ena_mask;
} }
/** /**

219
components/hal/esp32c3/include/hal/i2s_ll.h
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -32,11 +32,14 @@ extern "C" {
#define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (9) #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (9)
#define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1) #define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
/* I2S clock configuration structure */ /**
* @brief I2S clock configuration structure
* @note Fmclk = Fsclk /(integ+numer/denom)
*/
typedef struct { typedef struct {
uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a) uint16_t integ; // Integer part of I2S module clock divider
uint16_t a; uint16_t denom; // Denominator part of I2S module clock divider
uint16_t b; // The decimal part of module clock divider, the decimal is: b/a uint16_t numer; // Numerator part of I2S module clock divider
} i2s_ll_mclk_div_t; } i2s_ll_mclk_div_t;
/** /**
@ -222,96 +225,74 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
* @brief Set I2S tx raw clock division * @brief Set I2S tx raw clock division
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param div_int Integer part of division
* @param x div x * @param x div x
* @param y div y * @param y div y
* @param z div z * @param z div z
* @param yn1 yn1 * @param yn1 yn1
*/ */
static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1) static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
{ {
hw->tx_clkm_div_conf.tx_clkm_div_x = x; /* Set the integer part of mclk division */
hw->tx_clkm_div_conf.tx_clkm_div_y = y; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, div_int);
hw->tx_clkm_div_conf.tx_clkm_div_z = z; /* Set the decimal part of the mclk division */
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = yn1; typeof(hw->tx_clkm_div_conf) div = {};
div.tx_clkm_div_x = x;
div.tx_clkm_div_y = y;
div.tx_clkm_div_z = z;
div.tx_clkm_div_yn1 = yn1;
hw->tx_clkm_div_conf.val = div.val;
} }
/** /**
* @brief Set I2S rx raw clock division * @brief Set I2S rx raw clock division
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param div_int Integer part of division
* @param x div x * @param x div x
* @param y div y * @param y div y
* @param z div z * @param z div z
* @param yn1 yn1 * @param yn1 yn1
*/ */
static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1) static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
{ {
hw->rx_clkm_div_conf.rx_clkm_div_x = x; /* Set the integer part of mclk division */
hw->rx_clkm_div_conf.rx_clkm_div_y = y; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, div_int);
hw->rx_clkm_div_conf.rx_clkm_div_z = z; /* Set the decimal part of the mclk division */
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = yn1; typeof(hw->rx_clkm_div_conf) div = {};
div.rx_clkm_div_x = x;
div.rx_clkm_div_y = y;
div.rx_clkm_div_z = z;
div.rx_clkm_div_yn1 = yn1;
hw->rx_clkm_div_conf.val = div.val;
} }
/** /**
* @brief Configure I2S TX module clock divider * @brief Configure I2S TX module clock divider
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll * @param mclk_div The mclk division coefficients
* @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk
*/ */
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div) static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
{ {
int ma = 0; /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
int mb = 0; * Set to particular coefficients first then update to the target coefficients,
int denominator = 1; * otherwise the clock division might be inaccurate.
int numerator = 0; * the general idea is to set a value that impossible to calculate from the regular decimal */
i2s_ll_tx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div)); uint32_t div_x = 0;
if (!freq_diff) { uint32_t div_y = 0;
goto finish; uint32_t div_z = 0;
uint32_t div_yn1 = 0;
/* If any of denominator and numerator is 0, set all the coefficients to 0 */
if (mclk_div->denom && mclk_div->numer) {
div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
div_x = mclk_div->denom / div_z - 1;
div_y = mclk_div->denom % div_z;
} }
float decimal = freq_diff / (float)mclk; i2s_ll_tx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
if (decimal > 125.0 / 126.0) {
mclk_div++;
goto finish;
}
uint32_t min = ~0;
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
ma = freq_diff * a;
mb = mclk * b;
if (ma == mb) {
denominator = a;
numerator = b;
goto finish;
}
if (abs((mb - ma)) < min) {
denominator = a;
numerator = b;
min = abs(mb - ma);
}
}
finish:
if (denominator == 0 || numerator == 0) {
hw->tx_clkm_div_conf.tx_clkm_div_x = 0;
hw->tx_clkm_div_conf.tx_clkm_div_y = 0;
hw->tx_clkm_div_conf.tx_clkm_div_z = 0;
} else {
if (numerator > denominator / 2) {
hw->tx_clkm_div_conf.tx_clkm_div_x = denominator / (denominator - numerator) - 1;
hw->tx_clkm_div_conf.tx_clkm_div_y = denominator % (denominator - numerator);
hw->tx_clkm_div_conf.tx_clkm_div_z = denominator - numerator;
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 1;
} else {
hw->tx_clkm_div_conf.tx_clkm_div_x = denominator / numerator - 1;
hw->tx_clkm_div_conf.tx_clkm_div_y = denominator % numerator;
hw->tx_clkm_div_conf.tx_clkm_div_z = numerator;
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 0;
}
}
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, mclk_div);
} }
/** /**
@ -330,62 +311,28 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
* @note mclk on ESP32 is shared by both TX and RX channel * @note mclk on ESP32 is shared by both TX and RX channel
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll * @param mclk_div The mclk division coefficients
* @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk
*/ */
static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div) static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
{ {
int ma = 0; /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
int mb = 0; * Set to particular coefficients first then update to the target coefficients,
int denominator = 1; * otherwise the clock division might be inaccurate.
int numerator = 0; * the general idea is to set a value that impossible to calculate from the regular decimal */
i2s_ll_rx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div)); uint32_t div_x = 0;
if (!freq_diff) { uint32_t div_y = 0;
goto finish; uint32_t div_z = 0;
uint32_t div_yn1 = 0;
/* If any of denominator and numerator is 0, set all the coefficients to 0 */
if (mclk_div->denom && mclk_div->numer) {
div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
div_x = mclk_div->denom / div_z - 1;
div_y = mclk_div->denom % div_z;
} }
float decimal = freq_diff / (float)mclk; i2s_ll_rx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
if (decimal > 125.0 / 126.0) {
mclk_div++;
goto finish;
}
uint32_t min = ~0;
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
ma = freq_diff * a;
mb = mclk * b;
if (ma == mb) {
denominator = a;
numerator = b;
goto finish;
}
if (abs((mb - ma)) < min) {
denominator = a;
numerator = b;
min = abs(mb - ma);
}
}
finish:
if (denominator == 0 || numerator == 0) {
hw->rx_clkm_div_conf.rx_clkm_div_x = 0;
hw->rx_clkm_div_conf.rx_clkm_div_y = 0;
hw->rx_clkm_div_conf.rx_clkm_div_z = 0;
} else {
if (numerator > denominator / 2) {
hw->rx_clkm_div_conf.rx_clkm_div_x = denominator / (denominator - numerator) - 1;
hw->rx_clkm_div_conf.rx_clkm_div_y = denominator % (denominator - numerator);
hw->rx_clkm_div_conf.rx_clkm_div_z = denominator - numerator;
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 1;
} else {
hw->rx_clkm_div_conf.rx_clkm_div_x = denominator / numerator - 1;
hw->rx_clkm_div_conf.rx_clkm_div_y = denominator % numerator;
hw->rx_clkm_div_conf.rx_clkm_div_z = numerator;
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 0;
}
}
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, mclk_div);
} }
/** /**
@ -565,10 +512,10 @@ static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num)
*/ */
static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask) static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
{ {
typeof(hw->tx_tdm_ctrl) tdm_ctrl_reg = hw->tx_tdm_ctrl; uint32_t tdm_ctrl = hw->tx_tdm_ctrl.val;
tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK; tdm_ctrl &= 0xFFFF0000;
tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK; tdm_ctrl |= chan_mask;
hw->tx_tdm_ctrl.val = tdm_ctrl_reg.val; hw->tx_tdm_ctrl.val = tdm_ctrl;
} }
/** /**
@ -579,10 +526,10 @@ static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_m
*/ */
static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask) static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
{ {
typeof(hw->rx_tdm_ctrl) tdm_ctrl_reg = hw->rx_tdm_ctrl; uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val;
tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK; tdm_ctrl &= 0xFFFF0000;
tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK; tdm_ctrl |= chan_mask;
hw->rx_tdm_ctrl.val = tdm_ctrl_reg.val; hw->rx_tdm_ctrl.val = tdm_ctrl;
} }
/** /**
@ -596,21 +543,22 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
/* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
* Otherwise always enable the first two slots */ * Otherwise always enable the first two slots */
hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1 hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1
hw->tx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK; uint32_t chan_mask = 0;
switch (slot_mask) switch (slot_mask)
{ {
case I2S_STD_SLOT_LEFT: case I2S_STD_SLOT_LEFT:
hw->tx_tdm_ctrl.val |= 0x01; chan_mask |= 0x01;
break; break;
case I2S_STD_SLOT_RIGHT: case I2S_STD_SLOT_RIGHT:
hw->tx_tdm_ctrl.val |= 0x02; chan_mask |= 0x02;
break; break;
case I2S_STD_SLOT_BOTH: case I2S_STD_SLOT_BOTH:
hw->tx_tdm_ctrl.val |= 0x03; chan_mask |= 0x03;
break; break;
default: default:
break; break;
} }
i2s_ll_tx_set_active_chan_mask(hw, chan_mask);
} }
/** /**
@ -624,21 +572,22 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
/* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
* Otherwise always enable the first two slots */ * Otherwise always enable the first two slots */
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1 hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
hw->rx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK; uint32_t chan_mask = 0;
switch (slot_mask) switch (slot_mask)
{ {
case I2S_STD_SLOT_LEFT: case I2S_STD_SLOT_LEFT:
hw->rx_tdm_ctrl.val |= 0x01; chan_mask |= 0x01;
break; break;
case I2S_STD_SLOT_RIGHT: case I2S_STD_SLOT_RIGHT:
hw->rx_tdm_ctrl.val |= 0x02; chan_mask |= 0x02;
break; break;
case I2S_STD_SLOT_BOTH: case I2S_STD_SLOT_BOTH:
hw->rx_tdm_ctrl.val |= 0x03; chan_mask |= 0x03;
break; break;
default: default:
break; break;
} }
i2s_ll_rx_set_active_chan_mask(hw, chan_mask);
} }
/** /**

219
components/hal/esp32h2/include/hal/i2s_ll.h
View File

@ -34,11 +34,14 @@ extern "C" {
#define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (9) #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (9)
#define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1) #define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
/* I2S clock configuration structure */ /**
* @brief I2S clock configuration structure
* @note Fmclk = Fsclk /(integ+numer/denom)
*/
typedef struct { typedef struct {
uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a) uint16_t integ; // Integer part of I2S module clock divider
uint16_t a; uint16_t denom; // Denominator part of I2S module clock divider
uint16_t b; // The decimal part of module clock divider, the decimal is: b/a uint16_t numer; // Numerator part of I2S module clock divider
} i2s_ll_mclk_div_t; } i2s_ll_mclk_div_t;
/** /**
@ -224,96 +227,74 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
* @brief Set I2S tx raw clock division * @brief Set I2S tx raw clock division
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param div_int Integer part of division
* @param x div x * @param x div x
* @param y div y * @param y div y
* @param z div z * @param z div z
* @param yn1 yn1 * @param yn1 yn1
*/ */
static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1) static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
{ {
hw->tx_clkm_div_conf.tx_clkm_div_x = x; /* Set the integer part of mclk division */
hw->tx_clkm_div_conf.tx_clkm_div_y = y; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, div_int);
hw->tx_clkm_div_conf.tx_clkm_div_z = z; /* Set the decimal part of the mclk division */
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = yn1; typeof(hw->tx_clkm_div_conf) div = {};
div.tx_clkm_div_x = x;
div.tx_clkm_div_y = y;
div.tx_clkm_div_z = z;
div.tx_clkm_div_yn1 = yn1;
hw->tx_clkm_div_conf.val = div.val;
} }
/** /**
* @brief Set I2S rx raw clock division * @brief Set I2S rx raw clock division
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param div_int Integer part of division
* @param x div x * @param x div x
* @param y div y * @param y div y
* @param z div z * @param z div z
* @param yn1 yn1 * @param yn1 yn1
*/ */
static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1) static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
{ {
hw->rx_clkm_div_conf.rx_clkm_div_x = x; /* Set the integer part of mclk division */
hw->rx_clkm_div_conf.rx_clkm_div_y = y; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, div_int);
hw->rx_clkm_div_conf.rx_clkm_div_z = z; /* Set the decimal part of the mclk division */
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = yn1; typeof(hw->rx_clkm_div_conf) div = {};
div.rx_clkm_div_x = x;
div.rx_clkm_div_y = y;
div.rx_clkm_div_z = z;
div.rx_clkm_div_yn1 = yn1;
hw->rx_clkm_div_conf.val = div.val;
} }
/** /**
* @brief Configure I2S TX module clock divider * @brief Configure I2S TX module clock divider
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll * @param mclk_div The mclk division coefficients
* @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk
*/ */
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div) static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
{ {
int ma = 0; /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
int mb = 0; * Set to particular coefficients first then update to the target coefficients,
int denominator = 1; * otherwise the clock division might be inaccurate.
int numerator = 0; * the general idea is to set a value that impossible to calculate from the regular decimal */
i2s_ll_tx_set_raw_clk_div(hw, 8, 1, 1, 73, 1);
uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div)); uint32_t div_x = 0;
if (!freq_diff) { uint32_t div_y = 0;
goto finish; uint32_t div_z = 0;
uint32_t div_yn1 = 0;
/* If any of denominator and numerator is 0, set all the coefficients to 0 */
if (mclk_div->denom && mclk_div->numer) {
div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
div_x = mclk_div->denom / div_z - 1;
div_y = mclk_div->denom % div_z;
} }
float decimal = freq_diff / (float)mclk; i2s_ll_tx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
if (decimal > 125.0 / 126.0) {
mclk_div++;
goto finish;
}
uint32_t min = ~0;
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
ma = freq_diff * a;
mb = mclk * b;
if (ma == mb) {
denominator = a;
numerator = b;
goto finish;
}
if (abs((mb - ma)) < min) {
denominator = a;
numerator = b;
min = abs(mb - ma);
}
}
finish:
if (denominator == 0 || numerator == 0) {
hw->tx_clkm_div_conf.tx_clkm_div_x = 0;
hw->tx_clkm_div_conf.tx_clkm_div_y = 0;
hw->tx_clkm_div_conf.tx_clkm_div_z = 0;
} else {
if (numerator > denominator / 2) {
hw->tx_clkm_div_conf.tx_clkm_div_x = denominator / (denominator - numerator) - 1;
hw->tx_clkm_div_conf.tx_clkm_div_y = denominator % (denominator - numerator);
hw->tx_clkm_div_conf.tx_clkm_div_z = denominator - numerator;
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 1;
} else {
hw->tx_clkm_div_conf.tx_clkm_div_x = denominator / numerator - 1;
hw->tx_clkm_div_conf.tx_clkm_div_y = denominator % numerator;
hw->tx_clkm_div_conf.tx_clkm_div_z = numerator;
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 0;
}
}
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, mclk_div);
} }
/** /**
@ -332,62 +313,28 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
* @note mclk on ESP32 is shared by both TX and RX channel * @note mclk on ESP32 is shared by both TX and RX channel
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll * @param mclk_div The mclk division coefficients
* @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk
*/ */
static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div) static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
{ {
int ma = 0; /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
int mb = 0; * Set to particular coefficients first then update to the target coefficients,
int denominator = 1; * otherwise the clock division might be inaccurate.
int numerator = 0; * the general idea is to set a value that impossible to calculate from the regular decimal */
i2s_ll_rx_set_raw_clk_div(hw, 8, 1, 1, 73, 1);
uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div)); uint32_t div_x = 0;
if (!freq_diff) { uint32_t div_y = 0;
goto finish; uint32_t div_z = 0;
uint32_t div_yn1 = 0;
/* If any of denominator and numerator is 0, set all the coefficients to 0 */
if (mclk_div->denom && mclk_div->numer) {
div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
div_x = mclk_div->denom / div_z - 1;
div_y = mclk_div->denom % div_z;
} }
float decimal = freq_diff / (float)mclk; i2s_ll_rx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
if (decimal > 125.0 / 126.0) {
mclk_div++;
goto finish;
}
uint32_t min = ~0;
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
ma = freq_diff * a;
mb = mclk * b;
if (ma == mb) {
denominator = a;
numerator = b;
goto finish;
}
if (abs((mb - ma)) < min) {
denominator = a;
numerator = b;
min = abs(mb - ma);
}
}
finish:
if (denominator == 0 || numerator == 0) {
hw->rx_clkm_div_conf.rx_clkm_div_x = 0;
hw->rx_clkm_div_conf.rx_clkm_div_y = 0;
hw->rx_clkm_div_conf.rx_clkm_div_z = 0;
} else {
if (numerator > denominator / 2) {
hw->rx_clkm_div_conf.rx_clkm_div_x = denominator / (denominator - numerator) - 1;
hw->rx_clkm_div_conf.rx_clkm_div_y = denominator % (denominator - numerator);
hw->rx_clkm_div_conf.rx_clkm_div_z = denominator - numerator;
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 1;
} else {
hw->rx_clkm_div_conf.rx_clkm_div_x = denominator / numerator - 1;
hw->rx_clkm_div_conf.rx_clkm_div_y = denominator % numerator;
hw->rx_clkm_div_conf.rx_clkm_div_z = numerator;
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 0;
}
}
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, mclk_div);
} }
/** /**
@ -435,7 +382,7 @@ static inline void i2s_ll_rx_stop(i2s_dev_t *hw)
} }
/** /**
* @brief Configure TX WS signal width * @brief Start I2S TX
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param width WS width in BCK cycle * @param width WS width in BCK cycle
@ -567,10 +514,10 @@ static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num)
*/ */
static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask) static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
{ {
typeof(hw->tx_tdm_ctrl) tdm_ctrl_reg = hw->tx_tdm_ctrl; uint32_t tdm_ctrl = hw->tx_tdm_ctrl.val;
tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK; tdm_ctrl &= 0xFFFF0000;
tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK; tdm_ctrl |= chan_mask;
hw->tx_tdm_ctrl.val = tdm_ctrl_reg.val; hw->tx_tdm_ctrl.val = tdm_ctrl;
} }
/** /**
@ -581,10 +528,10 @@ static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_m
*/ */
static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask) static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
{ {
typeof(hw->rx_tdm_ctrl) tdm_ctrl_reg = hw->rx_tdm_ctrl; uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val;
tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK; tdm_ctrl &= 0xFFFF0000;
tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK; tdm_ctrl |= chan_mask;
hw->rx_tdm_ctrl.val = tdm_ctrl_reg.val; hw->rx_tdm_ctrl.val = tdm_ctrl;
} }
/** /**
@ -598,21 +545,22 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
/* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
* Otherwise always enable the first two slots */ * Otherwise always enable the first two slots */
hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1 hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1
hw->tx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK; uint32_t chan_mask = 0;
switch (slot_mask) switch (slot_mask)
{ {
case I2S_STD_SLOT_LEFT: case I2S_STD_SLOT_LEFT:
hw->tx_tdm_ctrl.val |= 0x01; chan_mask |= 0x01;
break; break;
case I2S_STD_SLOT_RIGHT: case I2S_STD_SLOT_RIGHT:
hw->tx_tdm_ctrl.val |= 0x02; chan_mask |= 0x02;
break; break;
case I2S_STD_SLOT_BOTH: case I2S_STD_SLOT_BOTH:
hw->tx_tdm_ctrl.val |= 0x03; chan_mask |= 0x03;
break; break;
default: default:
break; break;
} }
i2s_ll_tx_set_active_chan_mask(hw, chan_mask);
} }
/** /**
@ -626,21 +574,22 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
/* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
* Otherwise always enable the first two slots */ * Otherwise always enable the first two slots */
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1 hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
hw->rx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK; uint32_t chan_mask = 0;
switch (slot_mask) switch (slot_mask)
{ {
case I2S_STD_SLOT_LEFT: case I2S_STD_SLOT_LEFT:
hw->rx_tdm_ctrl.val |= 0x01; chan_mask |= 0x01;
break; break;
case I2S_STD_SLOT_RIGHT: case I2S_STD_SLOT_RIGHT:
hw->rx_tdm_ctrl.val |= 0x02; chan_mask |= 0x02;
break; break;
case I2S_STD_SLOT_BOTH: case I2S_STD_SLOT_BOTH:
hw->rx_tdm_ctrl.val |= 0x03; chan_mask |= 0x03;
break; break;
default: default:
break; break;
} }
i2s_ll_rx_set_active_chan_mask(hw, chan_mask);
} }
/** /**

98
components/hal/esp32s2/include/hal/i2s_ll.h
View File

@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -44,11 +44,14 @@ extern "C" {
#define I2S_LL_TX_EVENT_MASK I2S_LL_EVENT_TX_EOF #define I2S_LL_TX_EVENT_MASK I2S_LL_EVENT_TX_EOF
#define I2S_LL_RX_EVENT_MASK I2S_LL_EVENT_RX_EOF #define I2S_LL_RX_EVENT_MASK I2S_LL_EVENT_RX_EOF
/* I2S clock configuration structure */ /**
* @brief I2S clock configuration structure
* @note Fmclk = Fsclk /(integ+numer/denom)
*/
typedef struct { typedef struct {
uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a) uint16_t integ; // Integer part of I2S module clock divider
uint16_t a; uint16_t denom; // Denominator part of I2S module clock divider
uint16_t b; // The decimal part of module clock divider, the decimal is: b/a uint16_t numer; // Numerator part of I2S module clock divider
} i2s_ll_mclk_div_t; } i2s_ll_mclk_div_t;
/** /**
@ -275,57 +278,9 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
hw->sample_rate_conf.tx_bck_div_num = val; hw->sample_rate_conf.tx_bck_div_num = val;
} }
/**
* @brief Configure I2S TX module clock divider
* @note mclk on ESP32S2 is shared by both TX and RX channel
*
* @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll
* @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk
*/
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div)
{
int ma = 0;
int mb = 0;
int denominator = 1;
int numerator = 0;
uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div));
if (!freq_diff) {
goto finish;
}
float decimal = freq_diff / (float)mclk;
// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
if (decimal > 125.0 / 126.0) {
mclk_div++;
goto finish;
}
uint32_t min = ~0;
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
ma = freq_diff * a;
mb = mclk * b;
if (ma == mb) {
denominator = a;
numerator = b;
goto finish;
}
if (abs((mb - ma)) < min) {
denominator = a;
numerator = b;
min = abs(mb - ma);
}
}
finish:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clkm_conf, clkm_div_num, mclk_div);
hw->clkm_conf.clkm_div_b = numerator;
hw->clkm_conf.clkm_div_a = denominator;
}
/** /**
* @brief Configure I2S module clock divider * @brief Configure I2S module clock divider
* @note mclk on ESP32 is shared by both TX and RX channel * @note mclk on ESP32S2 is shared by both TX and RX channel
* mclk = sclk / (mclk_div + b/a) * mclk = sclk / (mclk_div + b/a)
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
@ -340,6 +295,24 @@ static inline void i2s_ll_set_raw_mclk_div(i2s_dev_t *hw, uint32_t mclk_div, uin
hw->clkm_conf.clkm_div_a = a; hw->clkm_conf.clkm_div_a = a;
} }
/**
* @brief Configure I2S TX module clock divider
*
* @note mclk on ESP32 is shared by both TX and RX channel
*
* @param hw Peripheral I2S hardware instance address.
* @param mclk_div The mclk division coefficients
*/
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
{
/* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
* Set to particular coefficients first then update to the target coefficients,
* otherwise the clock division might be inaccurate.
* the general idea is to set a value that unlike to calculate from the regular decimal */
i2s_ll_set_raw_mclk_div(hw, 7, 47, 3);
i2s_ll_set_raw_mclk_div(hw, mclk_div->integ, mclk_div->denom, mclk_div->numer);
}
/** /**
* @brief Set I2S rx bck div num * @brief Set I2S rx bck div num
* *
@ -353,16 +326,15 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
/** /**
* @brief Configure I2S RX module clock divider * @brief Configure I2S RX module clock divider
* @note mclk on ESP32S2 is shared by both TX and RX channel * @note mclk on ESP32 is shared by both TX and RX channel
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll * @param mclk_div The mclk division coefficients
* @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk
*/ */
static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div) static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
{ {
i2s_ll_tx_set_mclk(hw, sclk, mclk, mclk_div); // TX and RX channel on ESP32 shares a same mclk
i2s_ll_tx_set_mclk(hw, mclk_div);
} }
/** /**
@ -374,11 +346,13 @@ static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mcl
*/ */
static inline void i2s_ll_enable_intr(i2s_dev_t *hw, uint32_t mask, bool en) static inline void i2s_ll_enable_intr(i2s_dev_t *hw, uint32_t mask, bool en)
{ {
uint32_t int_ena_mask = hw->int_ena.val;
if (en) { if (en) {
hw->int_ena.val |= mask; int_ena_mask |= mask;
} else { } else {
hw->int_ena.val &= ~mask; int_ena_mask &= ~mask;
} }
hw->int_ena.val = int_ena_mask;
} }
/** /**

220
components/hal/esp32s3/include/hal/i2s_ll.h
View File

@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -33,11 +33,14 @@ extern "C" {
#define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (9) #define I2S_LL_MCLK_DIVIDER_BIT_WIDTH (9)
#define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1) #define I2S_LL_MCLK_DIVIDER_MAX ((1 << I2S_LL_MCLK_DIVIDER_BIT_WIDTH) - 1)
/* I2S clock configuration structure */ /**
* @brief I2S clock configuration structure
* @note Fmclk = Fsclk /(integ+numer/denom)
*/
typedef struct { typedef struct {
uint16_t mclk_div; // I2S module clock divider, Fmclk = Fsclk /(mclk_div+b/a) uint16_t integ; // Integer part of I2S module clock divider
uint16_t a; uint16_t denom; // Denominator part of I2S module clock divider
uint16_t b; // The decimal part of module clock divider, the decimal is: b/a uint16_t numer; // Numerator part of I2S module clock divider
} i2s_ll_mclk_div_t; } i2s_ll_mclk_div_t;
/** /**
@ -225,96 +228,74 @@ static inline void i2s_ll_tx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
* @brief Set I2S tx raw clock division * @brief Set I2S tx raw clock division
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param div_int Integer part of division
* @param x div x * @param x div x
* @param y div y * @param y div y
* @param z div z * @param z div z
* @param yn1 yn1 * @param yn1 yn1
*/ */
static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1) static inline void i2s_ll_tx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
{ {
hw->tx_clkm_div_conf.tx_clkm_div_x = x; /* Set the integer part of mclk division */
hw->tx_clkm_div_conf.tx_clkm_div_y = y; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, div_int);
hw->tx_clkm_div_conf.tx_clkm_div_z = z; /* Set the decimal part of the mclk division */
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = yn1; typeof(hw->tx_clkm_div_conf) div = {};
div.tx_clkm_div_x = x;
div.tx_clkm_div_y = y;
div.tx_clkm_div_z = z;
div.tx_clkm_div_yn1 = yn1;
hw->tx_clkm_div_conf.val = div.val;
} }
/** /**
* @brief Set I2S rx raw clock division * @brief Set I2S rx raw clock division
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param div_int Integer part of division
* @param x div x * @param x div x
* @param y div y * @param y div y
* @param z div z * @param z div z
* @param yn1 yn1 * @param yn1 yn1
*/ */
static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1) static inline void i2s_ll_rx_set_raw_clk_div(i2s_dev_t *hw, uint32_t div_int, uint32_t x, uint32_t y, uint32_t z, uint32_t yn1)
{ {
hw->rx_clkm_div_conf.rx_clkm_div_x = x; /* Set the integer part of mclk division */
hw->rx_clkm_div_conf.rx_clkm_div_y = y; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, div_int);
hw->rx_clkm_div_conf.rx_clkm_div_z = z; /* Set the decimal part of the mclk division */
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = yn1; typeof(hw->rx_clkm_div_conf) div = {};
div.rx_clkm_div_x = x;
div.rx_clkm_div_y = y;
div.rx_clkm_div_z = z;
div.rx_clkm_div_yn1 = yn1;
hw->rx_clkm_div_conf.val = div.val;
} }
/** /**
* @brief Configure I2S TX module clock divider * @brief Configure I2S TX module clock divider
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll * @param mclk_div The mclk division coefficients
* @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk
*/ */
static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div) static inline void i2s_ll_tx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
{ {
int ma = 0; /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
int mb = 0; * Set to particular coefficients first then update to the target coefficients,
int denominator = 1; * otherwise the clock division might be inaccurate.
int numerator = 0; * the general idea is to set a value that impossible to calculate from the regular decimal */
i2s_ll_tx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div)); uint32_t div_x = 0;
if (!freq_diff) { uint32_t div_y = 0;
goto finish; uint32_t div_z = 0;
uint32_t div_yn1 = 0;
/* If any of denominator and numerator is 0, set all the coefficients to 0 */
if (mclk_div->denom && mclk_div->numer) {
div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
div_x = mclk_div->denom / div_z - 1;
div_y = mclk_div->denom % div_z;
} }
float decimal = freq_diff / (float)mclk; i2s_ll_tx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
if (decimal > 125.0 / 126.0) {
mclk_div++;
goto finish;
}
uint32_t min = ~0;
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
ma = freq_diff * a;
mb = mclk * b;
if (ma == mb) {
denominator = a;
numerator = b;
goto finish;
}
if (abs((mb - ma)) < min) {
denominator = a;
numerator = b;
min = abs(mb - ma);
}
}
finish:
if (denominator == 0 || numerator == 0) {
hw->tx_clkm_div_conf.tx_clkm_div_x = 0;
hw->tx_clkm_div_conf.tx_clkm_div_y = 0;
hw->tx_clkm_div_conf.tx_clkm_div_z = 0;
} else {
if (numerator > denominator / 2) {
hw->tx_clkm_div_conf.tx_clkm_div_x = denominator / (denominator - numerator) - 1;
hw->tx_clkm_div_conf.tx_clkm_div_y = denominator % (denominator - numerator);
hw->tx_clkm_div_conf.tx_clkm_div_z = denominator - numerator;
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 1;
} else {
hw->tx_clkm_div_conf.tx_clkm_div_x = denominator / numerator - 1;
hw->tx_clkm_div_conf.tx_clkm_div_y = denominator % numerator;
hw->tx_clkm_div_conf.tx_clkm_div_z = numerator;
hw->tx_clkm_div_conf.tx_clkm_div_yn1 = 0;
}
}
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->tx_clkm_conf, tx_clkm_div_num, mclk_div);
} }
/** /**
@ -333,64 +314,31 @@ static inline void i2s_ll_rx_set_bck_div_num(i2s_dev_t *hw, uint32_t val)
* @note mclk on ESP32 is shared by both TX and RX channel * @note mclk on ESP32 is shared by both TX and RX channel
* *
* @param hw Peripheral I2S hardware instance address. * @param hw Peripheral I2S hardware instance address.
* @param sclk system clock, 0 means use apll * @param mclk_div The mclk division coefficients
* @param mclk module clock
* @param mclk_div integer part of the division from sclk to mclk
*/ */
static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, uint32_t sclk, uint32_t mclk, uint32_t mclk_div) static inline void i2s_ll_rx_set_mclk(i2s_dev_t *hw, const i2s_ll_mclk_div_t *mclk_div)
{ {
int ma = 0; /* Workaround for inaccurate clock while switching from a relatively low sample rate to a high sample rate
int mb = 0; * Set to particular coefficients first then update to the target coefficients,
int denominator = 1; * otherwise the clock division might be inaccurate.
int numerator = 0; * the general idea is to set a value that impossible to calculate from the regular decimal */
i2s_ll_rx_set_raw_clk_div(hw, 7, 317, 7, 3, 0);
uint32_t freq_diff = abs((int)sclk - (int)(mclk * mclk_div)); uint32_t div_x = 0;
if (!freq_diff) { uint32_t div_y = 0;
goto finish; uint32_t div_z = 0;
uint32_t div_yn1 = 0;
/* If any of denominator and numerator is 0, set all the coefficients to 0 */
if (mclk_div->denom && mclk_div->numer) {
div_yn1 = mclk_div->numer * 2 > mclk_div->denom;
div_z = div_yn1 ? mclk_div->denom - mclk_div->numer : mclk_div->numer;
div_x = mclk_div->denom / div_z - 1;
div_y = mclk_div->denom % div_z;
} }
float decimal = freq_diff / (float)mclk; i2s_ll_rx_set_raw_clk_div(hw, mclk_div->integ, div_x, div_y, div_z, div_yn1);
// Carry bit if the decimal is greater than 1.0 - 1.0 / (63.0 * 2) = 125.0 / 126.0
if (decimal > 125.0 / 126.0) {
mclk_div++;
goto finish;
}
uint32_t min = ~0;
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
ma = freq_diff * a;
mb = mclk * b;
if (ma == mb) {
denominator = a;
numerator = b;
goto finish;
}
if (abs((mb - ma)) < min) {
denominator = a;
numerator = b;
min = abs(mb - ma);
}
}
finish:
if (denominator == 0 || numerator == 0) {
hw->rx_clkm_div_conf.rx_clkm_div_x = 0;
hw->rx_clkm_div_conf.rx_clkm_div_y = 0;
hw->rx_clkm_div_conf.rx_clkm_div_z = 0;
} else {
if (numerator > denominator / 2) {
hw->rx_clkm_div_conf.rx_clkm_div_x = denominator / (denominator - numerator) - 1;
hw->rx_clkm_div_conf.rx_clkm_div_y = denominator % (denominator - numerator);
hw->rx_clkm_div_conf.rx_clkm_div_z = denominator - numerator;
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 1;
} else {
hw->rx_clkm_div_conf.rx_clkm_div_x = denominator / numerator - 1;
hw->rx_clkm_div_conf.rx_clkm_div_y = denominator % numerator;
hw->rx_clkm_div_conf.rx_clkm_div_z = numerator;
hw->rx_clkm_div_conf.rx_clkm_div_yn1 = 0;
}
}
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->rx_clkm_conf, rx_clkm_div_num, mclk_div);
} }
/** /**
* @brief Start I2S TX * @brief Start I2S TX
* *
@ -568,10 +516,10 @@ static inline void i2s_ll_rx_set_chan_num(i2s_dev_t *hw, int total_num)
*/ */
static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask) static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
{ {
typeof(hw->tx_tdm_ctrl) tdm_ctrl_reg = hw->tx_tdm_ctrl; uint32_t tdm_ctrl = hw->tx_tdm_ctrl.val;
tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK; tdm_ctrl &= 0xFFFF0000;
tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK; tdm_ctrl |= chan_mask;
hw->tx_tdm_ctrl.val = tdm_ctrl_reg.val; hw->tx_tdm_ctrl.val = tdm_ctrl;
} }
/** /**
@ -582,10 +530,10 @@ static inline void i2s_ll_tx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_m
*/ */
static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask) static inline void i2s_ll_rx_set_active_chan_mask(i2s_dev_t *hw, uint32_t chan_mask)
{ {
typeof(hw->rx_tdm_ctrl) tdm_ctrl_reg = hw->rx_tdm_ctrl; uint32_t tdm_ctrl = hw->rx_tdm_ctrl.val;
tdm_ctrl_reg.val &= ~I2S_LL_TDM_CH_MASK; tdm_ctrl &= 0xFFFF0000;
tdm_ctrl_reg.val |= chan_mask & I2S_LL_TDM_CH_MASK; tdm_ctrl |= chan_mask;
hw->rx_tdm_ctrl.val = tdm_ctrl_reg.val; hw->rx_tdm_ctrl.val = tdm_ctrl;
} }
/** /**
@ -599,21 +547,22 @@ static inline void i2s_ll_tx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
/* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
* Otherwise always enable the first two slots */ * Otherwise always enable the first two slots */
hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1 hw->tx_tdm_ctrl.tx_tdm_tot_chan_num = 1; // tx_tdm_tot_chan_num = 2 slots - 1 = 1
hw->tx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK; uint32_t chan_mask = 0;
switch (slot_mask) switch (slot_mask)
{ {
case I2S_STD_SLOT_LEFT: case I2S_STD_SLOT_LEFT:
hw->tx_tdm_ctrl.val |= 0x01; chan_mask |= 0x01;
break; break;
case I2S_STD_SLOT_RIGHT: case I2S_STD_SLOT_RIGHT:
hw->tx_tdm_ctrl.val |= 0x02; chan_mask |= 0x02;
break; break;
case I2S_STD_SLOT_BOTH: case I2S_STD_SLOT_BOTH:
hw->tx_tdm_ctrl.val |= 0x03; chan_mask |= 0x03;
break; break;
default: default:
break; break;
} }
i2s_ll_tx_set_active_chan_mask(hw, chan_mask);
} }
/** /**
@ -627,21 +576,22 @@ static inline void i2s_ll_rx_select_std_slot(i2s_dev_t *hw, i2s_std_slot_mask_t
/* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot /* In mono mode, there only should be one slot enabled, another inactive slot will transmit same data as enabled slot
* Otherwise always enable the first two slots */ * Otherwise always enable the first two slots */
hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1 hw->rx_tdm_ctrl.rx_tdm_tot_chan_num = 1; // rx_tdm_tot_chan_num = 2 slots - 1 = 1
hw->rx_tdm_ctrl.val &= ~I2S_LL_TDM_CH_MASK; uint32_t chan_mask = 0;
switch (slot_mask) switch (slot_mask)
{ {
case I2S_STD_SLOT_LEFT: case I2S_STD_SLOT_LEFT:
hw->rx_tdm_ctrl.val |= 0x01; chan_mask |= 0x01;
break; break;
case I2S_STD_SLOT_RIGHT: case I2S_STD_SLOT_RIGHT:
hw->rx_tdm_ctrl.val |= 0x02; chan_mask |= 0x02;
break; break;
case I2S_STD_SLOT_BOTH: case I2S_STD_SLOT_BOTH:
hw->rx_tdm_ctrl.val |= 0x03; chan_mask |= 0x03;
break; break;
default: default:
break; break;
} }
i2s_ll_rx_set_active_chan_mask(hw, chan_mask);
} }
/** /**

61
components/hal/i2s_hal.c
View File

@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -11,7 +11,7 @@
#include "hal/i2s_hal.h" #include "hal/i2s_hal.h"
#if SOC_I2S_HW_VERSION_2 && SOC_I2S_SUPPORTS_PDM_TX #if SOC_I2S_HW_VERSION_2 && SOC_I2S_SUPPORTS_PDM_TX
/* PDM tx high pass filter cut-off frequency and coeffecients list /* PDM tx high pass filter cut-off frequency and coefficients list
* [0]: cut-off frequency; [1]: param0; [2]: param5 */ * [0]: cut-off frequency; [1]: param0; [2]: param5 */
static const float cut_off_coef[21][3] = { static const float cut_off_coef[21][3] = {
{185, 0, 0}, {172, 0, 1}, {160, 1, 1}, {185, 0, 0}, {172, 0, 1}, {160, 1, 1},
@ -24,6 +24,53 @@ static const float cut_off_coef[21][3] = {
}; };
#endif #endif
/**
* @brief Calculate the precise mclk division by sclk and mclk
*
* @param sclk system clock
* @param mclk module clock
* @param integer output the integer part of the division
* @param denominator output the denominator part of the division
* @param numerator output the numerator part of the division
*/
void i2s_hal_calc_mclk_precise_division(uint32_t sclk, uint32_t mclk, i2s_ll_mclk_div_t *mclk_div)
{
int ma = 0;
int mb = 0;
int min = INT32_MAX;
uint32_t div_denom = 1;
uint32_t div_numer = 0;
uint32_t div_inter = sclk / mclk;
uint32_t freq_diff = sclk % mclk;
if (freq_diff) {
float decimal = freq_diff / (float)mclk;
// Carry bit if the decimal is greater than 1.0 - 1.0 / (I2S_LL_MCLK_DIVIDER_MAX * 2)
if (decimal <= 1.0 - 1.0 / (float)(I2S_LL_MCLK_DIVIDER_MAX * 2)) {
for (int a = 2; a <= I2S_LL_MCLK_DIVIDER_MAX; a++) {
int b = (int)(a * (freq_diff / (double)mclk) + 0.5);
ma = freq_diff * a;
mb = mclk * b;
if (ma == mb) {
div_denom = (uint32_t)a;
div_numer = (uint32_t)b;
break;
}
if (abs(mb - ma) < min) {
div_denom = (uint32_t)a;
div_numer = (uint32_t)b;
min = abs(mb - ma);
}
}
} else {
div_inter++;
}
}
mclk_div->integ = div_inter;
mclk_div->denom = div_denom;
mclk_div->numer = div_numer;
}
void i2s_hal_init(i2s_hal_context_t *hal, int port_id) void i2s_hal_init(i2s_hal_context_t *hal, int port_id)
{ {
/* Get hardware instance */ /* Get hardware instance */
@ -32,23 +79,27 @@ void i2s_hal_init(i2s_hal_context_t *hal, int port_id)
void i2s_hal_set_tx_clock(i2s_hal_context_t *hal, const i2s_hal_clock_info_t *clk_info, i2s_clock_src_t clk_src) void i2s_hal_set_tx_clock(i2s_hal_context_t *hal, const i2s_hal_clock_info_t *clk_info, i2s_clock_src_t clk_src)
{ {
i2s_ll_mclk_div_t mclk_div = {};
#if SOC_I2S_HW_VERSION_2 #if SOC_I2S_HW_VERSION_2
i2s_ll_tx_enable_clock(hal->dev); i2s_ll_tx_enable_clock(hal->dev);
i2s_ll_mclk_bind_to_tx_clk(hal->dev); i2s_ll_mclk_bind_to_tx_clk(hal->dev);
#endif #endif
i2s_ll_tx_clk_set_src(hal->dev, clk_src); i2s_ll_tx_clk_set_src(hal->dev, clk_src);
i2s_ll_tx_set_mclk(hal->dev, clk_info->sclk, clk_info->mclk, clk_info->mclk_div); i2s_hal_calc_mclk_precise_division(clk_info->sclk, clk_info->mclk, &mclk_div);
i2s_ll_tx_set_mclk(hal->dev, &mclk_div);
i2s_ll_tx_set_bck_div_num(hal->dev, clk_info->bclk_div); i2s_ll_tx_set_bck_div_num(hal->dev, clk_info->bclk_div);
} }
void i2s_hal_set_rx_clock(i2s_hal_context_t *hal, const i2s_hal_clock_info_t *clk_info, i2s_clock_src_t clk_src) void i2s_hal_set_rx_clock(i2s_hal_context_t *hal, const i2s_hal_clock_info_t *clk_info, i2s_clock_src_t clk_src)
{ {
i2s_ll_mclk_div_t mclk_div = {};
#if SOC_I2S_HW_VERSION_2 #if SOC_I2S_HW_VERSION_2
i2s_ll_rx_enable_clock(hal->dev); i2s_ll_rx_enable_clock(hal->dev);
i2s_ll_mclk_bind_to_rx_clk(hal->dev); i2s_ll_mclk_bind_to_rx_clk(hal->dev);
#endif #endif
i2s_ll_rx_clk_set_src(hal->dev, clk_src); i2s_ll_rx_clk_set_src(hal->dev, clk_src);
i2s_ll_rx_set_mclk(hal->dev, clk_info->sclk, clk_info->mclk, clk_info->mclk_div); i2s_hal_calc_mclk_precise_division(clk_info->sclk, clk_info->mclk, &mclk_div);
i2s_ll_rx_set_mclk(hal->dev, &mclk_div);
i2s_ll_rx_set_bck_div_num(hal->dev, clk_info->bclk_div); i2s_ll_rx_set_bck_div_num(hal->dev, clk_info->bclk_div);
} }
@ -200,7 +251,7 @@ void i2s_hal_pdm_set_rx_slot(i2s_hal_context_t *hal, bool is_slave, const i2s_ha
i2s_ll_rx_enable_msb_right(hal->dev, false); i2s_ll_rx_enable_msb_right(hal->dev, false);
i2s_ll_rx_enable_right_first(hal->dev, false); i2s_ll_rx_enable_right_first(hal->dev, false);
#elif SOC_I2S_HW_VERSION_2 #elif SOC_I2S_HW_VERSION_2
i2s_ll_tx_set_half_sample_bit(hal->dev, 16); i2s_ll_rx_set_half_sample_bit(hal->dev, 16);
i2s_ll_rx_enable_mono_mode(hal->dev, false); i2s_ll_rx_enable_mono_mode(hal->dev, false);
/* Set the channel mask to enable corresponding slots, always enable two slots for stereo mode */ /* Set the channel mask to enable corresponding slots, always enable two slots for stereo mode */
i2s_ll_rx_set_active_chan_mask(hal->dev, slot_cfg->slot_mode == I2S_SLOT_MODE_STEREO ? i2s_ll_rx_set_active_chan_mask(hal->dev, slot_cfg->slot_mode == I2S_SLOT_MODE_STEREO ?

11
components/hal/include/hal/i2s_hal.h
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -120,6 +120,15 @@ typedef struct {
*/ */
void i2s_hal_init(i2s_hal_context_t *hal, int port_id); void i2s_hal_init(i2s_hal_context_t *hal, int port_id);
/**
* @brief Helper function for calculating the precise mclk division by sclk and mclk
*
* @param sclk system clock
* @param mclk module clock
* @param mclk_div mclk division coefficients, including integer part and decimal part
*/
void i2s_hal_calc_mclk_precise_division(uint32_t sclk, uint32_t mclk, i2s_ll_mclk_div_t *mclk_div);
/** /**
* @brief Set tx channel clock * @brief Set tx channel clock
* *

2
components/soc/esp32c3/include/soc/i2s_struct.h
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@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */

2
components/soc/esp32s3/include/soc/i2s_struct.h
View File

@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */