mirror of
https://github.com/espressif/esp-idf
synced 2025-03-09 17:19:09 -04:00
refactor(soc): sort esp32c2 soc headers
This commit is contained in:
laokaiyao
Kevin (Lao Kaiyao)
parent
f33bd32b36
commit
fa8d73861b
@ -8,8 +8,7 @@
|
||||
#define _DPORT_ACCESS_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc.h"
|
||||
#include "uart_reg.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "interrupt_core0_reg.h"
|
||||
#include "soc/interrupt_core0_reg.h"
|
||||
|
||||
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG INTERRUPT_CORE0_CPU_INT_THRESH_REG
|
||||
#define INTERRUPT_PRIO_REG(n) (INTERRUPT_CORE0_CPU_INT_PRI_0_REG + (n)*4)
|
||||
|
||||
@ -12,7 +12,7 @@
|
||||
#endif
|
||||
|
||||
#include "esp_bit_defs.h"
|
||||
#include "reg_base.h"
|
||||
#include "soc/reg_base.h"
|
||||
|
||||
#define PRO_CPU_NUM (0)
|
||||
|
||||
|
||||
@ -15,14 +15,14 @@ extern "C" {
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
|
||||
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [0]; default: 0;
|
||||
* enbale sp underlow monitor
|
||||
* enable sp underflow monitor
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 0
|
||||
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [1]; default: 0;
|
||||
* enbale sp overflow monitor
|
||||
* enable sp overflow monitor
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
|
||||
@ -34,14 +34,14 @@ extern "C" {
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
|
||||
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [0]; default: 0;
|
||||
* sp underlow monitor interrupt status register
|
||||
* sp underflow monitor interrupt status register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 0
|
||||
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [1]; default: 0;
|
||||
* sp overflow monitor interupt status register
|
||||
* sp overflow monitor interrupt status register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
|
||||
@ -53,14 +53,14 @@ extern "C" {
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
|
||||
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [0]; default: 0;
|
||||
* enbale sp underlow monitor interrupt
|
||||
* enable sp underflow monitor interrupt
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x00000001U
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 0
|
||||
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [1]; default: 0;
|
||||
* enbale sp overflow monitor interrupt
|
||||
* enable sp overflow monitor interrupt
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(1))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
|
||||
@ -72,7 +72,7 @@ extern "C" {
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
|
||||
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [0]; default: 0;
|
||||
* clr sp underlow monitor interrupt
|
||||
* clr sp underflow monitor interrupt
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(0))
|
||||
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
|
||||
@ -91,7 +91,7 @@ extern "C" {
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
|
||||
/** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0;
|
||||
* core0 sp region configuration regsiter
|
||||
* core0 sp region configuration register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
|
||||
@ -115,7 +115,7 @@ extern "C" {
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
|
||||
/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
|
||||
* This regsiter stores the PC when trigger stack monitor.
|
||||
* This register stores the PC when trigger stack monitor.
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU
|
||||
#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
|
||||
@ -142,7 +142,7 @@ extern "C" {
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
|
||||
* record status regsiter
|
||||
* record status register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
|
||||
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
|
||||
@ -154,7 +154,7 @@ extern "C" {
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0
|
||||
|
||||
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
|
||||
* record status regsiter
|
||||
* record status register
|
||||
*/
|
||||
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
|
||||
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
|
||||
@ -5,7 +5,7 @@
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
@ -7,7 +7,7 @@
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "efuse_defs.h"
|
||||
#include "soc/efuse_defs.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
@ -896,7 +896,7 @@ extern "C" {
|
||||
#define EFUSE_CLK_EN_S 16
|
||||
|
||||
/** EFUSE_CONF_REG register
|
||||
* eFuse operation mode configuraiton register
|
||||
* eFuse operation mode configuration register
|
||||
*/
|
||||
#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x8c)
|
||||
/** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0;
|
||||
@ -745,7 +745,7 @@ typedef union {
|
||||
} efuse_clk_reg_t;
|
||||
|
||||
/** Type of conf register
|
||||
* eFuse operation mode configuraiton register
|
||||
* eFuse operation mode configuration register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
@ -7,7 +7,7 @@
|
||||
#define _SOC_IO_MUX_REG_H_
|
||||
|
||||
#pragma once
|
||||
#include "soc.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
|
||||
/* Output enable in sleep mode */
|
||||
@ -43,5 +43,5 @@
|
||||
#define DR_REG_I2C_MST_BASE 0x6004E800
|
||||
#define DR_REG_XTS_AES_BASE 0x600CC000
|
||||
|
||||
/* For backward compatability with the older register name */
|
||||
/* For backward compatibility with the older register name */
|
||||
#define DR_REG_AES_XTS_BASE DR_REG_XTS_AES_BASE
|
||||
@ -9,7 +9,7 @@
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
#include "soc/soc.h"
|
||||
#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG
|
||||
#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG
|
||||
|
||||
@ -1144,7 +1144,7 @@ RO CPU.*/
|
||||
#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1
|
||||
#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31
|
||||
/* RTC_CNTL_SWD_DISABLE : ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: disabel SWD.*/
|
||||
/*description: disable SWD.*/
|
||||
#define RTC_CNTL_SWD_DISABLE (BIT(30))
|
||||
#define RTC_CNTL_SWD_DISABLE_M (BIT(30))
|
||||
#define RTC_CNTL_SWD_DISABLE_V 0x1
|
||||
@ -399,7 +399,7 @@ typedef volatile struct rtc_cntl_dev_s{
|
||||
uint32_t swd_signal_width : 10; /*adjust signal width send to swd*/
|
||||
uint32_t swd_rst_flag_clr : 1; /*reset swd reset flag*/
|
||||
uint32_t swd_feed : 1; /*Sw feed swd*/
|
||||
uint32_t swd_disable : 1; /*disabel SWD*/
|
||||
uint32_t swd_disable : 1; /*disable SWD*/
|
||||
uint32_t swd_auto_feed_en : 1; /*automatically feed swd when int comes*/
|
||||
};
|
||||
uint32_t val;
|
||||
@ -7,7 +7,7 @@
|
||||
#define _SOC_SPI_MEM_REG_H_
|
||||
|
||||
|
||||
#include "soc.h"
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
@ -94,15 +94,15 @@ he bit will be cleared once the operation done.1: enable 0: disable..*/
|
||||
#define SPI_MEM_FLASH_DP_S 21
|
||||
/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */
|
||||
/*description: This bit combined with reg_resandres bit releases Flash from the power-down stat
|
||||
e or high performance mode and obtains the devices ID. The bit will be cleared o
|
||||
nce the operation done.1: enable 0: disable..*/
|
||||
e or high performance mode and obtains the devices ID. The bit will be cleared once
|
||||
the operation done.1: enable 0: disable..*/
|
||||
#define SPI_MEM_FLASH_RES (BIT(20))
|
||||
#define SPI_MEM_FLASH_RES_M (BIT(20))
|
||||
#define SPI_MEM_FLASH_RES_V 0x1
|
||||
#define SPI_MEM_FLASH_RES_S 20
|
||||
/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */
|
||||
/*description: Drive Flash into high performance mode. The bit will be cleared once the operat
|
||||
ion done.1: enable 0: disable..*/
|
||||
/*description: Drive Flash into high performance mode. The bit will be cleared once the operation
|
||||
done.1: enable 0: disable..*/
|
||||
#define SPI_MEM_FLASH_HPM (BIT(19))
|
||||
#define SPI_MEM_FLASH_HPM_M (BIT(19))
|
||||
#define SPI_MEM_FLASH_HPM_V 0x1
|
||||
@ -123,8 +123,8 @@ peration done.1: enable 0: disable..*/
|
||||
#define SPI_MEM_FLASH_PE_V 0x1
|
||||
#define SPI_MEM_FLASH_PE_S 17
|
||||
/* SPI_MEM_MSPI_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
|
||||
/*description: The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation sta
|
||||
te, 2: send command state, 3: send address state, 4: wait state, 5: read data st
|
||||
/*description: The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation
|
||||
state, 2: send command state, 3: send address state, 4: wait state, 5: read data st
|
||||
ate, 6:write data state, 7: done state, 8: read data end state..*/
|
||||
#define SPI_MEM_MSPI_ST 0x0000000F
|
||||
#define SPI_MEM_MSPI_ST_M ((SPI_MEM_MSPI_ST_V)<<(SPI_MEM_MSPI_ST_S))
|
||||
@ -213,14 +213,14 @@ UT AND SPI_MEM_FREAD_DOUT. 1: enable 0: disable..*/
|
||||
#define SPI_MEM_FASTRD_MODE_V 0x1
|
||||
#define SPI_MEM_FASTRD_MODE_S 13
|
||||
/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disabl
|
||||
/*description: For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
|
||||
e.*/
|
||||
#define SPI_MEM_TX_CRC_EN (BIT(11))
|
||||
#define SPI_MEM_TX_CRC_EN_M (BIT(11))
|
||||
#define SPI_MEM_TX_CRC_EN_V 0x1
|
||||
#define SPI_MEM_TX_CRC_EN_S 11
|
||||
/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Activ
|
||||
/*description: For SPI1, initialize crc32 module before writing encrypted data to flash. Active
|
||||
e low..*/
|
||||
#define SPI_MEM_FCS_CRC_EN (BIT(10))
|
||||
#define SPI_MEM_FCS_CRC_EN_M (BIT(10))
|
||||
@ -262,7 +262,7 @@ e low..*/
|
||||
/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
|
||||
/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
|
||||
d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
|
||||
ve 3: SPI clock is alwasy on..*/
|
||||
ve 3: SPI clock is always on..*/
|
||||
#define SPI_MEM_CLK_MODE 0x00000003
|
||||
#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
|
||||
#define SPI_MEM_CLK_MODE_V 0x3
|
||||
@ -822,7 +822,7 @@ out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS
|
||||
#define SPI_MEM_FLASH_PES_EN_S 5
|
||||
/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to enable PES end triggers PER transfer option. If this bit is 0, a
|
||||
pplication should send PER after PES is done..*/
|
||||
application should send PER after PES is done..*/
|
||||
#define SPI_MEM_PES_PER_EN (BIT(4))
|
||||
#define SPI_MEM_PES_PER_EN_M (BIT(4))
|
||||
#define SPI_MEM_PES_PER_EN_V 0x1
|
||||
@ -844,8 +844,8 @@ resume command is sent..*/
|
||||
#define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1
|
||||
#define SPI_MEM_FLASH_PER_WAIT_EN_S 2
|
||||
/* SPI_MEM_FLASH_PES : R/W/SC ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: program erase suspend bit, program erase suspend operation will be triggered whe
|
||||
n the bit is set. The bit will be cleared once the operation done.1: enable 0: d
|
||||
/*description: program erase suspend bit, program erase suspend operation will be triggered when
|
||||
the bit is set. The bit will be cleared once the operation done.1: enable 0: d
|
||||
isable..*/
|
||||
#define SPI_MEM_FLASH_PES (BIT(1))
|
||||
#define SPI_MEM_FLASH_PES_M (BIT(1))
|
||||
@ -1148,7 +1148,7 @@ ut with the spi_clk high edge ,6: output with the spi_clk low edge.*/
|
||||
#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8)
|
||||
/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that
|
||||
chip is loosing power and RTC module sends out brown out close flash request to
|
||||
chip is losing power and RTC module sends out brown out close flash request to
|
||||
SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered
|
||||
and MSPI returns to idle state. 0: Others..*/
|
||||
#define SPI_MEM_BROWN_OUT_INT_RAW (BIT(5))
|
||||
@ -64,7 +64,7 @@ typedef volatile struct spi_mem_dev_s{
|
||||
} ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
|
||||
uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
|
||||
uint32_t cs_hold_dly_res : 10; /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
|
||||
uint32_t reserved2 : 18; /*reserved*/
|
||||
uint32_t rxfifo_rst : 1; /*SPI0 RX FIFO reset signal.*/
|
||||
@ -322,7 +322,7 @@ typedef volatile struct spi_mem_dev_s{
|
||||
uint32_t wpe_end : 1; /*The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.*/
|
||||
uint32_t slv_st_end : 1; /*The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others*/
|
||||
uint32_t mst_st_end : 1; /*The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.*/
|
||||
uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
|
||||
uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
|
||||
uint32_t reserved6 : 26; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
@ -159,7 +159,7 @@ e, the FSPI bus signals are output. Can be configured in CONF state..*/
|
||||
|
||||
#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xC)
|
||||
/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */
|
||||
/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from syst
|
||||
/*description: In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from syst
|
||||
em clock. Can be configured in CONF state..*/
|
||||
#define SPI_CLK_EQU_SYSCLK (BIT(31))
|
||||
#define SPI_CLK_EQU_SYSCLK_M (BIT(31))
|
||||
@ -196,15 +196,15 @@ e 0. Can be configured in CONF state..*/
|
||||
|
||||
#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10)
|
||||
/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
|
||||
/*description: This bit enable the command phase of an operation. Can be configured in CONF sta
|
||||
te..*/
|
||||
/*description: This bit enable the command phase of an operation. Can be configured in CONF
|
||||
state..*/
|
||||
#define SPI_USR_COMMAND (BIT(31))
|
||||
#define SPI_USR_COMMAND_M (BIT(31))
|
||||
#define SPI_USR_COMMAND_V 0x1
|
||||
#define SPI_USR_COMMAND_S 31
|
||||
/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: This bit enable the address phase of an operation. Can be configured in CONF sta
|
||||
te..*/
|
||||
/*description: This bit enable the address phase of an operation. Can be configured in CONF
|
||||
state..*/
|
||||
#define SPI_USR_ADDR (BIT(30))
|
||||
#define SPI_USR_ADDR_M (BIT(30))
|
||||
#define SPI_USR_ADDR_V 0x1
|
||||
@ -392,7 +392,7 @@ n be configured in CONF state..*/
|
||||
#define SPI_USR_COMMAND_BITLEN_S 28
|
||||
/* SPI_MST_REMPTY_ERR_END_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
|
||||
/*description: 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI m
|
||||
aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty erro
|
||||
aster FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error
|
||||
r is valid in GP-SPI master FD/HD-mode..*/
|
||||
#define SPI_MST_REMPTY_ERR_END_EN (BIT(27))
|
||||
#define SPI_MST_REMPTY_ERR_END_EN_M (BIT(27))
|
||||
@ -1113,7 +1113,7 @@ AFIFO read-empty error when SPI outputs data in master mode. 0: Others..*/
|
||||
#define SPI_SLV_CMD_ERR_INT_RAW_V 0x1
|
||||
#define SPI_SLV_CMD_ERR_INT_RAW_S 16
|
||||
/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */
|
||||
/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data addres
|
||||
/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address
|
||||
s of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission
|
||||
is bigger than 63. 0: Others..*/
|
||||
#define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15))
|
||||
@ -1684,7 +1684,7 @@ dge 0: output data at tsck posedge.*/
|
||||
/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delaye
|
||||
d one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inacti
|
||||
ve 3: SPI clock is alwasy on. Can be configured in CONF state..*/
|
||||
ve 3: SPI clock is always on. Can be configured in CONF state..*/
|
||||
#define SPI_CLK_MODE 0x00000003
|
||||
#define SPI_CLK_MODE_M ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S))
|
||||
#define SPI_CLK_MODE_V 0x3
|
||||
@ -10,7 +10,7 @@
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
typedef volatile struct spi_dev_s{
|
||||
union {
|
||||
@ -58,7 +58,7 @@ typedef volatile struct spi_dev_s{
|
||||
uint32_t clkcnt_n : 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/
|
||||
uint32_t clkdiv_pre : 4; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/
|
||||
uint32_t reserved22 : 9; /*reserved*/
|
||||
uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
|
||||
uint32_t clk_equ_sysclk : 1; /*In the master mode 1: spi_clk is equal to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clock;
|
||||
@ -366,7 +366,7 @@ typedef volatile struct spi_dev_s{
|
||||
uint32_t reserved_dc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/
|
||||
uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on. Can be configured in CONF state.*/
|
||||
uint32_t clk_mode_13 : 1; /*{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].*/
|
||||
uint32_t rsck_data_out : 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge */
|
||||
uint32_t reserved4 : 4; /*reserved*/
|
||||
@ -10,7 +10,7 @@
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x0)
|
||||
/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
|
||||
@ -10,7 +10,7 @@
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include "soc.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0)
|
||||
/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
|
||||
@ -92,7 +92,7 @@ NULL characters, after all data in Tx-FIFO are sent..*/
|
||||
#define UART_SW_XOFF_INT_RAW_V 0x1
|
||||
#define UART_SW_XOFF_INT_RAW_S 10
|
||||
/* UART_SW_XON_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: This interrupt raw bit turns to high level when receiver recevies Xon char when
|
||||
/*description: This interrupt raw bit turns to high level when receiver receives Xon char when
|
||||
uart_sw_flow_con_en is set to 1..*/
|
||||
#define UART_SW_XON_INT_RAW (BIT(9))
|
||||
#define UART_SW_XON_INT_RAW_M (BIT(9))
|
||||
@ -205,7 +205,7 @@ t to 1..*/
|
||||
#define UART_TX_DONE_INT_ST_V 0x1
|
||||
#define UART_TX_DONE_INT_ST_S 14
|
||||
/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
|
||||
/*description: This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_en
|
||||
/*description: This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_en
|
||||
a is set to 1..*/
|
||||
#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13))
|
||||
#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13))
|
||||
@ -744,7 +744,7 @@ ansmitter's 11th bit to 0..*/
|
||||
#define UART_IRDA_DPLX_V 0x1
|
||||
#define UART_IRDA_DPLX_S 9
|
||||
/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to enbale transmitter to send NULL when the process of sending dat
|
||||
/*description: Set this bit to enable transmitter to send NULL when the process of sending dat
|
||||
a is done..*/
|
||||
#define UART_TXD_BRK (BIT(8))
|
||||
#define UART_TXD_BRK_M (BIT(8))
|
||||
@ -791,7 +791,7 @@ ware flow control..*/
|
||||
|
||||
#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24)
|
||||
/* UART_RX_TOUT_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
|
||||
/*description: This is the enble bit for uart receiver's timeout function..*/
|
||||
/*description: This is the enable bit for uart receiver's timeout function..*/
|
||||
#define UART_RX_TOUT_EN (BIT(21))
|
||||
#define UART_RX_TOUT_EN_M (BIT(21))
|
||||
#define UART_RX_TOUT_EN_V 0x1
|
||||
@ -840,7 +840,7 @@ se. It is used in baud rate-detect process..*/
|
||||
|
||||
#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C)
|
||||
/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hfff ; */
|
||||
/*description: This register stores the value of the maxinum duration time for the high level
|
||||
/*description: This register stores the value of the maximum duration time for the high level
|
||||
pulse. It is used in baud rate-detect process..*/
|
||||
#define UART_HIGHPULSE_MIN_CNT 0x00000FFF
|
||||
#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
|
||||
@ -898,7 +898,7 @@ t process..*/
|
||||
#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38)
|
||||
/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */
|
||||
/*description: The uart is activated from light sleeping mode when the input rxd edge changes m
|
||||
ore times than this register value..*/
|
||||
or times than this register value..*/
|
||||
#define UART_ACTIVE_THRESHOLD 0x000003FF
|
||||
#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))
|
||||
#define UART_ACTIVE_THRESHOLD_V 0x3FF
|
||||
@ -951,8 +951,8 @@ of sending data is done. It is active when txd_brk is set to 1..*/
|
||||
#define UART_TX_IDLE_NUM_V 0x3FF
|
||||
#define UART_TX_IDLE_NUM_S 10
|
||||
/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */
|
||||
/*description: It will produce frame end signal when receiver takes more time to receive one by
|
||||
te data than this register value..*/
|
||||
/*description: It will produce frame end signal when receiver takes more time to receive one byte
|
||||
data than this register value..*/
|
||||
#define UART_RX_IDLE_THRHD 0x000003FF
|
||||
#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))
|
||||
#define UART_RX_IDLE_THRHD_V 0x3FF
|
||||
@ -1066,7 +1066,7 @@ akes more time to receive one byte with rx_tout_en set to 1..*/
|
||||
#define UART_RX_TOUT_THRHD_V 0x3FF
|
||||
#define UART_RX_TOUT_THRHD_S 16
|
||||
/* UART_RX_FLOW_THRHD : R/W ;bitpos:[15:7] ;default: 9'h0 ; */
|
||||
/*description: This register is used to configure the maximum amount of data that can be receiv
|
||||
/*description: This register is used to configure the maximum amount of data that can be receive
|
||||
ed when hardware flow control works..*/
|
||||
#define UART_RX_FLOW_THRHD 0x000001FF
|
||||
#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))
|
||||
@ -29,7 +29,7 @@ typedef volatile struct uart_dev_s {
|
||||
uint32_t cts_chg : 1; /*This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.*/
|
||||
uint32_t brk_det : 1; /*This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.*/
|
||||
uint32_t rxfifo_tout : 1; /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
|
||||
uint32_t sw_xon : 1; /*This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.*/
|
||||
uint32_t sw_xon : 1; /*This interrupt raw bit turns to high level when receiver receives Xon char when uart_sw_flow_con_en is set to 1.*/
|
||||
uint32_t sw_xoff : 1; /*This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.*/
|
||||
uint32_t glitch_det : 1; /*This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.*/
|
||||
uint32_t tx_brk_done : 1; /*This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent.*/
|
||||
@ -59,7 +59,7 @@ typedef volatile struct uart_dev_s {
|
||||
uint32_t sw_xoff : 1; /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
|
||||
uint32_t glitch_det : 1; /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
|
||||
uint32_t tx_brk_done : 1; /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
|
||||
uint32_t tx_brk_idle_done : 1; /*This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
|
||||
uint32_t tx_brk_idle_done : 1; /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
|
||||
uint32_t tx_done : 1; /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
|
||||
uint32_t rs485_parity_err : 1; /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
|
||||
uint32_t rs485_frm_err : 1; /*This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
|
||||
@ -162,7 +162,7 @@ typedef volatile struct uart_dev_s {
|
||||
uint32_t stop_bit_num : 2; /*This register is used to set the length of stop bit.*/
|
||||
uint32_t sw_rts : 1; /*This register is used to configure the software rts signal which is used in software flow control.*/
|
||||
uint32_t sw_dtr : 1; /*This register is used to configure the software dtr signal which is used in software flow control.*/
|
||||
uint32_t txd_brk : 1; /*Set this bit to enbale transmitter to send NULL when the process of sending data is done.*/
|
||||
uint32_t txd_brk : 1; /*Set this bit to enable transmitter to send NULL when the process of sending data is done.*/
|
||||
uint32_t irda_dplx : 1; /*Set this bit to enable IrDA loopback mode.*/
|
||||
uint32_t irda_tx_en : 1; /*This is the start enable bit for IrDA transmitter.*/
|
||||
uint32_t irda_wctl : 1; /*1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.*/
|
||||
@ -194,7 +194,7 @@ typedef volatile struct uart_dev_s {
|
||||
uint32_t dis_rx_dat_ovf : 1; /*Disable UART Rx data overflow detect. */
|
||||
uint32_t rx_tout_flow_dis : 1; /*Set this bit to stop accumulating idle_cnt when hardware flow control works.*/
|
||||
uint32_t rx_flow_en : 1; /*This is the flow enable bit for UART receiver.*/
|
||||
uint32_t rx_tout_en : 1; /*This is the enble bit for uart receiver's timeout function.*/
|
||||
uint32_t rx_tout_en : 1; /*This is the enable bit for uart receiver's timeout function.*/
|
||||
uint32_t reserved22 : 10;
|
||||
};
|
||||
uint32_t val;
|
||||
@ -208,7 +208,7 @@ typedef volatile struct uart_dev_s {
|
||||
} lowpulse;
|
||||
union {
|
||||
struct {
|
||||
uint32_t min_cnt : 12; /*This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.*/
|
||||
uint32_t min_cnt : 12; /*This register stores the value of the maximum duration time for the high level pulse. It is used in baud rate-detect process.*/
|
||||
uint32_t reserved12 : 20; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
@ -119,7 +119,7 @@ extern "C" {
|
||||
#define XTS_AES_DATE_V 0x3FFFFFFFU
|
||||
#define XTS_AES_DATE_S 0
|
||||
|
||||
/* For backward compatability with the older register names */
|
||||
/* For backward compatibility with the older register names */
|
||||
#define AES_XTS_PLAIN_BASE XTS_AES_PLAIN_MEM
|
||||
#define AES_XTS_SIZE_REG XTS_AES_LINESIZE_REG
|
||||
#define AES_XTS_DESTINATION_REG XTS_AES_DESTINATION_REG
|
||||
Loading…
x
Reference in New Issue
Block a user