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18 Commits

Author SHA1 Message Date
morris
7d07fe5047 Merge branch 'feat/async_memcpy_any_alignment_v5.4' into 'release/v5.4' 
async memcpy destination address doesn't have to be cache aligned (v5.4)

See merge request espressif/esp-idf!36633
 2025-02-13 10:36:23 +08:00
morris
1a430290f2 fix(rgb_lcd): drift issue caused by restart 
Closes https://github.com/espressif/esp-idf/issues/15013
 2025-02-12 10:43:16 +08:00
morris
e121a77c92 fix(dma): also consider buffer alignment when calculating the DMA nodes 
Closes https://github.com/espressif/esp-idf/issues/15228
 2025-02-11 13:46:12 +08:00
morris
00f21c37fe feat(lcd): increase the upper limit of pclk frequency for RGB LCD 2024-12-25 10:29:08 +08:00
morris
49fbe54bc4 feat(lcd): support color conversion for mipi dsi driver 2024-11-08 15:23:06 +08:00
morris
efcb91b47e feat(lcd): support rgb lcd driver for esp32p4 2024-10-22 17:18:05 +08:00
morris
dd82222dd9 feat(rgb_lcd): use gdma_link driver 2024-10-11 18:38:12 +08:00
morris
611fb654ce refactor(lcd): clean up GPIO initialization 2024-10-10 16:01:05 +08:00
wuzhenghui
13e42707a0
feat(esp_hw_support): add clk tree source gate management api 2024-09-11 10:53:01 +08:00
morris
23c41fc772 feat(lcd): support i80 lcd driver on esp32p4 2024-08-20 18:47:22 +08:00
morris
69ef3b6a34 change(rgb_lcd): set DMA transfer burst size 2024-05-24 22:43:55 +08:00
morris
4b67df323d feat(mipi_dsi): round to boundary when draw pixel 2024-05-08 14:08:19 +08:00
morris
c0289ee6eb fix(drivers): fix typos found by codespell 
codespell components/esp_driver*
 2024-03-28 10:01:27 +08:00
Markus Ebner
c755a62329 fix(esp_lcd): Flush rgb lcd PSRAM framebuffers after allocation 
Flush PSRAM framebuffers after allocation to avoid visual corruption.

Merges https://github.com/espressif/esp-idf/pull/13294
Closes https://github.com/espressif/esp-idf/issues/13293
 2024-03-01 18:05:22 +08:00
Hello1024
77029676d1 fix(rgb_lcd): remove validation of pins for LCD output 
There are a bunch of cases you might want some pins not exposed.

Eg.

  * Reading say 8 bit data and outputting the top 5 bits, discarding the rest by not mapping those data pins to output pins

 * Not using hsync/vsync because sync data is embedded within the data bits for more timing flexibility (eg. interlacing).

 * Using the LCD module as a high speed parallel data output bus, with no need for sync/control pins.

Removing this validation makes these cases work.

Merges https://github.com/espressif/esp-idf/pull/13103
 2024-02-05 10:00:35 +08:00
morris
b10dec96c5 fix(rgb_lcd): relax the check for the data line GPIO 
so we allow to leave some RGB data line unconnected by set the GPIO to -1
 2024-01-30 18:29:13 +08:00
Brian Whitman
ff840b645d fix(rgb_lcd): don't assume 16 bit width on panels for restart logic 
Merges https://github.com/espressif/esp-idf/pull/13020
 2024-01-30 18:29:13 +08:00
morris
ad84b61e49 change(esp_lcd): rearrange the esp_lcd folder by types 2024-01-16 17:40:27 +08:00