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Commit Graph

88 Commits

Author SHA1 Message Date
Jiang Jiang Jian
65577b9caf Merge branch 'fix/fix_tsens_power_after_modem_wakeup' into 'master' 
fix(esp_hw_support): fix tsensor power enable failed after modem state wakeup

See merge request espressif/esp-idf!35886
 2025-01-08 10:38:52 +08:00
Armando
784e87a9b2 feat(ocode): supported ocode on esp32c5 2025-01-02 10:12:47 +08:00
Wu Zheng Hui
12bb853c64 Merge branch 'feat/wait_pll_stable_after_sleep_wakeup' into 'master' 
feat(esp_hw_support): wait pll stable after sleep wakeup

Closes PM-280

See merge request espressif/esp-idf!34313
 2024-12-26 14:27:07 +08:00
wuzhenghui
0c0d8cb8e4
fix(esp_hw_support): fix modem power enable failed after modem state wakeup 2024-12-24 10:37:46 +08:00
nilesh.kale
1e11340061 feat(bootloader_support): enabled RSA based secure boot scheme for ESP32C5 ECO1 
This commit enabled RSA based secure boot scheme for ESP32C5 ECO1 module.
This update also adds a check to ensure the selected secure boot scheme is
valid for ECO0 modules.
 2024-12-03 16:48:56 +05:30
Song Ruo Jing
7e90a41bc9 Merge branch 'refactor/regi2c_mst_clock_enable' into 'master' 
refactor(regi2c): analog i2c mst clock should be enabled/disabled per usage

Closes IDF-10492 and IDF-10693

See merge request espressif/esp-idf!32682
 2024-11-05 15:15:26 +08:00
Jiang Jiang Jian
1f47975472 Merge branch 'bugfix/idf-11064' into 'master' 
fix some issues on esp32c5 eco1

Closes IDF-11064 and IDF-11066

See merge request espressif/esp-idf!34350
 2024-11-04 20:46:01 +08:00
Song Ruo Jing
2cb35a2955 refactor(regi2c): ana i2c master clock is enabled per request 2024-11-04 12:37:17 +08:00
Li Shuai
45ea08b955 fix(esp_hw_support): fix the issue of wifi rx packet loss when switchng soc root clock source 2024-11-04 11:19:29 +08:00
wuzhenghui
f4a6f1cc96
fix(esp_hw_support): fix hp clock wait time calculation after wait pll ready 2024-10-31 20:28:29 +08:00
wuzhenghui
58b1838946
feat(esp_hw_support): wait pll stable after sleep wakeup 2024-10-31 20:28:28 +08:00
wuzhenghui
3881d4031d
fix(esp_hw_support): enable all supported slow clock at pmu_init 2024-10-24 14:22:51 +08:00
Song Ruo Jing
7c0b1dc98c fix(clk): rtc_clk_cpu_freq_set_xtal will always disable CPU's PLL 
Align C6/H2/C5/C61 rtc_clk_cpu_freq_set_xtal behavior to other chips
For PMU supported chips, powering down CPU PLL in sleep will be done by PMU, not sleep code
 2024-10-17 12:41:15 +08:00
Song Ruo Jing
67a87a5fcd fix(pmu): enable all func clock icg during retention 
This should only increase a tiny amount of the power consumption in the retention process,
but save debug time since some module register read/write relies not only APB but also func clock.
 2024-10-17 12:41:15 +08:00
laokaiyao
4ed1b873b4 fix(gdma): fixed GDMA retention on C5 2024-09-30 17:38:22 +08:00
Mahavir Jain
2a6be654cd Merge branch 'ci/enable_memprot_tests_for_esp32c61' into 'master' 
Clear PMA entries before usage and enable tests for ESP32-C61

Closes IDF-10932

See merge request espressif/esp-idf!33438
 2024-09-20 21:32:18 +08:00
Marius Vikhammer
564d777018 Merge branch 'feature/lp_core_40_mhz' into 'master' 
feat(system): support choosing xtal as rtc-fast clock src on P4 and C5

Closes IDF-10203

See merge request espressif/esp-idf!32450
 2024-09-20 10:57:15 +08:00
Marius Vikhammer
00eb97725b feat(system): support choosing xtal as rtc-fast clock src on P4 and C5 
With xtal as rtc-fast clock source the LP-Core can run at twice the default
clock frequency. 40 MHz as opposed to 20 MHz.
 2024-09-19 17:30:44 +08:00
harshal.patil
7667d9ebbe
fix(cpu_region_protect): Reset PMA entries before using them 
- ROM uses some PMA entries so we clear such PMA entries before using them in ESP-IDF
 2024-09-18 10:25:18 +05:30
Marius Vikhammer
5486653a18 Merge branch 'contrib/github_pr_14422' into 'master' 
feat(esp_system,ulp): LP core reserved mem optionally executable from HP core (GitHub PR)

Closes IDFGH-13533

See merge request espressif/esp-idf!33139
 2024-09-12 09:10:22 +08:00
wuzhenghui
13e42707a0
feat(esp_hw_support): add clk tree source gate management api 2024-09-11 10:53:01 +08:00
wuzhenghui
05e74480f5
feat(esp_system): gate some clock by default to optmize esp32p4 active power 2024-09-11 10:53:00 +08:00
andylinpersonal
0e30c42625 feat(esp_system,ulp): Make LP core reserved memory optionally executable in HP core 2024-09-10 12:17:38 +08:00
Armando
17fc026c48 fix(pma): fixed pma 15 occupied by rom on c5 issue 2024-09-10 11:12:02 +08:00
chaijie@espressif.com
c9d4913393 fix(sleep): fix_wrong_sleep_param_for_lp_memory_retention 2024-09-04 15:02:15 +08:00
Li Shuai
1fa27cbb0d Merge branch 'feature/esp32c5mp_light_sleep_support_stage_2' into 'master' 
feat(esp_hw_support): esp32c5mp sleep support (system part)

Closes IDF-8643, PM-195, PM-169, IDF-8641, IDF-8640, IDF-8639, IDF-8638, CV-259, IDF-10308, IDF-10317, IDF-10310, PM-202, IDF-10918, PM-207, PM-208, PM-210, and PM-214

See merge request espressif/esp-idf!31645
 2024-08-29 19:32:05 +08:00
harshal.patil
dc61456ad8
feat(cpu_region_protect): Protect I/D-ROM memory split 2024-08-28 11:16:27 +05:30
harshal.patil
95f286555a
fix(esp_hw_support): Use _iram_text_end instead of _iram_end for I/D-RAM split 2024-08-28 11:16:27 +05:30
Lou Tianhao
d6737c3207 refactor(esp_hw_support): refactor sleep clock, split it to support multiple targets 2024-08-28 10:44:08 +08:00
Lou Tianhao
5e5fb89c10 change(esp_hw_support): modify the root clock source of pmu modem state to pll for esp32c5 2024-08-28 10:44:08 +08:00
Lou Tianhao
04485a655f change(esp_hw_support): set cpu clk 80m by selecting source pll240m and divider 3 
squash! change(esp_hw_support): set cpu clk 80m by selecting source pll240m and divider 3

squash! change(esp_hw_support): set cpu clk 80m by selecting source pll240m and divider 3

squash! change(esp_hw_support): set cpu clk 80m by selecting source pll240m and divider 3
 2024-08-28 10:44:08 +08:00
Lou Tianhao
ef8ff691aa change(esp_hw_support): update pmu sleep analog parameter 
change(pm): update pmu analog param for pu xtal or pu rc_fast during sleep

change(pm): update pmu analog param for reducing the impact of temperature on chip voltage
 2024-08-28 10:44:08 +08:00
Lou Tianhao
a0da9ade35 feat(esp_hw_support): support top domain powered down during sleep for esp32c5 2024-08-28 10:44:08 +08:00
Li Shuai
8d9b3cfb2f change(esp_hw_support): pmu reset and isolate contorl signal waiting time configuration 2024-08-28 10:44:08 +08:00
Lou Tianhao
980ec70d0a feat(esp_hw_support): support pmu init and sleep for esp32c5 
fix(ci): add efuse header in pmu_sleep
 2024-08-28 10:44:08 +08:00
Lou Tianhao
3e70dafa0b change(soc): update pmu register context structure and driver for esp32c5 2024-08-28 10:44:08 +08:00
laokaiyao
1c2f8b8ce0 feat(bootloader): support to check efuse block revision 
change(bootloader): remove ignore efuse check flag (temp)

change(bootloader): use int for the minimum efuse blk rev (temp)
 2024-08-26 10:02:31 +08:00
harshal.patil
488b2a741d change(esp_security): Move the crypto locking layer into the security component 2024-08-20 12:35:22 +08:00
Song Ruo Jing
6db52ffe12 remove(clk): rc32k is removed as a clk source option for lp_slow_clk on C5/C61 2024-07-31 22:41:23 +08:00
Song Ruo Jing
335d39b869 feat(clk): Add basic clock support for esp32c61 
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
- Remove FPGA build
 2024-07-31 22:41:22 +08:00
Song Ruo Jing
3aa27ae960 refactor(regi2c): add LL function to control analog i2c master clock 2024-07-24 12:26:59 +08:00
gaoxu
65820c07ac feat(adc): support ADC oneshot and continuous mode on ESP32C5 and enable test 2024-07-13 14:03:23 +08:00
Marius Vikhammer
41d39a419f fix(pmp): fixed alignment of PMP addr for RTC mem on C5 
Also refactored it for C6/H2/C61 to keep the approach consistent between targets
 2024-07-04 16:24:46 +08:00
gaoxu
0d35631ec1 feat(rtcio): support RTCIO on ESP32C5 2024-06-28 22:01:55 +08:00
wuzhenghui
2b70104761
fix(esp_hw_support): wait eFuse controller idle after sleep wakeup 2024-06-27 17:36:21 +08:00
Song Ruo Jing
e5dbbf467c Merge branch 'feature/esp32c5_clock_support' into 'master' 
feat(clk): Add basic clock support for esp32c5 mp

Closes IDF-8642 and IDF-9009

See merge request espressif/esp-idf!31514
 2024-06-26 19:27:51 +08:00
Song Ruo Jing
40f3bc2e57 feat(clk): Add basic clock support for esp32c5 mp 
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
- Remove FPGA build
 2024-06-26 14:26:34 +08:00
harshal.patil
84afc6a955
feat(esp_hw_support): Support memory protection using PMA and PMP for ESP32-C5 2024-06-25 11:55:15 +05:30
harshal.patil
980ac9bcf5
fix(soc): Fix ESP32-C5's rom mask high and subsystem high memory addresses 2024-06-25 11:39:22 +05:30
Wu Zheng Hui
2d36e81ccd Merge branch 'fix/remove_esp32c6_h2_solved_todos' into 'master' 
change(esp_hw_support): remove esp32c6 & esp32h2 solved todos

Closes IDF-5781 and IDF-6254

See merge request espressif/esp-idf!31401
 2024-06-24 13:35:04 +08:00