3 Commits

Author	SHA1	Message	Date
Omar Chebib	102d5bbf72	refactor(riscv): added a new API for the interrupts	2024-01-18 16:36:53 +08:00
Ivan Grokhotkov	75c92c3a66	refactor(startup): implement registration of core init functions ... Similar to how the secondary init functions were already registered via ESP_SYSTEM_INIT_FN, do the same for the core init functions. This MR doesn't actually move the init functions into respective components yet. This has to be carefully done in follow-up MRs.	2023-11-27 10:20:51 +01:00
Alexey Lapshin	4df3ff619e	feat(esp_system): implement hw stack guard for riscv chips ... - add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature	2023-07-01 16:27:40 +00:00