Merge branch 'bugfix/mdns_non_standard_domains' into 'master'

mdns: Fix parsing non-standard queries Closes IDFGH-6009 See merge request espressif/esp-idf!15566
Merge branch 'bugfix/remove-uneeded-clang-ifdefs' into 'master'
2025-03-09 09:09:10 -04:00 · 2021-10-20 16:21:24 +00:00 · 2021-10-20 14:54:28 +00:00 · 2021-10-20 13:59:39 +00:00 · 2021-10-20 10:22:22 +00:00 · 2021-10-20 15:20:08 +05:30
260 changed files with 5420 additions and 3257 deletions
--- a/.github/ISSUE_TEMPLATE/bug_report.md
+++ b/.github/ISSUE_TEMPLATE/bug_report.md
@ -24,7 +24,7 @@ If the issue cannot be solved after the steps before, please follow these instru

 1. Fill in all the fields under **Environment** marked with [ ] by picking the correct option for you in each case and deleting the others.
 2. Describe your problem.
-3. Include [debug logs from the "monitor" tool](https://docs.espressif.com/projects/esp-idf/en/latest/get-started/idf-monitor.html#automatically-decoding-addresses), or [coredumps](https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/core_dump.html).
+3. Include [debug logs from the "monitor" tool](https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/tools/idf-monitor.html), or [coredumps](https://docs.espressif.com/projects/esp-idf/en/latest/api-guides/core_dump.html).
 4. Providing as much information as possible under **Other items if possible** will help us locate and fix the problem.
 5. Use [Markdown](https://guides.github.com/features/mastering-markdown/) (see formatting buttons above) and the Preview tab to check what the issue will look like.
 6. Delete these instructions from the above to the below marker lines before submitting this issue.
--- a/.gitlab/CODEOWNERS
+++ b/.gitlab/CODEOWNERS
@ -203,8 +203,9 @@ requirements.txt              @esp-idf-codeowners/tools

 # sort-order-reset

-^[Ignore Lists]
-/tools/ci/check_copyright_ignore.txt                    @esp-idf-codeowners/ci @esp-idf-codeowners/tools
-/tools/ci/check_examples_cmake_make-cmake_ignore.txt    @esp-idf-codeowners/ci @esp-idf-codeowners/tools
-/tools/ci/check_examples_cmake_make-make_ignore.txt     @esp-idf-codeowners/ci @esp-idf-codeowners/tools
-/tools/ci/mypy_ignore_list.txt                          @esp-idf-codeowners/ci @esp-idf-codeowners/tools
+# ignore lists
+/tools/ci/check_copyright_ignore.txt                    @esp-idf-codeowners/tools
+/tools/ci/check_copyright_permanent_ignore.txt          @esp-idf-codeowners/all-maintainers
+/tools/ci/check_examples_cmake_make-cmake_ignore.txt    @esp-idf-codeowners/tools
+/tools/ci/check_examples_cmake_make-make_ignore.txt     @esp-idf-codeowners/tools
+/tools/ci/mypy_ignore_list.txt                          @esp-idf-codeowners/tools
--- a/.gitlab/ci/docs.yml
+++ b/.gitlab/ci/docs.yml
@ -8,6 +8,9 @@
  - "tools/kconfig_new/**/*"
  - "CONTRIBUTING.rst"

+.patterns-docs-preview: &patterns-docs-preview
+  - "docs/**/*"
+
 .if-protected: &if-protected
  if: '($CI_COMMIT_REF_NAME == "master" || $CI_COMMIT_BRANCH =~ /^release\/v/ || $CI_COMMIT_TAG =~ /^v\d+\.\d+(\.\d+)?($|-)/)'

@ -170,6 +173,8 @@ deploy_docs_preview:
  rules:
    - <<: *if-label-build_docs
    - <<: *if-label-docs
+    - <<: *if-dev-push
+      changes: *patterns-docs-preview
  dependencies:
    - build_docs_html_fast
    - build_docs_html_full
@ -181,7 +186,7 @@ deploy_docs_preview:
    DOCS_DEPLOY_SERVER: "$DOCS_SERVER"
    DOCS_DEPLOY_SERVER_USER: "$DOCS_SERVER_USER"
    DOCS_DEPLOY_PATH: "$DOCS_PATH"
-    DOCS_DEPLOY_URL_BASE: "https://$CI_DOCKER_REGISTRY/docs/esp-idf"
+    DOCS_DEPLOY_URL_BASE: "https://$DOCS_PREVIEW_SERVER_URL/docs/esp-idf"

 # stage: post_deploy
 deploy_docs_production:
--- a/.gitlab/ci/host-test.yml
+++ b/.gitlab/ci/host-test.yml
@ -208,7 +208,7 @@ test_idf_tools:
  script:
    - cd ${IDF_PATH}/components/efuse/
    - ./efuse_table_gen.py -t "${IDF_TARGET}" ${IDF_PATH}/components/efuse/${IDF_TARGET}/esp_efuse_table.csv
-    - git diff --exit-code -- ${IDF_TARGET}/esp_efuse_table.c || { echo 'Differences found for ${IDF_TARGET} target. Please run make efuse_common_table or idf.py efuse_common_table and commit the changes.'; exit 1; }
+    - git diff --exit-code -- ${IDF_TARGET}/esp_efuse_table.c || { echo 'Differences found for ${IDF_TARGET} target. Please run make efuse_common_table or idf.py efuse-common-table and commit the changes.'; exit 1; }
    - cd ${IDF_PATH}/components/efuse/test_efuse_host
    - ./efuse_tests.py

@ -369,4 +369,5 @@ test_linux_example:
  script:
    - cd ${IDF_PATH}/examples/build_system/cmake/linux_host_app
    - idf.py build
-    - build/linux_host_app.elf
+    - timeout 5 ./build/linux_host_app.elf >test.log || true
+    - grep "Restarting" test.log
--- a/.gitlab/ci/pre_check.yml
+++ b/.gitlab/ci/pre_check.yml
@ -193,12 +193,3 @@ check_commit_msg:
    - git log -n10 --oneline
    # commit start with "WIP: " need to be squashed before merge
    - 'git log --pretty=%s master.. -- | grep "^WIP: " && exit 1 || exit 0'
-
-check_tools_file_patterns:
-  extends: .pre_check_job_template
-  image: $CI_DOCKER_REGISTRY/ubuntu-test-env$BOT_DOCKER_IMAGE_TAG
-  variables:
-    PYTHON_VER: 3.7.7
-  script:
-    - python tools/ci/check_tools_files_patterns.py
-  allow_failure: true
--- a/.gitlab/ci/rules.yml
+++ b/.gitlab/ci/rules.yml
@ -115,6 +115,7 @@
  - "tools/test_idf_py/**/*"

  - "tools/idf_size.py"
+  - "tools/idf_size_yaml/*"
  - "tools/test_idf_size/**/*"

  - "tools/tools.json"
--- a/.gitlab/ci/target-test.yml
+++ b/.gitlab/ci/target-test.yml
@ -77,6 +77,11 @@ test_weekend_mqtt:
    - .example_test_template
    - .rules:labels:example_test-esp32c3

+.example_test_esp32s3_template:
+  extends:
+    - .example_test_template
+    - .rules:test:example_test-esp32s3
+
 example_test_001A:
  extends: .example_test_esp32_template
  tags:
@ -270,6 +275,12 @@ example_test_ESP32_SDSPI:
    - ESP32
    - UT_T1_SPIMODE

+example_test_S3_GENERIC:
+  extends: .example_test_esp32s3_template
+  tags:
+    - ESP32S3
+    - Example_GENERIC
+
 example_test_ESP32S2_SDSPI:
  extends: .example_test_esp32s2_template
  tags:
@ -467,7 +478,7 @@ UT_001:

 UT_002:
  extends: .unit_test_esp32_template
-  parallel: 14
+  parallel: 15
  tags:
    - ESP32_IDF
    - UT_T1_1
@ -672,7 +683,7 @@ UT_S2_SDSPI:

 UT_C3:
  extends: .unit_test_esp32c3_template
-  parallel: 32
+  parallel: 33
  tags:
    - ESP32C3_IDF
    - UT_T1_1
@ -716,7 +727,7 @@ UT_C3_SDSPI:

 UT_S3:
  extends: .unit_test_esp32s3_template
-  parallel: 29
+  parallel: 31
  tags:
    - ESP32S3_IDF
    - UT_T1_1
--- a/.pre-commit-config.yaml
+++ b/.pre-commit-config.yaml
@ -108,8 +108,16 @@ repos:
        language: python
        files: \.(py|c|h|cpp|hpp|ld)$
        require_serial: true
+      - id: check-tools-files-patterns
+        name: Check tools dir files patterns
+        entry: tools/ci/check_tools_files_patterns.py
+        language: python
+        files: '^tools/.+'
+        additional_dependencies:
+          - PyYAML == 5.3.1
+        pass_filenames: false
  - repo: https://github.com/pre-commit/pre-commit-hooks
    rev: v4.0.1
    hooks:
      - id: file-contents-sorter
-        files: 'tools\/ci\/(executable-list\.txt|mypy_ignore_list\.txt|check_copyright_ignore\.txt)'
+        files: 'tools\/ci\/(executable-list\.txt|mypy_ignore_list\.txt|check_copyright_ignore\.txt|check_copyright_permanent_ignore\.txt)'
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@ -61,6 +61,10 @@ else()
    list(APPEND link_options "-fno-rtti")           # used to invoke correct multilib variant (no-rtti) during linking
 endif()

+if(CONFIG_COMPILER_SAVE_RESTORE_LIBCALLS)
+    list(APPEND compile_options "-msave-restore")
+endif()
+
 if(CONFIG_COMPILER_DISABLE_GCC8_WARNINGS)
    list(APPEND compile_options "-Wno-parentheses"
                                "-Wno-sizeof-pointer-memaccess"
--- a/12
+++ b/12
@ -394,6 +394,18 @@ mainmenu "Espressif IoT Development Framework Configuration"
                For C++, this warns about the deprecated conversion from string
                literals to ``char *``.

+        config COMPILER_SAVE_RESTORE_LIBCALLS
+            bool "Enable -msave-restore flag to reduce code size"
+            depends on IDF_TARGET_ARCH_RISCV
+            help
+                Adds -msave-restore to C/C++ compilation flags.
+
+                When this flag is enabled, compiler will call library functions to
+                save/restore registers in function prologues/epilogues. This results
+                in lower overall code size, at the expense of slightly reduced performance.
+
+                This option can be enabled for RISC-V targets only.
+
        config COMPILER_DISABLE_GCC8_WARNINGS
            bool "Disable new warnings introduced in GCC 6 - 8"
            default "n"
--- a/README.md
+++ b/README.md
@ -103,9 +103,9 @@ After the initial flash, you may just want to build and flash just your app, not

 ## Erasing Flash

-The `idf.py flash` target does not erase the entire flash contents. However it is sometimes useful to set the device back to a totally erased state, particularly when making partition table changes or OTA app updates. To erase the entire flash, run `idf.py erase_flash`.
+The `idf.py flash` target does not erase the entire flash contents. However it is sometimes useful to set the device back to a totally erased state, particularly when making partition table changes or OTA app updates. To erase the entire flash, run `idf.py erase-flash`.

-This can be combined with other targets, ie `idf.py -p PORT erase_flash flash` will erase everything and then re-flash the new app, bootloader and partition table.
+This can be combined with other targets, ie `idf.py -p PORT erase-flash flash` will erase everything and then re-flash the new app, bootloader and partition table.

 # Resources

--- a/README_CN.md
+++ b/README_CN.md
@ -56,7 +56,7 @@ ESP-IDF 中的子模块采用相对路径（[详见 .gitmodules 文件](.gitmodu
 * 在主机中安装入门指南中提到的构建所依赖的工具。
 * 运行安装脚本来设置构建环境。可为 Windows shell 选择 `install.bat` 或 `install.ps1`，为 Unix shell 选择 `install.sh` 和 `install.fish`。
 * 在使用 ESP-IDF 之前，需要在 shell 中运行导出脚本。Windows 下可运行 `export.bat`，Unix 下可运行 `source export.sh`。
-  
+
 ## 配置项目

 * `idf.py set-target <chip_name>` 可将项目的目标芯片设置为 `<chip_name>`。运行 `idf.py set-target`，不用带任何参数，可查看所有支持的目标芯片列表。
@ -103,9 +103,9 @@ ESP-IDF 中的子模块采用相对路径（[详见 .gitmodules 文件](.gitmodu

 ## 擦除 Flash

-`idf.py flash` 并不会擦除 flash 上所有的内容，但是有时候我们需要设备恢复到完全擦除的状态，尤其是分区表发生了变化或者 OTA 应用升级时。要擦除整块 flash 请运行 `idf.py erase_flash`。
+`idf.py flash` 并不会擦除 flash 上所有的内容，但是有时候我们需要设备恢复到完全擦除的状态，尤其是分区表发生了变化或者 OTA 应用升级时。要擦除整块 flash 请运行 `idf.py erase-flash`。

-这条命令还可以和其余命令整合在一起，`idf.py -p PORT erase_flash flash` 会擦除一切然后重新烧写新的应用程序、引导程序和分区表。
+这条命令还可以和其余命令整合在一起，`idf.py -p PORT erase-flash flash` 会擦除一切然后重新烧写新的应用程序、引导程序和分区表。

 # 其它参考资源

--- a/components/app_update/CMakeLists.txt
+++ b/components/app_update/CMakeLists.txt
@ -55,7 +55,7 @@ if(NOT BOOTLOADER_BUILD)
                         "--partition-table-offset;${PARTITION_TABLE_OFFSET}")
        idf_component_get_property(esptool_py_dir esptool_py COMPONENT_DIR)

-        add_custom_target(read_otadata DEPENDS "${PARTITION_CSV_PATH}"
+        add_custom_target(read-otadata DEPENDS "${PARTITION_CSV_PATH}"
            COMMAND ${CMAKE_COMMAND}
            -D IDF_PATH="${idf_path}"
            -D SERIAL_TOOL="${otatool_py}"
@ -65,8 +65,9 @@ if(NOT BOOTLOADER_BUILD)
            WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}
            USES_TERMINAL
            )
+        add_deprecated_target_alias(read_otadata read-otadata)

-        add_custom_target(erase_otadata DEPENDS "${PARTITION_CSV_PATH}"
+        add_custom_target(erase-otadata DEPENDS "${PARTITION_CSV_PATH}"
            COMMAND ${CMAKE_COMMAND}
            -D IDF_PATH="${idf_path}"
            -D SERIAL_TOOL="${otatool_py}"
@ -76,6 +77,7 @@ if(NOT BOOTLOADER_BUILD)
            WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}
            USES_TERMINAL
            )
+        add_deprecated_target_alias(erase_otadata erase-otadata)

        idf_component_get_property(main_args esptool_py FLASH_ARGS)
        idf_component_get_property(sub_args esptool_py FLASH_SUB_ARGS)
--- a/components/bt/controller/esp32/bt.c
+++ b/components/bt/controller/esp32/bt.c
@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #include <stddef.h>
 #include <stdlib.h>
@ -488,6 +480,18 @@ static void btdm_slp_tmr_callback(void *arg);
 #endif /* #ifdef CONFIG_PM_ENABLE */


+static inline void esp_bt_power_domain_on(void)
+{
+    // Bluetooth module power up
+    esp_wifi_bt_power_domain_on();
+}
+
+static inline void esp_bt_power_domain_off(void)
+{
+    // Bluetooth module power down
+    esp_wifi_bt_power_domain_off();
+}
+
 static inline void btdm_check_and_init_bb(void)
 {
    /* init BT-BB if PHY/RF has been switched off since last BT-BB init */
@ -1621,6 +1625,8 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
        goto error;
    }

+    esp_bt_power_domain_on();
+
    btdm_controller_mem_init();

    periph_module_enable(PERIPH_BT_MODULE);
@ -1774,6 +1780,8 @@ esp_err_t esp_bt_controller_deinit(void)
    btdm_lpcycle_us = 0;
    btdm_controller_set_sleep_mode(BTDM_MODEM_SLEEP_MODE_NONE);

+    esp_bt_power_domain_off();
+
    return ESP_OK;
 }

--- a/components/bt/controller/esp32c3/bt.c
+++ b/components/bt/controller/esp32c3/bt.c
@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #include <stddef.h>
 #include <stdlib.h>
@ -408,7 +400,7 @@ static DRAM_ATTR esp_pm_lock_handle_t s_light_sleep_pm_lock;
 void IRAM_ATTR btdm_hw_mac_power_down_wrapper(void)
 {
 #if CONFIG_MAC_BB_PD
-    // le module power down
+    // Bluetooth module power down
    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_ISO);
    SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PD);

@ -419,7 +411,7 @@ void IRAM_ATTR btdm_hw_mac_power_down_wrapper(void)
 void IRAM_ATTR btdm_hw_mac_power_up_wrapper(void)
 {
 #if CONFIG_MAC_BB_PD
-    // le module power up
+    // Bluetooth module power up
    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PD);
    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_ISO);

@ -427,6 +419,22 @@ void IRAM_ATTR btdm_hw_mac_power_up_wrapper(void)
 #endif
 }

+static inline void esp_bt_power_domain_on(void)
+{
+    // Bluetooth module power up
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PD);
+    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_ISO);
+    esp_wifi_bt_power_domain_on();
+}
+
+static inline void esp_bt_power_domain_off(void)
+{
+    // Bluetooth module power down
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_ISO);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PD);
+    esp_wifi_bt_power_domain_off();
+}
+
 void IRAM_ATTR btdm_backup_dma_copy_wrapper(uint32_t reg, uint32_t mem_addr, uint32_t num,  bool to_mem)
 {
 #if CONFIG_MAC_BB_PD
@ -956,6 +964,11 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
    // overwrite some parameters
    cfg->magic = ESP_BT_CTRL_CONFIG_MAGIC_VAL;

+#if CONFIG_MAC_BB_PD
+    esp_mac_bb_pd_mem_init();
+#endif
+    esp_bt_power_domain_on();
+
    btdm_controller_mem_init();

 #if CONFIG_MAC_BB_PD
@ -1223,6 +1236,9 @@ esp_err_t esp_bt_controller_deinit(void)
    esp_unregister_mac_bb_pd_callback(btdm_mac_bb_power_down_cb);
    esp_unregister_mac_bb_pu_callback(btdm_mac_bb_power_up_cb);
 #endif
+
+    esp_bt_power_domain_off();
+
    free(osi_funcs_p);
    osi_funcs_p = NULL;

--- a/components/bt/controller/esp32s3/bt.c
+++ b/components/bt/controller/esp32s3/bt.c
@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #include <stddef.h>
 #include <stdlib.h>
@ -407,10 +399,6 @@ static DRAM_ATTR esp_pm_lock_handle_t s_light_sleep_pm_lock;
 void IRAM_ATTR btdm_hw_mac_power_down_wrapper(void)
 {
 #if CONFIG_MAC_BB_PD
-    // le module power down
-    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_ISO);
-    SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PD);
-
    esp_mac_bb_power_down();
 #endif
 }
@ -418,10 +406,6 @@ void IRAM_ATTR btdm_hw_mac_power_down_wrapper(void)
 void IRAM_ATTR btdm_hw_mac_power_up_wrapper(void)
 {
 #if CONFIG_MAC_BB_PD
-    // le module power up
-    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PD);
-    CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_ISO);
-
    esp_mac_bb_power_up();
 #endif
 }
@ -433,6 +417,18 @@ void IRAM_ATTR btdm_backup_dma_copy_wrapper(uint32_t reg, uint32_t mem_addr, uin
 #endif
 }

+static inline void esp_bt_power_domain_on(void)
+{
+    // Bluetooth module power up
+    esp_wifi_bt_power_domain_on();
+}
+
+static inline void esp_bt_power_domain_off(void)
+{
+    // Bluetooth module power down
+    esp_wifi_bt_power_domain_off();
+}
+
 static void interrupt_set_wrapper(int32_t cpu_no, int32_t intr_source, int32_t intr_num, int32_t intr_prio)
 {
    intr_matrix_set(cpu_no, intr_source, intr_num);
@ -936,6 +932,11 @@ esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
    // overwrite some parameters
    cfg->magic = ESP_BT_CTRL_CONFIG_MAGIC_VAL;

+#if CONFIG_MAC_BB_PD
+    esp_mac_bb_pd_mem_init();
+#endif
+    esp_bt_power_domain_on();
+
    btdm_controller_mem_init();

 #if CONFIG_MAC_BB_PD
@ -1143,6 +1144,8 @@ error:
    esp_unregister_mac_bb_pu_callback(btdm_mac_bb_power_up_cb);
 #endif

+    esp_bt_power_domain_off();
+
    if (osi_funcs_p != NULL) {
        free(osi_funcs_p);
        osi_funcs_p = NULL;
--- a/components/bt/host/bluedroid/bta/dm/bta_dm_act.c
+++ b/components/bt/host/bluedroid/bta/dm/bta_dm_act.c
@ -5380,6 +5380,16 @@ void bta_dm_ble_set_data_length(tBTA_DM_MSG *p_data)
        APPL_TRACE_ERROR("%s error: Invalid connection remote_bda.", __func__);
        return;
    }
+
+    p_acl_cb->p_set_pkt_data_cback = p_data->ble_set_data_length.p_set_pkt_data_cback;
+    // if the value of the data length is same, triger callback directly
+    if(p_data->ble_set_data_length.tx_data_length == p_acl_cb->data_length_params.tx_len) {
+        if(p_data->ble_set_data_length.p_set_pkt_data_cback) {
+            (*p_data->ble_set_data_length.p_set_pkt_data_cback)(status, &p_acl_cb->data_length_params);
+        }
+        return;
+    }
+
    if(p_acl_cb->data_len_updating) {
        // aleady have one cmd
        if(p_acl_cb->data_len_waiting) {
@ -5392,14 +5402,6 @@ void bta_dm_ble_set_data_length(tBTA_DM_MSG *p_data)
            return;
        }
    } else {
-        p_acl_cb->p_set_pkt_data_cback = p_data->ble_set_data_length.p_set_pkt_data_cback;
-        // if the value of the data length is same, triger callback directly
-        if(p_data->ble_set_data_length.tx_data_length == p_acl_cb->data_length_params.tx_len) {
-            if(p_data->ble_set_data_length.p_set_pkt_data_cback) {
-                (*p_data->ble_set_data_length.p_set_pkt_data_cback)(status, &p_acl_cb->data_length_params);
-            }
-            return;
-        }
        status = BTM_SetBleDataLength(p_data->ble_set_data_length.remote_bda,
                                        p_data->ble_set_data_length.tx_data_length);
    }
--- a/components/bt/host/bluedroid/stack/btm/btm_acl.c
+++ b/components/bt/host/bluedroid/stack/btm/btm_acl.c
@ -954,8 +954,10 @@ void btm_read_remote_version_complete (UINT8 *p)
                if (HCI_LE_DATA_LEN_EXT_SUPPORTED(p_acl_cb->peer_le_features)) {
                    uint16_t data_length = controller_get_interface()->get_ble_default_data_packet_length();
                    uint16_t data_txtime = controller_get_interface()->get_ble_default_data_packet_txtime();
-                    p_acl_cb->data_len_updating = true;
-                    btsnd_hcic_ble_set_data_length(p_acl_cb->hci_handle, data_length, data_txtime);
+                    if (data_length != p_acl_cb->data_length_params.tx_len) {
+                        p_acl_cb->data_len_updating = true;
+                        btsnd_hcic_ble_set_data_length(p_acl_cb->hci_handle, data_length, data_txtime);
+                    }
                }
                l2cble_notify_le_connection (p_acl_cb->remote_addr);
            } else {
--- a/components/bt/include/esp32/include/esp_bt.h
+++ b/components/bt/include/esp32/include/esp_bt.h
@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #ifndef __ESP_BT_H__
 #define __ESP_BT_H__
@ -530,6 +522,16 @@ esp_err_t esp_bt_sleep_disable(void);
 */
 esp_err_t esp_ble_scan_dupilcate_list_flush(void);

+/**
+ * @brief bt Wi-Fi power domain power on
+ */
+void esp_wifi_bt_power_domain_on(void);
+
+/**
+ * @brief bt Wi-Fi power domain power off
+ */
+void esp_wifi_bt_power_domain_off(void);
+
 #ifdef __cplusplus
 }
 #endif
--- a/components/bt/include/esp32c3/include/esp_bt.h
+++ b/components/bt/include/esp32c3/include/esp_bt.h
@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #ifndef __ESP_BT_H__
 #define __ESP_BT_H__
@ -527,6 +519,16 @@ void esp_bt_controller_wakeup_request(void);
 */
 int esp_bt_h4tl_eif_io_event_notify(int event);

+/**
+ * @brief bt Wi-Fi power domain power on
+ */
+void esp_wifi_bt_power_domain_on(void);
+
+/**
+ * @brief bt Wi-Fi power domain power off
+ */
+void esp_wifi_bt_power_domain_off(void);
+
 #ifdef __cplusplus
 }
 #endif
--- a/components/bt/include/esp32s3/include/esp_bt.h
+++ b/components/bt/include/esp32s3/include/esp_bt.h
@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #ifndef __ESP_BT_H__
 #define __ESP_BT_H__
@ -526,6 +518,16 @@ void esp_bt_controller_wakeup_request(void);
 */
 int esp_bt_h4tl_eif_io_event_notify(int event);

+/**
+ * @brief bt Wi-Fi power domain power on
+ */
+void esp_wifi_bt_power_domain_on(void);
+
+/**
+ * @brief bt Wi-Fi power domain power off
+ */
+void esp_wifi_bt_power_domain_off(void);
+
 #ifdef __cplusplus
 }
 #endif
--- a/components/driver/test/test_i2s.c
+++ b/components/driver/test/test_i2s.c
@ -1,8 +1,9 @@
 /*
 * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
 *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: CC0-1.0
 */
+
 /**
 * I2S test environment UT_T1_I2S:
 * We use internal signals instead of external wiring, but please keep the following IO connections, or connect nothing to prevent the signal from being disturbed.
@ -14,6 +15,7 @@
 #include <string.h>
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"
+#include "freertos/queue.h"
 #include "driver/i2s.h"
 #include "driver/gpio.h"
 #include "hal/gpio_hal.h"
@ -157,12 +159,15 @@ TEST_CASE("I2S basic driver install, uninstall, set pin test", "[i2s]")

    // normal  i2s
    i2s_pin_config_t pin_config = {
+        .mck_io_num = -1,
        .bck_io_num = MASTER_BCK_IO,
        .ws_io_num = MASTER_WS_IO,
        .data_out_num = DATA_OUT_IO,
        .data_in_num = -1
    };
-    TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
+    QueueHandle_t evt_que;
+    TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 16, &evt_que));
+    TEST_ASSERT(evt_que);
    TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &pin_config));
    TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));

@ -199,6 +204,7 @@ TEST_CASE("I2S Loopback test(master tx and rx)", "[i2s]")
 #endif
    };
    i2s_pin_config_t master_pin_config = {
+        .mck_io_num = -1,
        .bck_io_num = MASTER_BCK_IO,
        .ws_io_num = MASTER_WS_IO,
        .data_out_num = DATA_OUT_IO,
@ -247,6 +253,74 @@ TEST_CASE("I2S Loopback test(master tx and rx)", "[i2s]")
    i2s_driver_uninstall(I2S_NUM_0);
 }

+#if SOC_I2S_SUPPORTS_TDM
+TEST_CASE("I2S TDM Loopback test(master tx and rx)", "[i2s]")
+{
+    // master driver installed and send data
+    i2s_config_t master_i2s_config = {
+        .mode = I2S_MODE_MASTER | I2S_MODE_TX | I2S_MODE_RX,
+        .sample_rate = SAMPLE_RATE,
+        .bits_per_sample = SAMPLE_BITS,
+        .channel_format = I2S_CHANNEL_FMT_MULTIPLE,
+        .communication_format = I2S_COMM_FORMAT_STAND_I2S,
+        .total_chan = 4,
+        .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1 | I2S_TDM_ACTIVE_CH2 | I2S_TDM_ACTIVE_CH3,
+        .dma_buf_count = 6,
+        .dma_buf_len = 100,
+        .use_apll = 0,
+        .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
+    };
+    i2s_pin_config_t master_pin_config = {
+        .mck_io_num = -1,
+        .bck_io_num = MASTER_BCK_IO,
+        .ws_io_num = MASTER_WS_IO,
+        .data_out_num = DATA_OUT_IO,
+        .data_in_num = DATA_IN_IO
+    };
+    TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
+    TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
+    i2s_test_io_config(I2S_TEST_MODE_LOOPBACK);
+    printf("\r\nheap size: %d\n", esp_get_free_heap_size());
+
+    uint8_t *data_wr = (uint8_t *)malloc(sizeof(uint8_t) * 400);
+    size_t i2s_bytes_write = 0;
+    size_t bytes_read = 0;
+    int length = 0;
+    uint8_t *i2s_read_buff = (uint8_t *)malloc(sizeof(uint8_t) * 10000);
+
+    for (int i = 0; i < 100; i++) {
+        data_wr[i] = i + 1;
+    }
+    int flag = 0; // break loop flag
+    int end_position = 0;
+    // write data to slave
+    i2s_write(I2S_NUM_0, data_wr, sizeof(uint8_t) * 400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
+    while (!flag) {
+        if (length >= 10000 - 500) {
+            break;
+        }
+        i2s_read(I2S_NUM_0, i2s_read_buff + length, sizeof(uint8_t) * 500, &bytes_read, 1000 / portMAX_DELAY);
+        if (bytes_read > 0) {
+            for (int i = length; i < length + bytes_read; i++) {
+                if (i2s_read_buff[i] == 100) {
+                    flag = 1;
+                    end_position = i;
+                    break;
+                }
+            }
+        }
+        length = length + bytes_read;
+    }
+    // test the read data right or not
+    for (int i = end_position - 99; i <= end_position; i++) {
+        TEST_ASSERT_EQUAL_UINT8((i - end_position + 100), *(i2s_read_buff + i));
+    }
+    free(data_wr);
+    free(i2s_read_buff);
+    i2s_driver_uninstall(I2S_NUM_0);
+}
+#endif
+
 #if SOC_I2S_NUM > 1
 /* ESP32S2 and ESP32C3 has only single I2S port and hence following test cases are not applicable */
 TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s]")
@ -272,6 +346,7 @@ TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s]")
 #endif
    };
    i2s_pin_config_t master_pin_config = {
+        .mck_io_num = -1,
        .bck_io_num = MASTER_BCK_IO,
        .ws_io_num = MASTER_WS_IO,
        .data_out_num = DATA_OUT_IO,
@ -302,6 +377,7 @@ TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s]")
 #endif
    };
    i2s_pin_config_t slave_pin_config = {
+        .mck_io_num = -1,
        .bck_io_num = SLAVE_BCK_IO,
        .ws_io_num = SLAVE_WS_IO,
        .data_out_num = -1,
@ -374,6 +450,7 @@ TEST_CASE("I2S write and read test(master rx and slave tx)", "[i2s]")
 #endif
    };
    i2s_pin_config_t master_pin_config = {
+        .mck_io_num = -1,
        .bck_io_num = MASTER_BCK_IO,
        .ws_io_num = MASTER_WS_IO,
        .data_out_num = -1,
@ -404,6 +481,7 @@ TEST_CASE("I2S write and read test(master rx and slave tx)", "[i2s]")
 #endif
    };
    i2s_pin_config_t slave_pin_config = {
+        .mck_io_num = -1,
        .bck_io_num = SLAVE_BCK_IO,
        .ws_io_num = SLAVE_WS_IO,
        .data_out_num = DATA_OUT_IO,
@ -477,6 +555,7 @@ TEST_CASE("I2S memory leaking test", "[i2s]")
 #endif
    };
    i2s_pin_config_t master_pin_config = {
+        .mck_io_num = -1,
        .bck_io_num = MASTER_BCK_IO,
        .ws_io_num = MASTER_WS_IO,
        .data_out_num = -1,
@ -507,6 +586,7 @@ TEST_CASE("I2S memory leaking test", "[i2s]")
 TEST_CASE("I2S APLL clock variation test", "[i2s]")
 {
    i2s_pin_config_t pin_config = {
+        .mck_io_num = -1,
        .bck_io_num = MASTER_BCK_IO,
        .ws_io_num = MASTER_WS_IO,
        .data_out_num = DATA_OUT_IO,
--- a/components/efuse/CMakeLists.txt
+++ b/components/efuse/CMakeLists.txt
@ -39,9 +39,10 @@ idf_build_get_property(python PYTHON)
 # Make common files esp_efuse_table.c and include/esp_efuse_table.h files.
 set(EFUSE_COMMON_TABLE_CSV_PATH "${COMPONENT_DIR}/${target}/esp_efuse_table.csv")

-add_custom_target(efuse_common_table COMMAND "${python}"
+add_custom_target(efuse-common-table COMMAND "${python}"
                 "${CMAKE_CURRENT_SOURCE_DIR}/efuse_table_gen.py"
                 ${EFUSE_COMMON_TABLE_CSV_PATH} ${GEN_EFUSE_TABLE_ARG})
+add_deprecated_target_alias(efuse_common_table efuse-common-table)

 ###################
 # Make custom files project/main/esp_efuse_custom_table.c and project/main/include/esp_efuse_custom_table.h files.
@ -51,15 +52,18 @@ if(${CONFIG_EFUSE_CUSTOM_TABLE})
    idf_build_get_property(project_dir PROJECT_DIR)
    get_filename_component(EFUSE_CUSTOM_TABLE_CSV_PATH "${CONFIG_EFUSE_CUSTOM_TABLE_FILENAME}"
                           ABSOLUTE BASE_DIR "${project_dir}")
-    add_custom_target(efuse_custom_table COMMAND "${python}" "${CMAKE_CURRENT_SOURCE_DIR}/efuse_table_gen.py"
+    add_custom_target(efuse-custom-table COMMAND "${python}" "${CMAKE_CURRENT_SOURCE_DIR}/efuse_table_gen.py"
                           ${EFUSE_COMMON_TABLE_CSV_PATH} ${EFUSE_CUSTOM_TABLE_CSV_PATH} ${GEN_EFUSE_TABLE_ARG})
+    add_deprecated_target_alias(efuse_custom_table efuse-custom-table)
 else()
-    add_custom_target(efuse_custom_table COMMAND)
+    add_custom_target(efuse-custom-table COMMAND)
+    add_deprecated_target_alias(efuse_custom_table efuse-custom-table)
 endif()#if(${CONFIG_EFUSE_CUSTOM_TABLE})

-add_custom_target(show_efuse_table COMMAND "${python}"
+add_custom_target(show-efuse-table COMMAND "${python}"
                  "${CMAKE_CURRENT_SOURCE_DIR}/efuse_table_gen.py"
                  ${EFUSE_COMMON_TABLE_CSV_PATH} ${EFUSE_CUSTOM_TABLE_CSV_PATH} ${GEN_EFUSE_TABLE_ARG} "--info")
+add_deprecated_target_alias(show_efuse_table show-efuse-table)

 ###################
 # Generates files for unit test. This command is run manually.
--- a/components/efuse/esp32/esp_efuse_table.csv
+++ b/components/efuse/esp32/esp_efuse_table.csv
@ -6,7 +6,7 @@
 ##########################################################################
 # *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
 # !!!!!!!!!!! #
-# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table"
+# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
 # this will generate new source files, next rebuild all the sources.
 # !!!!!!!!!!! #

--- a/components/efuse/esp32c3/esp_efuse_table.csv
+++ b/components/efuse/esp32c3/esp_efuse_table.csv
@ -6,7 +6,7 @@
 ##########################################################################
 # *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
 # !!!!!!!!!!! #
-# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table"
+# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
 # this will generate new source files, next rebuild all the sources.
 # !!!!!!!!!!! #

--- a/components/efuse/esp32h2/esp_efuse_table.csv
+++ b/components/efuse/esp32h2/esp_efuse_table.csv
@ -6,7 +6,7 @@
 ##########################################################################
 # *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
 # !!!!!!!!!!! #
-# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table"
+# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
 # this will generate new source files, next rebuild all the sources.
 # !!!!!!!!!!! #

--- a/components/efuse/esp32s2/esp_efuse_table.csv
+++ b/components/efuse/esp32s2/esp_efuse_table.csv
@ -6,7 +6,7 @@
 ##########################################################################
 # *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
 # !!!!!!!!!!! #
-# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table"
+# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
 # this will generate new source files, next rebuild all the sources.
 # !!!!!!!!!!! #

--- a/components/efuse/esp32s3/esp_efuse_table.csv
+++ b/components/efuse/esp32s3/esp_efuse_table.csv
@ -5,7 +5,7 @@
 #                   |     EFUSE_BLK10)|            |            |        #
 ##########################################################################
 # !!!!!!!!!!! #
-# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table"
+# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
 # this will generate new source files, next rebuild all the sources.
 # !!!!!!!!!!! #

--- a/components/esp-tls/esp-tls-crypto/esp_tls_crypto.c
+++ b/components/esp-tls/esp-tls-crypto/esp_tls_crypto.c
@ -56,7 +56,7 @@ static int esp_crypto_base64_encode_woflSSL(unsigned char *dst, size_t dlen, siz
        const unsigned char *src, size_t slen)
 {
    *olen = dlen;
-    return Base64_Encode((const byte *) src, (word32) slen, (byte *) dst, (word32 *) olen);
+    return Base64_Encode_NoNl((const byte *) src, (word32) slen, (byte *) dst, (word32 *) olen);
 }

 #else
--- a/components/esp32c3/Kconfig
+++ b/components/esp32c3/Kconfig
@ -192,23 +192,4 @@ menu "ESP32C3-Specific"
            If enabled, this disables the linking of binary libraries in the application build. Note
            that after enabling this Wi-Fi/Bluetooth will not work.

-    config ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND
-        bool "light sleep GPIO reset workaround"
-        default y
-        select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE
-        help
-            ESP32C3 will reset at wake-up if GPIO is received a small electrostatic pulse during
-            light sleep, with specific condition
-
-            - GPIO needs to be configured as input-mode only
-            - The pin receives a small electrostatic pulse, and reset occurs when the pulse
-              voltage is higher than 6 V
-
-            For GPIO set to input mode only, it is not a good practice to leave it open/floating,
-            The hardware design needs to controlled it with determined supply or ground voltage
-            is necessary.
-
-            This option provides a software workaround for this issue. Configure to isolate all
-            GPIO pins in sleep state.
-
 endmenu  # ESP32C3-Specific
--- a/components/esp_http_client/esp_http_client.c
+++ b/components/esp_http_client/esp_http_client.c
@ -724,7 +724,9 @@ esp_err_t esp_http_client_cleanup(esp_http_client_handle_t client)
        return ESP_FAIL;
    }
    esp_http_client_close(client);
-    esp_transport_list_destroy(client->transport_list);
+    if (client->transport_list) {
+        esp_transport_list_destroy(client->transport_list);
+    }
    if (client->request) {
        http_header_destroy(client->request->headers);
        if (client->request->buffer) {
--- a/components/esp_hw_support/Kconfig
+++ b/components/esp_hw_support/Kconfig
@ -34,6 +34,25 @@ menu "Hardware Settings"
            bool
            default y if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3

+        config ESP_SLEEP_GPIO_RESET_WORKAROUND
+            bool "light sleep GPIO reset workaround"
+            default y if IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3
+            select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE
+            help
+                esp32c3 and esp32s3 will reset at wake-up if GPIO is received a small electrostatic
+                pulse during light sleep, with specific condition
+
+                - GPIO needs to be configured as input-mode only
+                - The pin receives a small electrostatic pulse, and reset occurs when the pulse
+                  voltage is higher than 6 V
+
+                For GPIO set to input mode only, it is not a good practice to leave it open/floating,
+                The hardware design needs to controlled it with determined supply or ground voltage
+                is necessary.
+
+                This option provides a software workaround for this issue. Configure to isolate all
+                GPIO pins in sleep state.
+
        config ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND
            bool "PSRAM leakage current workaround in light sleep"
            depends on SPIRAM
--- a/components/esp_hw_support/port/esp32/rtc_init.c
+++ b/components/esp_hw_support/port/esp32/rtc_init.c
@ -88,6 +88,9 @@ void rtc_init(rtc_config_t cfg)
        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
    }
+    /* force power down wifi and bt power domain */
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);

    REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
    REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
--- a/components/esp_hw_support/port/esp32c3/rtc_init.c
+++ b/components/esp_hw_support/port/esp32c3/rtc_init.c
@ -143,6 +143,13 @@ void rtc_init(rtc_config_t cfg)
        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
    }
+    /* force power down wifi and bt power domain */
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
+    /* force power down bt power domain */
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_ISO);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PD);
+
    REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
    REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
 }
--- a/components/esp_hw_support/port/esp32c3/rtc_time.c
+++ b/components/esp_hw_support/port/esp32c3/rtc_time.c
@ -57,16 +57,16 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
    if (cal_clk == RTC_CAL_8MD256) {
        SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
    }
-    /* Prepare calibration */
-    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
    /* There may be another calibration process already running during we call this function,
     * so we should wait the last process is done.
     */
-    if (!GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
-        if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
-            while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY));
-        }
+    if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
+        while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)
+               && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
    }
+
+    /* Prepare calibration */
+    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
    CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
    /* Figure out how long to wait for calibration to finish */
--- a/components/esp_hw_support/port/esp32h2/rtc_time.c
+++ b/components/esp_hw_support/port/esp32h2/rtc_time.c
@ -54,16 +54,16 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
    if (cal_clk == RTC_CAL_RC32K && !dig_rc32k_state) {
        REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_RC32K_EN, 1);
    }
-    /* Prepare calibration */
-    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
    /* There may be another calibration process already running during we call this function,
     * so we should wait the last process is done.
     */
-    if (!GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
-        if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
-            while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY));
-        }
+    if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
+        while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)
+               && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
    }
+
+    /* Prepare calibration */
+    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
    CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
    /* Figure out how long to wait for calibration to finish */
--- a/components/esp_hw_support/port/esp32s2/rtc_init.c
+++ b/components/esp_hw_support/port/esp32s2/rtc_init.c
@ -145,6 +145,9 @@ void rtc_init(rtc_config_t cfg)
        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
    }
+    /* force power down wifi and bt power domain */
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);

 #if !CONFIG_IDF_ENV_FPGA
    if (cfg.cali_ocode) {
--- a/components/esp_hw_support/port/esp32s2/rtc_time.c
+++ b/components/esp_hw_support/port/esp32s2/rtc_time.c
@ -30,16 +30,16 @@
 */
 static uint32_t rtc_clk_cal_internal_oneoff(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
 {
-    /* Prepare calibration */
-    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
    /* There may be another calibration process already running during we call this function,
     * so we should wait the last process is done.
     */
-    if (!GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
-        if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
-            while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY));
-        }
+    if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
+        while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)
+               && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
    }
+
+    /* Prepare calibration */
+    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
    CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
    /* Figure out how long to wait for calibration to finish */
--- a/components/esp_hw_support/port/esp32s3/rtc_init.c
+++ b/components/esp_hw_support/port/esp32s3/rtc_init.c
@ -21,18 +21,7 @@
 #include "esp_attr.h"
 #include "esp_efuse.h"
 #include "esp_efuse_table.h"
-
-#ifndef BOOTLOADER_BUILD
-/**
- * TODO: IDF-3204
- * Temporarily solution. Depends on MSPI
- * Final solution: the rtc should not depend on MSPI. We should do rtc related before Flash init
- */
 #include "esp_private/spi_flash_os.h"
-#include "esp32s3/rom/cache.h"
-#include "freertos/portmacro.h"
-portMUX_TYPE rtc_init_spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
-#endif


 #define RTC_CNTL_MEM_FORCE_NOISO (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
@ -192,6 +181,9 @@ void rtc_init(rtc_config_t cfg)
        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
    }
+    /* force power down wifi and bt power domain */
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
+    SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);

    REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
    REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
@ -245,39 +237,23 @@ static void set_ocode_by_efuse(int calib_version)
    REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1);
 }

-#ifndef BOOTLOADER_BUILD
-//TODO: IDF-3204
-//Temporary solution, these 2 functions should be defined elsewhere, because similar operations are also needed elsewhere
-//Final solution: the rtc should not depend on MSPI. We should do rtc related before Flash init
-static void IRAM_ATTR enter_mspi_low_speed_mode_safe(void)
-{
-    portENTER_CRITICAL(&rtc_init_spinlock);
-    Cache_Freeze_ICache_Enable(1);
-    Cache_Freeze_DCache_Enable(1);
-    spi_timing_enter_mspi_low_speed_mode(false);
-    Cache_Freeze_DCache_Disable();
-    Cache_Freeze_ICache_Disable();
-    portEXIT_CRITICAL(&rtc_init_spinlock);
-}
-
-static void IRAM_ATTR enter_mspi_high_speed_mode_safe(void)
-{
-    portENTER_CRITICAL(&rtc_init_spinlock);
-    Cache_Freeze_ICache_Enable(1);
-    Cache_Freeze_DCache_Enable(1);
-    spi_timing_enter_mspi_high_speed_mode(false);
-    Cache_Freeze_DCache_Disable();
-    Cache_Freeze_ICache_Disable();
-    portEXIT_CRITICAL(&rtc_init_spinlock);
-}
-#endif
-
-//TODO: IDF-3204
-//This function will change the system clock source to XTAL. Under lower frequency (e.g. XTAL), MSPI timing tuning configures should be modified accordingly.
-static void IRAM_ATTR calibrate_ocode(void)
+/**
+ * TODO: IDF-4141
+ * 1. This function will change the system clock source to XTAL. Under lower frequency (e.g. XTAL), MSPI timing tuning configures should be modified accordingly.
+ * 2. RTC related should be done before SPI0 initialisation
+ */
+static void calibrate_ocode(void)
 {
 #ifndef BOOTLOADER_BUILD
-    enter_mspi_low_speed_mode_safe();
+    /**
+     * Background:
+     * 1. Following code will switch the system clock to XTAL first, to self-calibrate the OCode.
+     * 2. For some of the MSPI high frequency setting (e.g. 80M DDR mode Flash or PSRAM), timing tuning is required.
+     *    Certain delay will be added to the MSPI RX direction.
+     *
+     * When CPU clock switches down, the delay should be cleared. Therefore here we call this function to remove the delays.
+     */
+    spi_timing_change_speed_mode_cache_safe(true);
 #endif
    /*
    Bandgap output voltage is not precise when calibrate o-code by hardware sometimes, so need software o-code calibration (must turn off PLL).
@ -327,6 +303,7 @@ static void IRAM_ATTR calibrate_ocode(void)
    }
    rtc_clk_cpu_freq_set_config(&old_config);
 #ifndef BOOTLOADER_BUILD
-    enter_mspi_high_speed_mode_safe();
+    //System clock is switched back to PLL. Here we switch to the MSPI high speed mode, add the delays back
+    spi_timing_change_speed_mode_cache_safe(false);
 #endif
 }
--- a/components/esp_hw_support/port/esp32s3/rtc_time.c
+++ b/components/esp_hw_support/port/esp32s3/rtc_time.c
@ -55,16 +55,16 @@ uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
    if (cal_clk == RTC_CAL_8MD256) {
        SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
    }
-    /* Prepare calibration */
-    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
    /* There may be another calibration process already running during we call this function,
     * so we should wait the last process is done.
     */
-    if (!GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
-        if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
-            while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY));
-        }
+    if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING)) {
+        while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)
+               && !GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT));
    }
+
+    /* Prepare calibration */
+    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
    CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
    /* Figure out how long to wait for calibration to finish */
--- a/components/esp_hw_support/sdkconfig.rename
+++ b/components/esp_hw_support/sdkconfig.rename
@ -6,3 +6,4 @@ CONFIG_TWO_UNIVERSAL_MAC_ADDRESS                        CONFIG_ESP32_UNIVERSAL_M
 CONFIG_FOUR_UNIVERSAL_MAC_ADDRESS                       CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR

 CONFIG_ESP_SYSTEM_PD_FLASH                              CONFIG_ESP_SLEEP_POWER_DOWN_FLASH
+CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND         CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND
--- a/components/esp_hw_support/sleep_modes.c
+++ b/components/esp_hw_support/sleep_modes.c
@ -188,12 +188,41 @@ static void touch_wakeup_prepare(void);
 static void esp_deep_sleep_wakeup_prepare(void);
 #endif

+#if SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
+static RTC_FAST_ATTR esp_deep_sleep_wake_stub_fn_t wake_stub_fn_handler = NULL;
+
+static void RTC_IRAM_ATTR __attribute__((used, noinline)) esp_wake_stub_start(void)
+{
+    if (wake_stub_fn_handler) {
+        (*wake_stub_fn_handler)();
+    }
+}
+
+/* We must have a default deep sleep wake stub entry function, which must be
+ * located at the start address of the RTC fast memory, and its implementation
+ * must be simple enough to ensure that there is no litteral data before the
+ * wake stub entry, otherwise, the litteral data before the wake stub entry
+ * will not be CRC checked. */
+static void __attribute__((section(".rtc.entry.text"))) esp_wake_stub_entry(void)
+{
+#define _SYM2STR(s) # s
+#define SYM2STR(s)  _SYM2STR(s)
+    // call4 has a larger effective addressing range (-524284 to 524288 bytes),
+    // which is sufficient for instruction addressing in RTC fast memory.
+    __asm__ __volatile__ ("call4 " SYM2STR(esp_wake_stub_start) "\n");
+}
+#endif // SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
+
 /* Wake from deep sleep stub
   See esp_deepsleep.h esp_wake_deep_sleep() comments for details.
 */
 esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void)
 {
+#if SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
+    esp_deep_sleep_wake_stub_fn_t stub_ptr = wake_stub_fn_handler;
+#else
    esp_deep_sleep_wake_stub_fn_t stub_ptr = (esp_deep_sleep_wake_stub_fn_t) REG_READ(RTC_ENTRY_ADDR_REG);
+#endif
    if (!esp_ptr_executable(stub_ptr)) {
        return NULL;
    }
@ -202,7 +231,11 @@ esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void)

 void esp_set_deep_sleep_wake_stub(esp_deep_sleep_wake_stub_fn_t new_stub)
 {
+#if SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
+    wake_stub_fn_handler = new_stub;
+#else
    REG_WRITE(RTC_ENTRY_ADDR_REG, (uint32_t)new_stub);
+#endif
 }

 void RTC_IRAM_ATTR esp_default_wake_deep_sleep(void)
@ -315,15 +348,6 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
    // For deep sleep, wait for the contents of UART FIFO to be sent.
    bool deep_sleep = pd_flags & RTC_SLEEP_PD_DIG;

-#if !CONFIG_FREERTOS_UNICORE && CONFIG_IDF_TARGET_ESP32S3 && CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
-    /* Currently only safe to use deep sleep wake stub & RTC memory as heap in single core mode.
-
-       For ESP32-S3, either disable ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP in config or find a way to set the
-       deep sleep wake stub to NULL.
-     */
-    assert(!deep_sleep || esp_get_deep_sleep_wake_stub() == NULL);
-#endif
-
    if (deep_sleep) {
        flush_uarts();
    } else {
@ -416,18 +440,27 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags)
         */
        portENTER_CRITICAL(&spinlock_rtc_deep_sleep);

+#if SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY
+        extern char _rtc_text_start[];
+#if CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
+        extern char _rtc_noinit_end[];
+        size_t rtc_fast_length = (size_t)_rtc_noinit_end - (size_t)_rtc_text_start;
+#else
+        extern char _rtc_force_fast_end[];
+        size_t rtc_fast_length = (size_t)_rtc_force_fast_end - (size_t)_rtc_text_start;
+#endif
+        esp_rom_set_rtc_wake_addr((esp_rom_wake_func_t)esp_wake_stub_entry, rtc_fast_length);
+        result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu);
+#else
 #if !CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
        /* If not possible stack is in RTC FAST memory, use the ROM function to calculate the CRC and save ~140 bytes IRAM */
-#if CONFIG_IDF_TARGET_ESP32S3//TODO: WIFI-3542
-        result = 0;
-#else
        set_rtc_memory_crc();
        result = call_rtc_sleep_start(reject_triggers, config.lslp_mem_inf_fpu);
-#endif
 #else
        /* Otherwise, need to call the dedicated soc function for this */
        result = rtc_deep_sleep_start(s_config.wakeup_triggers, reject_triggers);
 #endif
+#endif // SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY

        portEXIT_CRITICAL(&spinlock_rtc_deep_sleep);
    } else {
@ -466,11 +499,17 @@ void IRAM_ATTR esp_deep_sleep_start(void)
    esp_brownout_disable();
 #endif //CONFIG_IDF_TARGET_ESP32S2

+    esp_sync_counters_rtc_and_frc();
+
+    /* Disable interrupts and stall another core in case another task writes
+     * to RTC memory while we calculate RTC memory CRC.
+     */
+    portENTER_CRITICAL(&spinlock_rtc_deep_sleep);
+    esp_ipc_isr_stall_other_cpu();
+
    // record current RTC time
    s_config.rtc_ticks_at_sleep_start = rtc_time_get();

-    // record current RTC time
-    esp_sync_counters_rtc_and_frc();
    // Configure wake stub
    if (esp_get_deep_sleep_wake_stub() == NULL) {
        esp_set_deep_sleep_wake_stub(esp_wake_deep_sleep);
@ -502,6 +541,9 @@ void IRAM_ATTR esp_deep_sleep_start(void)
    while (1) {
        ;
    }
+    // Never returns here
+    esp_ipc_isr_release_other_cpu();
+    portEXIT_CRITICAL(&spinlock_rtc_deep_sleep);
 }

 /**
--- a/components/esp_netif/include/esp_netif_ip_addr.h
+++ b/components/esp_netif/include/esp_netif_ip_addr.h
@ -1,20 +1,13 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #ifndef _ESP_NETIF_IP_ADDR_H_
 #define _ESP_NETIF_IP_ADDR_H_

+#include <stdint.h>
 #include <machine/endian.h>

 #ifdef __cplusplus
--- a/components/esp_netif/include/esp_netif_types.h
+++ b/components/esp_netif/include/esp_netif_types.h
@ -1,20 +1,18 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #ifndef _ESP_NETIF_TYPES_H_
 #define _ESP_NETIF_TYPES_H_

+#include <stdbool.h>
+#include <stdint.h>
+#include "esp_event_base.h"
+#include "esp_err.h"
+#include "esp_netif_ip_addr.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
--- a/components/esp_phy/CMakeLists.txt
+++ b/components/esp_phy/CMakeLists.txt
@ -14,13 +14,29 @@ else()
    set(srcs "src/phy_init.c")
 endif()

-idf_component_register(SRCS "${srcs}"
-                    INCLUDE_DIRS "include" "${idf_target}/include"
-                    PRIV_REQUIRES nvs_flash
-                    LDFRAGMENTS "${ldfragments}")
-
 idf_build_get_property(build_dir BUILD_DIR)

+if(CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN)
+    if(NOT EXISTS "${build_dir}/phy_multiple_init_data.bin")
+        file(COPY ${CMAKE_CURRENT_SOURCE_DIR}/${idf_target}/phy_multiple_init_data.bin DESTINATION "${build_dir}")
+    endif()
+endif()
+
+if(CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN_EMBED)
+    idf_component_register(SRCS "${srcs}"
+                        INCLUDE_DIRS "include" "${idf_target}/include"
+                        PRIV_REQUIRES nvs_flash
+                        LDFRAGMENTS "${ldfragments}"
+                        EMBED_FILES "${build_dir}/phy_multiple_init_data.bin"
+                        )
+else()
+    idf_component_register(SRCS "${srcs}"
+                        INCLUDE_DIRS "include" "${idf_target}/include"
+                        PRIV_REQUIRES nvs_flash
+                        LDFRAGMENTS "${ldfragments}"
+                        )
+endif()
+
 set(target_name "${idf_target}")
 target_link_libraries(${COMPONENT_LIB} PUBLIC "-L \"${CMAKE_CURRENT_SOURCE_DIR}/lib/${target_name}\"")

@ -47,12 +63,15 @@ if(link_binary_libs)
    endif()
 endif()

-if(CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION)
+if(CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION)
    idf_component_get_property(esp_common_dir esp_common COMPONENT_DIR)
    partition_table_get_partition_info(phy_partition_offset "--partition-type data --partition-subtype phy" "offset")

-    if(CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN)
-        set(phy_init_data_bin "${CMAKE_CURRENT_SOURCE_DIR}/phy_multiple_init_data.bin")
+    if(CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN)
+        set(phy_init_data_bin "${build_dir}/phy_multiple_init_data.bin")
+        if(CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN_EMBED)
+            set(COMPONENT_EMBED_FILES "${build_dir}/phy_multiple_init_data.bin")
+        endif()
    else()
        set(phy_init_data_bin "${build_dir}/phy_init_data.bin")

--- a/components/esp_phy/Kconfig
+++ b/components/esp_phy/Kconfig
@ -1,6 +1,6 @@
 menu "PHY"

-    config ESP32_PHY_CALIBRATION_AND_DATA_STORAGE
+    config ESP_PHY_CALIBRATION_AND_DATA_STORAGE
        bool "Store phy calibration data in NVS"
        default y
        help
@ -15,7 +15,7 @@ menu "PHY"
            2.Because of your board design, each time when you do calibration, the result are too unstable.
            If unsure, choose 'y'.

-    menuconfig ESP32_PHY_INIT_DATA_IN_PARTITION
+    menuconfig ESP_PHY_INIT_DATA_IN_PARTITION
        bool "Use a partition to store PHY init data"
        default n
        help
@ -31,20 +31,20 @@ menu "PHY"

            If unsure, choose 'n'.

-    config ESP32_PHY_DEFAULT_INIT_IF_INVALID
+    config ESP_PHY_DEFAULT_INIT_IF_INVALID
        bool "Reset default PHY init data if invalid"
        default n
-        depends on ESP32_PHY_INIT_DATA_IN_PARTITION
+        depends on ESP_PHY_INIT_DATA_IN_PARTITION
        help
            If enabled, PHY init data will be restored to default if
            it cannot be verified successfully to avoid endless bootloops.

            If unsure, choose 'n'.

-    if ESP32_PHY_INIT_DATA_IN_PARTITION
-        config ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+    if ESP_PHY_INIT_DATA_IN_PARTITION
+        config ESP_PHY_MULTIPLE_INIT_DATA_BIN
            bool "Support multiple PHY init data bin"
-            depends on ESP32_PHY_INIT_DATA_IN_PARTITION
+            depends on ESP_PHY_INIT_DATA_IN_PARTITION
            default n
            help
                If enabled, the corresponding PHY init data type can be automatically switched
@ -57,9 +57,17 @@ menu "PHY"
                3. Country configured by API esp_wifi_set_country()
                and the parameter policy is WIFI_COUNTRY_POLICY_AUTO.

-        config ESP32_PHY_INIT_DATA_ERROR
+        config ESP_PHY_MULTIPLE_INIT_DATA_BIN_EMBED
+            bool "Support embedded multiple phy init data bin to app bin"
+            depends on ESP_PHY_MULTIPLE_INIT_DATA_BIN
+            default n
+            help
+                If enabled, multiple phy init data bin will embedded into app bin
+                If not enabled, multiple phy init data bin will still leave alone, and need to be flashed by users.
+
+        config ESP_PHY_INIT_DATA_ERROR
            bool "Terminate operation when PHY init data error"
-            depends on ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+            depends on ESP_PHY_MULTIPLE_INIT_DATA_BIN
            default n
            help
                If enabled, when an error occurs while the PHY init data is updated,
@ -67,7 +75,7 @@ menu "PHY"
                If not enabled, the PHY init data will not be updated when an error occurs.
    endif

-    config ESP32_PHY_MAX_WIFI_TX_POWER
+    config ESP_PHY_MAX_WIFI_TX_POWER
        int "Max WiFi TX power (dBm)"
        range 10 20
        default 20
@ -75,11 +83,11 @@ menu "PHY"
            Set maximum transmit power for WiFi radio. Actual transmit power for high
            data rates may be lower than this setting.

-    config ESP32_PHY_MAX_TX_POWER
+    config ESP_PHY_MAX_TX_POWER
        int
-        default ESP32_PHY_MAX_WIFI_TX_POWER
+        default ESP_PHY_MAX_WIFI_TX_POWER

-    config ESP32_PHY_MAC_BB_PD
+    config ESP_PHY_MAC_BB_PD
        bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled"
        depends on ((IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3) && FREERTOS_USE_TICKLESS_IDLE)
        default n
@ -89,7 +97,7 @@ menu "PHY"
            by a small amount but increases RAM use by approximately 4 KB(Wi-Fi only),
            2 KB(Bluetooth only) or 5.3 KB(Wi-Fi + Bluetooth).

-    config ESP32_REDUCE_PHY_TX_POWER
+    config ESP_PHY_REDUCE_TX_POWER
        bool "Reduce PHY TX power when brownout reset"
        depends on ESP32_BROWNOUT_DET
        default y
--- a/components/esp_phy/Makefile.projbuild
+++ b/components/esp_phy/Makefile.projbuild
@ -1,9 +1,9 @@
-ifdef CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION
+ifdef CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION

 ESP_PHY_COMPONENT_PATH := $(COMPONENT_PATH)

-ifdef CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
-PHY_INIT_DATA_BIN = $(ESP_PHY_COMPONENT_PATH)/phy_multiple_init_data.bin
+ifdef CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
+PHY_INIT_DATA_BIN = $(ESP_PHY_COMPONENT_PATH)/$(IDF_TARGET)/phy_multiple_init_data.bin
 else
 PHY_INIT_DATA_OBJ = $(BUILD_DIR_BASE)/phy_init_data.o
 PHY_INIT_DATA_BIN = $(BUILD_DIR_BASE)/phy_init_data.bin
@ -27,7 +27,7 @@ phy_init_data-flash: $(PHY_INIT_DATA_BIN)
 	@echo "Flashing PHY init data..."
 	$(PHY_INIT_DATA_FLASH_CMD)

-ifndef CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+ifndef CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
 phy_init_data-clean:
 	rm -f $(PHY_INIT_DATA_BIN) $(PHY_INIT_DATA_OBJ)

@ -37,4 +37,4 @@ endif
 all: phy_init_data
 flash: phy_init_data

-endif # CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION
+endif # CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION
--- a/components/esp_phy/esp32/include/phy_init_data.h
+++ b/components/esp_phy/esp32/include/phy_init_data.h
@ -1,16 +1,8 @@
-// Copyright 2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #ifndef PHY_INIT_DATA_H
 #define PHY_INIT_DATA_H /* don't use #pragma once here, we compile this file sometimes */
@ -23,11 +15,11 @@
 #define PHY_INIT_MAGIC "PHYINIT"

 // define the lowest tx power as LOWEST_PHY_TX_POWER
-#define PHY_TX_POWER_LOWEST LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 52)
+#define PHY_TX_POWER_LOWEST LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 52)
 #define PHY_TX_POWER_OFFSET 44
 #define PHY_TX_POWER_NUM    5

-#if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
 #define PHY_CRC_ALGORITHM 1
 #define PHY_COUNTRY_CODE_LEN 2
 #define PHY_INIT_DATA_TYPE_OFFSET 126
@ -83,12 +75,12 @@ static const esp_phy_init_data_t phy_init_data= { {
        0x18,
        0x18,
        0x18,
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 40, 78),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 40, 72),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 40, 66),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 40, 60),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 40, 56),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 40, 52),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 40, 78),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 40, 72),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 40, 66),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 40, 60),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 40, 56),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 40, 52),
        0,
        1,
        1,
@ -150,7 +142,7 @@ static const esp_phy_init_data_t phy_init_data= { {

 static const char phy_init_magic_post[] = PHY_INIT_MAGIC;

-#if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
 /**
 * @brief PHY init data control infomation structure
 */
--- a/components/esp_phy/esp32/phy_multiple_init_data.bin
+++ b/components/esp_phy/esp32/phy_multiple_init_data.bin
--- a/components/esp_phy/esp32c3/include/phy_init_data.h
+++ b/components/esp_phy/esp32c3/include/phy_init_data.h
@ -1,16 +1,8 @@
-// Copyright 2016-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #ifndef PHY_INIT_DATA_H
 #define PHY_INIT_DATA_H /* don't use #pragma once here, we compile this file sometimes */
@ -27,11 +19,11 @@ extern "C" {
 #define PHY_INIT_MAGIC "PHYINIT"

 // define the lowest tx power as LOWEST_PHY_TX_POWER
-#define PHY_TX_POWER_LOWEST LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 52)
+#define PHY_TX_POWER_LOWEST LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 52)
 #define PHY_TX_POWER_OFFSET 44
 #define PHY_TX_POWER_NUM    5

-#if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
 #define PHY_CRC_ALGORITHM 1
 #define PHY_COUNTRY_CODE_LEN 2
 #define PHY_INIT_DATA_TYPE_OFFSET 126
@ -46,20 +38,20 @@ static const char __attribute__((section(".rodata"))) phy_init_magic_pre[] = PHY
 static const esp_phy_init_data_t phy_init_data= { {
        0x00,
        0x00,
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x50),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x50),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x50),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x4c),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x4c),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x4c),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x44),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x4a),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x46),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x46),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x42),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x44),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4a),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x46),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x46),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x42),
        0x00,
        0x00,
        0x00,
@ -160,7 +152,7 @@ static const esp_phy_init_data_t phy_init_data= { {

 static const char __attribute__((section(".rodata"))) phy_init_magic_post[] = PHY_INIT_MAGIC;

-#if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
 /**
 * @brief PHY init data control infomation structure
 */
--- a/components/esp_phy/esp32c3/phy_multiple_init_data.bin
+++ b/components/esp_phy/esp32c3/phy_multiple_init_data.bin
--- a/components/esp_phy/esp32s2/include/phy_init_data.h
+++ b/components/esp_phy/esp32s2/include/phy_init_data.h
@ -1,16 +1,8 @@
-// Copyright 2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #ifndef PHY_INIT_DATA_H
 #define PHY_INIT_DATA_H /* don't use #pragma once here, we compile this file sometimes */
@ -27,11 +19,11 @@ extern "C" {
 #define PHY_INIT_MAGIC "PHYINIT"

 // define the lowest tx power as LOWEST_PHY_TX_POWER
-#define PHY_TX_POWER_LOWEST LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 52)
+#define PHY_TX_POWER_LOWEST LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 52)
 #define PHY_TX_POWER_OFFSET 44
 #define PHY_TX_POWER_NUM    5

-#if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
 #define PHY_CRC_ALGORITHM 1
 #define PHY_COUNTRY_CODE_LEN 2
 #define PHY_INIT_DATA_TYPE_OFFSET 126
@ -88,12 +80,12 @@ static const esp_phy_init_data_t phy_init_data= { {
        0x18,
        0x18,
        0x18,
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 84),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 72),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 66),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 60),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 56),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 52),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 84),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 72),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 66),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 60),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 56),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 52),
        0,
        1,
        1,
@ -155,7 +147,7 @@ static const esp_phy_init_data_t phy_init_data= { {

 static const char phy_init_magic_post[] = PHY_INIT_MAGIC;

-#if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
 /**
 * @brief PHY init data control infomation structure
 */
--- a/components/esp_phy/esp32s2/phy_multiple_init_data.bin
+++ b/components/esp_phy/esp32s2/phy_multiple_init_data.bin
--- a/components/esp_phy/esp32s3/include/phy_init_data.h
+++ b/components/esp_phy/esp32s3/include/phy_init_data.h
@ -1,16 +1,8 @@
-// Copyright 2016-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2016-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #ifndef PHY_INIT_DATA_H
 #define PHY_INIT_DATA_H /* don't use #pragma once here, we compile this file sometimes */
@ -27,11 +19,11 @@ extern "C" {
 #define PHY_INIT_MAGIC "PHYINIT"

 // define the lowest tx power as LOWEST_PHY_TX_POWER
-#define PHY_TX_POWER_LOWEST LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 52)
+#define PHY_TX_POWER_LOWEST LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 52)
 #define PHY_TX_POWER_OFFSET 44
 #define PHY_TX_POWER_NUM    5

-#if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
 #define PHY_CRC_ALGORITHM 1
 #define PHY_COUNTRY_CODE_LEN 2
 #define PHY_INIT_DATA_TYPE_OFFSET 126
@ -46,20 +38,20 @@ static const char phy_init_magic_pre[] = PHY_INIT_MAGIC;
 static const esp_phy_init_data_t phy_init_data= { {
        0x00,
        0x00,
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x50),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x50),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x50),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x4c),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x4c),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x4c),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x48),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x44),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x4a),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x46),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x46),
-        LIMIT(CONFIG_ESP32_PHY_MAX_TX_POWER * 4, 0, 0x42),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x50),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4c),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x48),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x44),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x4a),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x46),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x46),
+        LIMIT(CONFIG_ESP_PHY_MAX_TX_POWER * 4, 0, 0x42),
        0x00,
        0x00,
        0x00,
@ -160,7 +152,7 @@ static const esp_phy_init_data_t phy_init_data= { {

 static const char phy_init_magic_post[] = PHY_INIT_MAGIC;

-#if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
 /**
 * @brief PHY init data control infomation structure
 */
--- a/components/esp_phy/esp32s3/phy_multiple_init_data.bin
+++ b/components/esp_phy/esp32s3/phy_multiple_init_data.bin
--- a/components/esp_phy/include/esp_phy_init.h
+++ b/components/esp_phy/include/esp_phy_init.h
@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #pragma once
 #include <stdint.h>
@ -48,7 +40,7 @@ typedef enum {
    PHY_RF_CAL_FULL    = 0x00000002         /*!< Do full RF calibration. Produces best results, but also consumes a lot of time and current. Suggested to be used once. */
 } esp_phy_calibration_mode_t;

-#if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
 /**
 * @brief PHY init data type
 */
@ -220,7 +212,7 @@ int64_t esp_phy_rf_get_on_ts(void);
 esp_err_t esp_phy_update_country_info(const char *country);


-#if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
 /**
 * @brief Apply PHY init bin to PHY
 * @return ESP_OK on success.
--- a/components/esp_phy/include/phy.h
+++ b/components/esp_phy/include/phy.h
@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #pragma once
 #include "esp_phy_init.h"
--- a/components/esp_phy/linker.lf
+++ b/components/esp_phy/linker.lf
@ -25,3 +25,4 @@ entries:
    if ESP_WIFI_SLP_IRAM_OPT =y:
        phy_init:esp_phy_enable (noflash)
        phy_init:esp_phy_disable (noflash)
+        phy_init:esp_wifi_bt_power_domain_off (noflash)
--- a/components/esp_phy/sdkconfig.rename
+++ b/components/esp_phy/sdkconfig.rename
@ -1,5 +1,14 @@
 # sdkconfig replacement configurations for deprecated options formatted as
 # CONFIG_DEPRECATED_OPTION CONFIG_NEW_OPTION

-CONFIG_MAC_BB_PD                        CONFIG_ESP32_PHY_MAC_BB_PD
-CONFIG_REDUCE_PHY_TX_POWER              CONFIG_ESP32_REDUCE_PHY_TX_POWER
+CONFIG_MAC_BB_PD                                    CONFIG_ESP32_PHY_MAC_BB_PD
+CONFIG_REDUCE_PHY_TX_POWER                          CONFIG_ESP32_REDUCE_PHY_TX_POWER
+CONFIG_ESP32_PHY_MAC_BB_PD                          CONFIG_ESP_PHY_MAC_BB_PD
+CONFIG_ESP32_REDUCE_PHY_TX_POWER                    CONFIG_ESP_PHY_REDUCE_TX_POWER
+CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE       CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE
+CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION             CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION
+CONFIG_ESP32_PHY_DEFAULT_INIT_IF_INVALID            CONFIG_ESP_PHY_DEFAULT_INIT_IF_INVALID
+CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN     CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
+CONFIG_ESP32_PHY_INIT_DATA_ERROR                    CONFIG_ESP_PHY_INIT_DATA_ERROR
+CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER                  CONFIG_ESP_PHY_MAX_WIFI_TX_POWER
+CONFIG_ESP32_PHY_MAX_TX_POWER                       CONFIG_ESP_PHY_MAX_TX_POWER
--- a/components/esp_phy/src/phy_init.c
+++ b/components/esp_phy/src/phy_init.c
@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #include <stddef.h>
 #include <stdlib.h>
@ -36,11 +28,10 @@
 #include "esp_rom_crc.h"
 #include "esp_rom_sys.h"

-#if CONFIG_IDF_TARGET_ESP32C3
 #include "soc/rtc_cntl_reg.h"
+#if CONFIG_IDF_TARGET_ESP32C3
 #include "soc/syscon_reg.h"
 #elif CONFIG_IDF_TARGET_ESP32S3
-#include "soc/rtc_cntl_reg.h"
 #include "soc/syscon_reg.h"
 #endif

@ -52,6 +43,11 @@ static const char* TAG = "phy_init";

 static _lock_t s_phy_access_lock;

+static DRAM_ATTR struct {
+    int     count;  /* power on count of wifi and bt power domain */
+    _lock_t lock;
+} s_wifi_bt_pd_controller = { .count = 0 };
+
 /* Indicate PHY is calibrated or not */
 static bool s_is_phy_calibrated = false;

@ -78,7 +74,11 @@ static uint32_t* s_phy_digital_regs_mem = NULL;
 uint32_t* s_mac_bb_pd_mem = NULL;
 #endif

-#if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN_EMBED
+extern uint8_t multi_phy_init_data_bin_start[] asm("_binary_phy_multiple_init_data_bin_start");
+extern uint8_t multi_phy_init_data_bin_end[]   asm("_binary_phy_multiple_init_data_bin_end");
+#endif
 /* The following static variables are only used by Wi-Fi tasks, so they can be handled without lock */
 static phy_init_data_type_t s_phy_init_data_type = 0;

@ -277,6 +277,30 @@ void esp_phy_disable(void)
    _lock_release(&s_phy_access_lock);
 }

+void IRAM_ATTR esp_wifi_bt_power_domain_on(void)
+{
+    _lock_acquire(&s_wifi_bt_pd_controller.lock);
+    if (s_wifi_bt_pd_controller.count++ == 0) {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
+        SET_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, SYSTEM_BB_RST | SYSTEM_FE_RST);
+        CLEAR_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, SYSTEM_BB_RST | SYSTEM_FE_RST);
+#endif
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
+    }
+    _lock_release(&s_wifi_bt_pd_controller.lock);
+}
+
+void esp_wifi_bt_power_domain_off(void)
+{
+    _lock_acquire(&s_wifi_bt_pd_controller.lock);
+    if (--s_wifi_bt_pd_controller.count == 0) {
+        SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
+        SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
+    }
+    _lock_release(&s_wifi_bt_pd_controller.lock);
+}
+
 #if CONFIG_MAC_BB_PD
 void esp_mac_bb_pd_mem_init(void)
 {
@ -291,12 +315,12 @@ void esp_mac_bb_pd_mem_init(void)

 IRAM_ATTR void esp_mac_bb_power_up(void)
 {
-    if (s_mac_bb_pd_mem != NULL && (!s_mac_bb_pu)) {
+    if (s_mac_bb_pd_mem == NULL) {
+        return;
+    }
+    esp_wifi_bt_power_domain_on();
+    if (!s_mac_bb_pu) {
        esp_phy_common_clock_enable();
-        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
-        SET_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, SYSTEM_BB_RST | SYSTEM_FE_RST);
-        CLEAR_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, SYSTEM_BB_RST | SYSTEM_FE_RST);
-        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
        phy_freq_mem_backup(false, s_mac_bb_pd_mem);
        esp_phy_common_clock_disable();
        s_mac_bb_pu = true;
@ -305,24 +329,39 @@ IRAM_ATTR void esp_mac_bb_power_up(void)

 IRAM_ATTR void esp_mac_bb_power_down(void)
 {
-    if (s_mac_bb_pd_mem != NULL && s_mac_bb_pu) {
+    if (s_mac_bb_pd_mem == NULL) {
+        return;
+    }
+    if (s_mac_bb_pu) {
        esp_phy_common_clock_enable();
        phy_freq_mem_backup(true, s_mac_bb_pd_mem);
-        SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
-        SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
        esp_phy_common_clock_disable();
        s_mac_bb_pu = false;
    }
+    esp_wifi_bt_power_domain_off();
 }
 #endif

 // PHY init data handling functions
-#if CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION
+#if CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION
 #include "esp_partition.h"

 const esp_phy_init_data_t* esp_phy_get_init_data(void)
 {
-    const esp_partition_t* partition = esp_partition_find_first(
+    esp_err_t err = ESP_OK;
+    const esp_partition_t* partition = NULL;
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN_EMBED
+    size_t init_data_store_length = sizeof(phy_init_magic_pre) +
+            sizeof(esp_phy_init_data_t) + sizeof(phy_init_magic_post);
+    uint8_t* init_data_store = (uint8_t*) malloc(init_data_store_length);
+    if (init_data_store == NULL) {
+        ESP_LOGE(TAG, "failed to allocate memory for updated country code PHY init data");
+        return NULL;
+    }
+    memcpy(init_data_store, multi_phy_init_data_bin_start, init_data_store_length);
+    ESP_LOGI(TAG, "loading embedded multiple PHY init data");
+#else
+    partition = esp_partition_find_first(
            ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_PHY, NULL);
    if (partition == NULL) {
        ESP_LOGE(TAG, "PHY data partition not found");
@ -337,17 +376,18 @@ const esp_phy_init_data_t* esp_phy_get_init_data(void)
        return NULL;
    }
    // read phy data from flash
-    esp_err_t err = esp_partition_read(partition, 0, init_data_store, init_data_store_length);
+    err = esp_partition_read(partition, 0, init_data_store, init_data_store_length);
    if (err != ESP_OK) {
        ESP_LOGE(TAG, "failed to read PHY data partition (0x%x)", err);
        free(init_data_store);
        return NULL;
    }
+#endif
    // verify data
    if (memcmp(init_data_store, PHY_INIT_MAGIC, sizeof(phy_init_magic_pre)) != 0 ||
        memcmp(init_data_store + init_data_store_length - sizeof(phy_init_magic_post),
                PHY_INIT_MAGIC, sizeof(phy_init_magic_post)) != 0) {
-#ifndef CONFIG_ESP32_PHY_DEFAULT_INIT_IF_INVALID
+#ifndef CONFIG_ESP_PHY_DEFAULT_INIT_IF_INVALID
        ESP_LOGE(TAG, "failed to validate PHY data partition");
        free(init_data_store);
        return NULL;
@ -372,9 +412,9 @@ const esp_phy_init_data_t* esp_phy_get_init_data(void)
            free(init_data_store);
            return NULL;
        }
-#endif // CONFIG_ESP32_PHY_DEFAULT_INIT_IF_INVALID
+#endif // CONFIG_ESP_PHY_DEFAULT_INIT_IF_INVALID
    }
-#if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
    if ((*(init_data_store + (sizeof(phy_init_magic_pre) + PHY_SUPPORT_MULTIPLE_BIN_OFFSET)))) {
        s_multiple_phy_init_data_bin = true;
        ESP_LOGI(TAG, "Support multiple PHY init data bins");
@ -391,7 +431,7 @@ void esp_phy_release_init_data(const esp_phy_init_data_t* init_data)
    free((uint8_t*) init_data - sizeof(phy_init_magic_pre));
 }

-#else // CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION
+#else // CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION

 // phy_init_data.h will declare static 'phy_init_data' variable initialized with default init data

@ -405,7 +445,7 @@ void esp_phy_release_init_data(const esp_phy_init_data_t* init_data)
 {
    // no-op
 }
-#endif // CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION
+#endif // CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION


 // PHY calibration data handling functions
@ -561,7 +601,7 @@ static esp_err_t store_cal_data_to_nvs_handle(nvs_handle_t handle,
    return err;
 }

-#if CONFIG_ESP32_REDUCE_PHY_TX_POWER
+#if CONFIG_ESP_PHY_REDUCE_TX_POWER
 // TODO: fix the esp_phy_reduce_tx_power unused warning for esp32s2 - IDF-759
 static void __attribute((unused)) esp_phy_reduce_tx_power(esp_phy_init_data_t* init_data)
 {
@ -586,7 +626,7 @@ void esp_phy_load_cal_and_init(void)
        abort();
    }

-#if CONFIG_ESP32_REDUCE_PHY_TX_POWER
+#if CONFIG_ESP_PHY_REDUCE_TX_POWER
    const esp_phy_init_data_t* phy_init_data = esp_phy_get_init_data();
    if (phy_init_data == NULL) {
        ESP_LOGE(TAG, "failed to obtain PHY init data");
@ -611,7 +651,7 @@ void esp_phy_load_cal_and_init(void)
    }
 #endif

-#ifdef CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE
+#ifdef CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE
    esp_phy_calibration_mode_t calibration_mode = PHY_RF_CAL_PARTIAL;
    uint8_t sta_mac[6];
    if (esp_rom_get_reset_reason(0) == RESET_REASON_CORE_DEEP_SLEEP) {
@ -640,7 +680,7 @@ void esp_phy_load_cal_and_init(void)
    register_chipv7_phy(init_data, cal_data, PHY_RF_CAL_FULL);
 #endif

-#if CONFIG_ESP32_REDUCE_PHY_TX_POWER
+#if CONFIG_ESP_PHY_REDUCE_TX_POWER
    esp_phy_release_init_data(phy_init_data);
    free(init_data);
 #else
@ -650,7 +690,7 @@ void esp_phy_load_cal_and_init(void)
    free(cal_data); // PHY maintains a copy of calibration data, so we can free this
 }

-#if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
 static esp_err_t phy_crc_check_init_data(uint8_t* init_data, const uint8_t* checksum, size_t init_data_length)
 {
    uint32_t crc_data = 0;
@ -716,14 +756,17 @@ static esp_err_t phy_get_multiple_init_data(const esp_partition_t* partition,
        ESP_LOGE(TAG, "failed to allocate memory for PHY init data control info");
        return ESP_FAIL;
    }
-
-    esp_err_t err = esp_partition_read(partition, init_data_store_length, init_data_control_info, sizeof(phy_control_info_data_t));
+    esp_err_t err = ESP_OK;
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN_EMBED
+    memcpy(init_data_control_info, multi_phy_init_data_bin_start + init_data_store_length, sizeof(phy_control_info_data_t));
+#else
+    err = esp_partition_read(partition, init_data_store_length, init_data_control_info, sizeof(phy_control_info_data_t));
    if (err != ESP_OK) {
        free(init_data_control_info);
        ESP_LOGE(TAG, "failed to read PHY control info data partition (0x%x)", err);
        return ESP_FAIL;
    }
-
+#endif
    if ((init_data_control_info->check_algorithm) == PHY_CRC_ALGORITHM) {
        err =  phy_crc_check_init_data(init_data_control_info->multiple_bin_checksum, init_data_control_info->control_info_checksum,
                sizeof(phy_control_info_data_t) - sizeof(init_data_control_info->control_info_checksum));
@ -745,6 +788,9 @@ static esp_err_t phy_get_multiple_init_data(const esp_partition_t* partition,
        return ESP_FAIL;
    }

+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN_EMBED
+    memcpy(init_data_multiple, multi_phy_init_data_bin_start + init_data_store_length + sizeof(phy_control_info_data_t), sizeof(esp_phy_init_data_t) * init_data_control_info->number);
+#else
    err = esp_partition_read(partition, init_data_store_length + sizeof(phy_control_info_data_t),
            init_data_multiple, sizeof(esp_phy_init_data_t) * init_data_control_info->number);
    if (err != ESP_OK) {
@ -753,7 +799,7 @@ static esp_err_t phy_get_multiple_init_data(const esp_partition_t* partition,
        ESP_LOGE(TAG, "failed to read PHY init data multiple bin partition (0x%x)", err);
        return ESP_FAIL;
    }
-
+#endif
    if ((init_data_control_info->check_algorithm) == PHY_CRC_ALGORITHM) {
        err = phy_crc_check_init_data(init_data_multiple, init_data_control_info->multiple_bin_checksum,
                sizeof(esp_phy_init_data_t) * init_data_control_info->number);
@ -785,6 +831,19 @@ static esp_err_t phy_get_multiple_init_data(const esp_partition_t* partition,

 esp_err_t esp_phy_update_init_data(phy_init_data_type_t init_data_type)
 {
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN_EMBED
+    esp_err_t err = ESP_OK;
+    const esp_partition_t* partition = NULL;
+    size_t init_data_store_length = sizeof(phy_init_magic_pre) +
+        sizeof(esp_phy_init_data_t) + sizeof(phy_init_magic_post);
+    uint8_t* init_data_store = (uint8_t*) malloc(init_data_store_length);
+    if (init_data_store == NULL) {
+        ESP_LOGE(TAG, "failed to allocate memory for updated country code PHY init data");
+        return ESP_ERR_NO_MEM;
+    }
+    memcpy(init_data_store, multi_phy_init_data_bin_start, init_data_store_length);
+    ESP_LOGI(TAG, "load embedded multi phy init data");
+#else
    const esp_partition_t* partition = esp_partition_find_first(
          ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_DATA_PHY, NULL);
    if (partition == NULL) {
@ -805,6 +864,7 @@ esp_err_t esp_phy_update_init_data(phy_init_data_type_t init_data_type)
        ESP_LOGE(TAG, "failed to read updated country code PHY data partition (0x%x)", err);
        return ESP_FAIL;
    }
+#endif
    if (memcmp(init_data_store, PHY_INIT_MAGIC, sizeof(phy_init_magic_pre)) != 0 ||
            memcmp(init_data_store + init_data_store_length - sizeof(phy_init_magic_post),
                PHY_INIT_MAGIC, sizeof(phy_init_magic_post)) != 0) {
@ -818,7 +878,7 @@ esp_err_t esp_phy_update_init_data(phy_init_data_type_t init_data_type)
        err = phy_get_multiple_init_data(partition, init_data_store, init_data_store_length, init_data_type);
        if (err != ESP_OK) {
            free(init_data_store);
-#if CONFIG_ESP32_PHY_INIT_DATA_ERROR
+#if CONFIG_ESP_PHY_INIT_DATA_ERROR
            abort();
 #else
            return ESP_FAIL;
@ -848,7 +908,7 @@ esp_err_t esp_phy_update_init_data(phy_init_data_type_t init_data_type)

 esp_err_t esp_phy_update_country_info(const char *country)
 {
-#if CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA_BIN
+#if CONFIG_ESP_PHY_MULTIPLE_INIT_DATA_BIN
    uint8_t phy_init_data_type_map = 0;

    if (!s_multiple_phy_init_data_bin) {
@ -875,3 +935,6 @@ esp_err_t esp_phy_update_country_info(const char *country)
 #endif
    return ESP_OK;
 }
+
+void esp_wifi_power_domain_on(void) __attribute__((alias("esp_wifi_bt_power_domain_on")));
+void esp_wifi_power_domain_off(void) __attribute__((alias("esp_wifi_bt_power_domain_off")));
--- a/components/esp_phy/test/test_phy_rtc.c
+++ b/components/esp_phy/test/test_phy_rtc.c
@ -12,6 +12,7 @@
 #include <freertos/task.h>
 #include <freertos/semphr.h>
 #include "soc/soc_caps.h"
+#include "esp_private/wifi.h"

 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3)

@ -52,6 +53,9 @@ static void test_phy_rtc_init(void)

 static IRAM_ATTR void test_phy_rtc_cache_task(void *arg)
 {
+    //power up wifi and bt mac bb power domain
+    esp_wifi_power_domain_on();
+
    test_phy_rtc_init();

 #if CONFIG_IDF_TARGET_ESP32
@ -102,6 +106,9 @@ static IRAM_ATTR void test_phy_rtc_cache_task(void *arg)

 #endif //SOC_BT_SUPPORTED

+    //power down wifi and bt mac bb power domain
+    esp_wifi_power_domain_off();
+
    TEST_ASSERT( xSemaphoreGive(semphr_done) );

    vTaskDelete(NULL);
--- a/components/esp_rom/esp32c3/ld/esp32c3.rom.ld
+++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.ld
@ -1567,7 +1567,6 @@ ppEnqueueRxq = 0x400016c8;
 ppEnqueueTxDone = 0x400016cc;
 ppGetTxQFirstAvail_Locked = 0x400016d0;
 ppGetTxframe = 0x400016d4;
-ppProcTxSecFrame = 0x400016dc;
 ppProcessRxPktHdr = 0x400016e0;
 ppProcessTxQ = 0x400016e4;
 ppRecordBarRRC = 0x400016e8;
--- a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld
+++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld
@ -1873,7 +1873,6 @@ ppEnqueueTxDone = 0x400055a4;
 ppGetTxQFirstAvail_Locked = 0x400055b0;
 ppGetTxframe = 0x400055bc;
 ppMapTxQueue = 0x400055c8;
-ppProcTxSecFrame = 0x400055d4;
 ppProcessRxPktHdr = 0x400055e0;
 ppProcessTxQ = 0x400055ec;
 ppRecordBarRRC = 0x400055f8;
--- a/components/esp_rom/include/esp32s3/rom/rtc.h
+++ b/components/esp_rom/include/esp32s3/rom/rtc.h
@ -1,16 +1,8 @@
-// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #pragma once

@ -62,6 +54,7 @@ extern "C" {
 #define RTC_BOOT_TIME_LOW_REG   RTC_CNTL_STORE2_REG
 #define RTC_BOOT_TIME_HIGH_REG  RTC_CNTL_STORE3_REG
 #define RTC_XTAL_FREQ_REG       RTC_CNTL_STORE4_REG
+#define RTC_ENTRY_LENGTH_REG    RTC_CNTL_STORE5_REG
 #define RTC_ENTRY_ADDR_REG      RTC_CNTL_STORE6_REG
 #define RTC_RESET_CAUSE_REG     RTC_CNTL_STORE6_REG
 #define RTC_MEMORY_CRC_REG      RTC_CNTL_STORE7_REG
@ -173,16 +166,31 @@ RESET_REASON rtc_get_reset_reason(int cpu_no);
  */
 WAKEUP_REASON rtc_get_wakeup_cause(void);

+typedef void (* esp_rom_wake_func_t)(void);
+
 /**
-  * @brief Get CRC for Fast RTC Memory.
+  * @brief Read stored RTC wake function address
  *
-  * @param  uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
+  * Returns pointer to wake address if a value is set in RTC registers, and stored length & CRC all valid.
  *
-  * @param  uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
+  * @param  None
  *
-  * @return uint32_t : CRC32 result
+  * @return esp_rom_wake_func_t : Returns pointer to wake address if a value is set in RTC registers
  */
-uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
+esp_rom_wake_func_t esp_rom_get_rtc_wake_addr(void);
+
+/**
+  * @brief Store new RTC wake function address
+  *
+  * Set a new RTC wake address function. If a non-NULL function pointer is set then the function
+  * memory is calculated and stored also.
+  *
+  * @param entry_addr Address of function. If NULL, length is ignored and all registers are cleared to 0.
+  * @param length of function in RTC fast memory. cannot be larger than RTC Fast memory size.
+  *
+  * @return None
+  */
+void esp_rom_set_rtc_wake_addr(esp_rom_wake_func_t entry_addr, size_t length);

 /**
  * @brief Suppress ROM log by setting specific RTC control register.
@ -202,26 +210,6 @@ static inline void rtc_suppress_rom_log(void)
    REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
 }

-/**
-  * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
-  *
-  * @param  None
-  *
-  * @return None
-  */
-void set_rtc_memory_crc(void);
-
-/**
-  * @brief Fetch entry from RTC memory and RTC STORE reg
-  *
-  * @param uint32_t * entry_addr : the address to save entry
-  *
-  * @param RESET_REASON reset_reason : reset reason this time
-  *
-  * @return None
-  */
-void rtc_boot_control(uint32_t *entry_addr, RESET_REASON reset_reason);
-
 /**
  * @brief Software Reset digital core.
  *
--- a/components/esp_system/Kconfig
+++ b/components/esp_system/Kconfig
@ -87,11 +87,7 @@ menu "ESP System Settings"

    config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
        bool "Enable RTC fast memory for dynamic allocations"
-        default y if IDF_TARGET_ESP32
-        default y if IDF_TARGET_ESP32S2
-        default y if IDF_TARGET_ESP32C3
-        default n if IDF_TARGET_ESP32S3  # TODO
-        default y if IDF_TARGET_ESP32H2
+        default y
        depends on ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK
        help
            This config option allows to add RTC fast memory region to system heap with capability
--- a/components/esp_system/ld/esp32s3/memory.ld.in
+++ b/components/esp_system/ld/esp32s3/memory.ld.in
@ -103,7 +103,7 @@ MEMORY
  /**
   * RTC fast memory (same block as above), viewed from data bus
   */
-  rtc_data_seg(RW) :                 org = 0x600fe000, len = 0x2000
+  rtc_data_seg(RW) :                 org = 0x600fe000, len = 0x2000 - ESP_BOOTLOADER_RESERVE_RTC

  /**
   * RTC slow memory (data accessible). Persists over deep sleep.
--- a/components/esp_system/ld/esp32s3/sections.ld.in
+++ b/components/esp_system/ld/esp32s3/sections.ld.in
@ -18,6 +18,8 @@ SECTIONS
  .rtc.text :
  {
    . = ALIGN(4);
+    _rtc_text_start = ABSOLUTE(.);
+    *(.rtc.entry.text)

    mapping[rtc_text]

--- a/components/esp_system/port/arch/xtensa/panic_arch.c
+++ b/components/esp_system/port/arch/xtensa/panic_arch.c
@ -422,11 +422,7 @@ void panic_soc_fill_info(void *f, panic_info_t *info)
        "Coprocessor exception",
        "Interrupt wdt timeout on CPU0",
        "Interrupt wdt timeout on CPU1",
-#if CONFIG_IDF_TARGET_ESP32
        "Cache disabled but cached memory region accessed",
-#elif CONFIG_IDF_TARGET_ESP32S2
-        "Cache error",
-#endif
    };

    info->reason = pseudo_reason[0];
@ -441,7 +437,7 @@ void panic_soc_fill_info(void *f, panic_info_t *info)
        info->exception = PANIC_EXCEPTION_DEBUG;
    }

-#if CONFIG_IDF_TARGET_ESP32S2
+#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
    if (frame->exccause == PANIC_RSN_CACHEERR) {
 #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE
        if ( esp_memprot_is_intr_ena_any() ) {
--- a/components/esp_system/port/cpu_start.c
+++ b/components/esp_system/port/cpu_start.c
@ -137,6 +137,15 @@ static volatile bool s_resume_cores;
 // If CONFIG_SPIRAM_IGNORE_NOTFOUND is set and external RAM is not found or errors out on testing, this is set to false.
 bool g_spiram_ok = true;

+static void core_intr_matrix_clear(void)
+{
+    uint32_t core_id = cpu_hal_get_core_id();
+
+    for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
+        intr_matrix_set(core_id, i, ETS_INVALID_INUM);
+    }
+}
+
 #if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
 void startup_resume_other_cores(void)
 {
@ -170,6 +179,9 @@ void IRAM_ATTR call_start_cpu1(void)
    s_cpu_up[1] = true;
    ESP_EARLY_LOGI(TAG, "App cpu up.");

+    // Clear interrupt matrix for APP CPU core
+    core_intr_matrix_clear();
+
    //Take care putting stuff here: if asked, FreeRTOS will happily tell you the scheduler
    //has started, but it isn't active *on this CPU* yet.
    esp_cache_err_int_init();
@ -244,16 +256,6 @@ static void start_other_core(void)
 }
 #endif // !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE

-static void intr_matrix_clear(void)
-{
-    for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
-        intr_matrix_set(0, i, ETS_INVALID_INUM);
-#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
-        intr_matrix_set(1, i, ETS_INVALID_INUM);
-#endif
-    }
-}
-
 /*
 * We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
 * and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
@ -525,7 +527,8 @@ void IRAM_ATTR call_start_cpu0(void)
    // and default RTC-backed system time provider.
    g_startup_time = esp_rtc_get_time_us();

-    intr_matrix_clear();
+    // Clear interrupt matrix for PRO CPU core
+    core_intr_matrix_clear();

 #ifndef CONFIG_IDF_ENV_FPGA // TODO: on FPGA it should be possible to configure this, not currently working with APB_CLK_FREQ changed
 #ifdef CONFIG_ESP_CONSOLE_UART
--- a/components/esp_system/port/soc/esp32/highint_hdl.S
+++ b/components/esp_system/port/soc/esp32/highint_hdl.S
@ -173,7 +173,13 @@ xt_highintx:
    rsr     a0, INTERRUPT
    extui   a0, a0, ETS_IPC_ISR_INUM, 1
    beqz    a0, 1f
-    j       esp_ipc_isr_handler
+    /* Jump to `esp_ipc_isr_handler` which is non-returning. We need to use `jx`
+     * because on Xtensa, `j` instruction can only refer to a label which
+     * is in the range [-131068;+131075]. If the destination is out of scope,
+     * linking will fail. So, to make sure we will always be able to jump to
+     * that subroutine, retrieve its address and store it in a register. */
+    movi    a0, esp_ipc_isr_handler
+    jx      a0
 1:
 #endif /* not CONFIG_FREERTOS_UNICORE */

--- a/components/esp_system/port/soc/esp32s3/cache_err_int.c
+++ b/components/esp_system/port/soc/esp32s3/cache_err_int.c
@ -1,16 +1,8 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 /**
 * @file cache_err_int.c
@ -65,11 +57,69 @@ void esp_cache_err_int_init(void)
                      EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA |
                      EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA);

+    if (core_id == PRO_CPU_NUM) {
+        intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
+        /* On the hardware side, stat by clearing all the bits reponsible for
+         * enabling cache access error interrupts.  */
+        SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG,
+                EXTMEM_CORE0_DBUS_REJECT_INT_CLR |
+                EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR |
+                EXTMEM_CORE0_IBUS_REJECT_INT_CLR |
+                EXTMEM_CORE0_IBUS_WR_IC_INT_CLR |
+                EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR);
+
+        /* Enable cache access error interrupts */
+        SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG,
+                EXTMEM_CORE0_DBUS_REJECT_INT_ENA |
+                EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA |
+                EXTMEM_CORE0_IBUS_REJECT_INT_ENA |
+                EXTMEM_CORE0_IBUS_WR_IC_INT_ENA |
+                EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA);
+    } else {
+        intr_matrix_set(core_id, ETS_CACHE_CORE1_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
+
+        /* On the hardware side, stat by clearing all the bits reponsible for
+         * enabling cache access error interrupts.  */
+        SET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG,
+                EXTMEM_CORE1_DBUS_REJECT_INT_CLR |
+                EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR |
+                EXTMEM_CORE1_IBUS_REJECT_INT_CLR |
+                EXTMEM_CORE1_IBUS_WR_IC_INT_CLR |
+                EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR);
+
+        /* Enable cache access error interrupts */
+        SET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG,
+                EXTMEM_CORE1_DBUS_REJECT_INT_ENA |
+                EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA |
+                EXTMEM_CORE1_IBUS_REJECT_INT_ENA |
+                EXTMEM_CORE1_IBUS_WR_IC_INT_ENA |
+                EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA);
+    }
+
    ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
 }

 int IRAM_ATTR esp_cache_err_get_cpuid(void)
 {
-    // FIXME
+    const uint32_t pro_mask = EXTMEM_CORE0_DBUS_REJECT_ST |
+                EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST |
+                EXTMEM_CORE0_IBUS_REJECT_ST |
+                EXTMEM_CORE0_IBUS_WR_ICACHE_ST |
+                EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST;
+
+    if (GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, pro_mask)) {
+        return PRO_CPU_NUM;
+    }
+
+    const uint32_t app_mask = EXTMEM_CORE1_DBUS_REJECT_ST |
+                EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST |
+                EXTMEM_CORE1_IBUS_REJECT_ST |
+                EXTMEM_CORE1_IBUS_WR_ICACHE_ST |
+                EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST;
+
+    if (GET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_ST_REG, app_mask)) {
+        return APP_CPU_NUM;
+    }
+
    return -1;
 }
--- a/components/esp_system/port/soc/esp32s3/highint_hdl.S
+++ b/components/esp_system/port/soc/esp32s3/highint_hdl.S
@ -49,7 +49,7 @@ xt_highint4:
    /* See if we're here for the IPC_ISR interrupt */
    rsr     a0, INTERRUPT
    extui   a0, a0, ETS_IPC_ISR_INUM, 1
-    bnez    a0, esp_ipc_isr_handler
+    bnez    a0, jump_to_esp_ipc_isr_handler
 #endif // not CONFIG_FREERTOS_UNICORE

    /* Allocate exception frame and save minimal context. */
@ -130,6 +130,14 @@ xt_highint4:
    rsr     a0, EXCSAVE_4                   /* restore a0 */
    rfi     4

+#ifdef CONFIG_ESP_IPC_ISR_ENABLE
+jump_to_esp_ipc_isr_handler:
+    /* Address of `esp_ipc_isr_handler_address` will always be in `movi` range
+     * as it is defined right above. */
+    movi    a0, esp_ipc_isr_handler
+    jx      a0
+#endif
+
 /* The linker has no reason to link in this file; all symbols it exports are already defined
   (weakly!) in the default int handler. Define a symbol here so we can use it to have the
   linker inspect this anyway. */
--- a/components/esp_system/startup.c
+++ b/components/esp_system/startup.c
@ -434,7 +434,7 @@ IRAM_ATTR ESP_SYSTEM_INIT_FN(init_components0, BIT(0))
 {
    esp_timer_init();

-#if CONFIG_ESP32C3_LIGHTSLEEP_GPIO_RESET_WORKAROUND && !CONFIG_PM_SLP_DISABLE_GPIO
+#if CONFIG_ESP_SLEEP_GPIO_RESET_WORKAROUND && !CONFIG_PM_SLP_DISABLE_GPIO
    // Configure to isolate (disable the Input/Output/Pullup/Pulldown
    // function of the pin) all GPIO pins in sleep state
    esp_sleep_config_gpio_isolate();
--- a/components/esp_system/task_wdt.c
+++ b/components/esp_system/task_wdt.c
@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 #include <stdint.h>
 #include <stdio.h>
@ -226,9 +218,9 @@ esp_err_t esp_task_wdt_init(uint32_t timeout, bool panic)
        wdt_hal_init(&twdt_context, TWDT_INSTANCE, TWDT_PRESCALER, true);
        wdt_hal_write_protect_disable(&twdt_context);
        //Configure 1st stage timeout and behavior
-        wdt_hal_config_stage(&twdt_context, WDT_STAGE0, twdt_config->timeout * 1000000 / TWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT);
+        wdt_hal_config_stage(&twdt_context, WDT_STAGE0, twdt_config->timeout * (1000000 / TWDT_TICKS_PER_US), WDT_STAGE_ACTION_INT);
        //Configure 2nd stage timeout and behavior
-        wdt_hal_config_stage(&twdt_context, WDT_STAGE1, 2*twdt_config->timeout * 1000000 / TWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM);
+        wdt_hal_config_stage(&twdt_context, WDT_STAGE1, twdt_config->timeout * (2 * 1000000 / TWDT_TICKS_PER_US), WDT_STAGE_ACTION_RESET_SYSTEM);
        //Enable the WDT
        wdt_hal_enable(&twdt_context);
        wdt_hal_write_protect_enable(&twdt_context);
@ -240,8 +232,8 @@ esp_err_t esp_task_wdt_init(uint32_t timeout, bool panic)
        //Reconfigure hardware timer
        wdt_hal_write_protect_disable(&twdt_context);
        wdt_hal_disable(&twdt_context);
-        wdt_hal_config_stage(&twdt_context, WDT_STAGE0, twdt_config->timeout*1000*1000/TWDT_TICKS_PER_US, WDT_STAGE_ACTION_INT);
-        wdt_hal_config_stage(&twdt_context, WDT_STAGE1, 2*twdt_config->timeout*1000*1000/TWDT_TICKS_PER_US, WDT_STAGE_ACTION_RESET_SYSTEM);
+        wdt_hal_config_stage(&twdt_context, WDT_STAGE0, twdt_config->timeout * (1000 * 1000 / TWDT_TICKS_PER_US), WDT_STAGE_ACTION_INT);
+        wdt_hal_config_stage(&twdt_context, WDT_STAGE1, twdt_config->timeout * (2 * 1000 * 1000 / TWDT_TICKS_PER_US), WDT_STAGE_ACTION_RESET_SYSTEM);
        wdt_hal_enable(&twdt_context);
        wdt_hal_write_protect_enable(&twdt_context);
    }
--- a/components/esp_system/test/test_sleep.c
+++ b/components/esp_system/test/test_sleep.c
@ -1,3 +1,9 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 #include "unity.h"
 #include <sys/time.h>
 #include <sys/param.h>
@ -20,8 +26,6 @@
 #include "esp_rom_sys.h"
 #include "esp_timer.h"

-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
-
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/clk.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
@ -284,8 +288,10 @@ static void check_wake_stub(void)
 {
    TEST_ASSERT_EQUAL(ESP_RST_DEEPSLEEP, esp_reset_reason());
    TEST_ASSERT_EQUAL_HEX32((uint32_t) &wake_stub, s_wake_stub_var);
+#if !CONFIG_IDF_TARGET_ESP32S3
    /* ROM code clears wake stub entry address */
    TEST_ASSERT_NULL(esp_get_deep_sleep_wake_stub());
+#endif
 }

 TEST_CASE_MULTIPLE_STAGES("can set sleep wake stub", "[deepsleep][reset=DEEPSLEEP_RESET]",
@ -318,7 +324,12 @@ static void prepare_wake_stub_from_rtc(void)
       a memory capability (as it's an implementation detail). So to test this we need to allocate
       the stack statically.
    */
+#if CONFIG_IDF_TARGET_ESP32S3
+    uint8_t *sleep_stack = (uint8_t *)heap_caps_malloc(1024, MALLOC_CAP_RTCRAM);
+    TEST_ASSERT((uint32_t)sleep_stack >= SOC_RTC_DRAM_LOW && (uint32_t)sleep_stack < SOC_RTC_DRAM_HIGH);
+#else
    static RTC_FAST_ATTR uint8_t sleep_stack[1024];
+#endif
    static RTC_FAST_ATTR StaticTask_t sleep_task;

    /* normally BSS like sleep_stack will be cleared on reset, but RTC memory is not cleared on
@ -423,7 +434,7 @@ __attribute__((unused)) static uint32_t get_cause(void)
    return wakeup_cause;
 }

-#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
+#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3)
 // Fails on S2 IDF-2903

 // This test case verifies deactivation of trigger for wake up sources
@ -498,7 +509,7 @@ TEST_CASE("disable source trigger behavior", "[deepsleep]")
    // Disable ext0 wakeup source, as this might interfere with other tests
    ESP_ERROR_CHECK(esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_EXT0));
 }
-#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2)
+#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32S3)

 #endif //SOC_RTCIO_INPUT_OUTPUT_SUPPORTED

@ -537,8 +548,6 @@ static void check_time_deepsleep(void)

 TEST_CASE_MULTIPLE_STAGES("check a time after wakeup from deep sleep", "[deepsleep][reset=DEEPSLEEP_RESET]", trigger_deepsleep, check_time_deepsleep);

-#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3)
-
 #if SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
 static void gpio_deepsleep_wakeup_config(void)
 {
--- a/components/esp_wifi/Kconfig
+++ b/components/esp_wifi/Kconfig
@ -312,4 +312,17 @@ menu "Wi-Fi"
            This function depends on BT-off
            because currently we don't support external coex and internal coex simultaneously.

+    config ESP_WIFI_GCMP_SUPPORT
+        bool "WiFi GCMP Support(GCMP128 and GCMP256)"
+        default n
+        depends on (IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3)
+        help
+            Select this option to enable GCMP support. GCMP support is compulsory for WiFi Suite-B support.
+
+    config ESP_WIFI_GMAC_SUPPORT
+        bool "WiFi GMAC Support(GMAC128 and GMAC256)"
+        default n
+        help
+            Select this option to enable GMAC support. GMAC support is compulsory for WiFi 192 bit certification.
+
 endmenu  # Wi-Fi
--- a/components/esp_wifi/include/esp_private/wifi.h
+++ b/components/esp_wifi/include/esp_private/wifi.h
@ -1,16 +1,8 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 /*
 * All the APIs declared here are internal only APIs, it can only be used by
@ -505,6 +497,16 @@ bool esp_wifi_internal_is_tsf_active(void);
 void esp_wifi_internal_update_light_sleep_wake_ahead_time(uint32_t);
 #endif

+/**
+ * @brief Wifi power domain power on
+ */
+void esp_wifi_power_domain_on(void);
+
+/**
+ * @brief Wifi power domain power off
+ */
+void esp_wifi_power_domain_off(void);
+
 #if CONFIG_MAC_BB_PD
 /**
  * @brief     Enable or disable powering down MAC and baseband when Wi-Fi is sleeping.
--- a/components/esp_wifi/include/esp_wifi_crypto_types.h
+++ b/components/esp_wifi/include/esp_wifi_crypto_types.h
@ -1,16 +1,8 @@
-// Hardware crypto support Copyright 2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */


 #ifndef __ESP_WIFI_CRYPTO_TYPES_H__
@ -358,6 +350,21 @@ typedef uint8_t * (*esp_ccmp_decrypt_t)(const uint8_t *tk, const uint8_t *ieee80
 typedef uint8_t * (*esp_ccmp_encrypt_t)(const uint8_t *tk, uint8_t *frame, size_t len, size_t hdrlen,
                                        uint8_t *pn, int keyid, size_t *encrypted_len);

+/**
+ * @brief One-Key GMAC hash with AES for MIC computation
+ *
+ * @key: key for the hash operation
+ * @keylen: key length
+ * @iv: initialization vector
+ * @iv_len: initialization vector length
+ * @aad: aad
+ * @aad_len: aad length
+ * @mic: Buffer for MIC (128 bits, i.e., 16 bytes)
+ * Returns: 0 on success, -1 on failure
+ */
+typedef int (*esp_aes_gmac_t)(const uint8_t *key, size_t keylen, const uint8_t *iv, size_t iv_len,
+                              const uint8_t *aad, size_t aad_len, uint8_t *mic);
+
 /**
  * @brief The crypto callback function structure used when do station security connect.
  *        The structure can be set as software crypto or the crypto optimized by ESP32
@ -390,6 +397,7 @@ typedef struct {
    esp_omac1_aes_128_t omac1_aes_128;
    esp_ccmp_decrypt_t ccmp_decrypt;
    esp_ccmp_encrypt_t ccmp_encrypt;
+    esp_aes_gmac_t aes_gmac;
 }wpa_crypto_funcs_t;

 /**
--- a/components/esp_wifi/include/esp_wifi_types.h
+++ b/components/esp_wifi/include/esp_wifi_types.h
@ -142,6 +142,10 @@ typedef enum {
    WIFI_CIPHER_TYPE_TKIP_CCMP,  /**< the cipher type is TKIP and CCMP */
    WIFI_CIPHER_TYPE_AES_CMAC128,/**< the cipher type is AES-CMAC-128 */
    WIFI_CIPHER_TYPE_SMS4,       /**< the cipher type is SMS4 */
+    WIFI_CIPHER_TYPE_GCMP,       /**< the cipher type is GCMP */
+    WIFI_CIPHER_TYPE_GCMP256,    /**< the cipher type is GCMP-256 */
+    WIFI_CIPHER_TYPE_AES_GMAC128,/**< the cipher type is AES-GMAC-128 */
+    WIFI_CIPHER_TYPE_AES_GMAC256,/**< the cipher type is AES-GMAC-256 */
    WIFI_CIPHER_TYPE_UNKNOWN,    /**< the cipher type is unknown */
 } wifi_cipher_type_t;

--- a/components/esp_wifi/lib
+++ b/components/esp_wifi/lib
@ -1 +1 @@
-Subproject commit 049fbb7f22962fc4e2316e732ad08fc95b14149f
+Subproject commit 681c8bfeb739c2fcd579e404b1df8b19acc07497
--- a/components/esp_wifi/src/wifi_init.c
+++ b/components/esp_wifi/src/wifi_init.c
@ -125,6 +125,7 @@ esp_err_t esp_wifi_deinit(void)
    esp_unregister_mac_bb_pd_callback(pm_mac_sleep);
    esp_unregister_mac_bb_pu_callback(pm_mac_wakeup);
 #endif
+    esp_wifi_power_domain_off();
    return err;
 }

@ -169,6 +170,7 @@ static void esp_wifi_config_info(void)

 esp_err_t esp_wifi_init(const wifi_init_config_t *config)
 {
+    esp_wifi_power_domain_on();
 #ifdef CONFIG_PM_ENABLE
    if (s_wifi_modem_sleep_lock == NULL) {
        esp_err_t err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "wifi",
--- a/components/espcoredump/test/esp32s3/core.elf
+++ b/components/espcoredump/test/esp32s3/core.elf
--- a/components/espcoredump/test/test_espcoredump.sh
+++ b/components/espcoredump/test/test_espcoredump.sh
@ -11,6 +11,11 @@ else
  elf_dir=$1
 fi

+if ! command -v coverage &> /dev/null; then
+  echo "coverage could not be found, please install it ('pip install coverage')"
+  exit 1
+fi
+
 SUPPORTED_TARGETS=("esp32" "esp32s2" "esp32c3" "esp32s3" )
 res=0
 coverage erase
--- a/components/espcoredump/test_apps/README.md
+++ b/components/espcoredump/test_apps/README.md
@ -1,6 +1,30 @@
-| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 |
-| ----------------- | ----- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-S2 | ESP32-C3 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- |

 # ESP Core Dump Tests

 This test app is used to provide built binaries for the test cases under test folders
+
+## Update coredump.64 test data
+
+To update `test/<target>/coredump.64` build a `test_apps` for a target, flash and get a base64 text from `idf.py monitor`
+
+## Update expected_output test data
+
+To update `test/<target>/expected_output` run
+
+```
+TARGET=esp32
+espcoredump.py --chip $TARGET info_corefile -c ../test/$TARGET/coredump.b64 -t b64 -m ./build/test_core_dump.elf > ../test/$TARGET/expected_output
+```
+
+A `test_apps` app should be built for that target.
+
+Do the same for other targets: esp32s2, esp32c3, etc.
+
+## Update ELF test binaries
+
+The ELF test binaries are placed in a different git repository, _idf-coredump-elf_, to avoid putting big binaries in IDF repo.
+It is used in _test_espcoredump_ CI job.
+
+See _idf-coredump-elf/README.md_ to use `build_espcoredump.sh` and generate test ELF binaries
--- a/components/hal/esp32/include/hal/gpio_ll.h
+++ b/components/hal/esp32/include/hal/gpio_ll.h
@ -1,16 +1,8 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 /*******************************************************************************
 * NOTICE
@ -511,7 +503,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_
  */
 static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength)
 {
-    *strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
+    *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
 }

 /**
--- a/components/hal/esp32c3/include/hal/gpio_ll.h
+++ b/components/hal/esp32c3/include/hal/gpio_ll.h
@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 /*******************************************************************************
 * NOTICE
@ -325,7 +317,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_
  */
 static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength)
 {
-    *strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
+    *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
 }

 /**
--- a/components/hal/esp32h2/include/hal/gpio_ll.h
+++ b/components/hal/esp32h2/include/hal/gpio_ll.h
@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 /*******************************************************************************
 * NOTICE
@ -325,7 +317,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_
  */
 static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength)
 {
-    *strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
+    *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
 }

 /**
--- a/components/hal/esp32s2/include/hal/gpio_ll.h
+++ b/components/hal/esp32s2/include/hal/gpio_ll.h
@ -1,16 +1,8 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 /*******************************************************************************
 * NOTICE
@ -334,7 +326,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_
  */
 static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength)
 {
-    *strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
+    *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
 }

 /**
--- a/components/hal/esp32s3/include/hal/gpio_ll.h
+++ b/components/hal/esp32s3/include/hal/gpio_ll.h
@ -1,16 +1,8 @@
-// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

 /*******************************************************************************
 * NOTICE
@ -335,7 +327,7 @@ static inline void gpio_ll_set_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_
  */
 static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, gpio_num_t gpio_num, gpio_drive_cap_t *strength)
 {
-    *strength = GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
+    *strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(GPIO_PIN_MUX_REG[gpio_num], FUN_DRV_V, FUN_DRV_S);
 }

 /**
--- a/components/heap/include/esp_heap_caps.h
+++ b/components/heap/include/esp_heap_caps.h
@ -1,16 +1,9 @@
-// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
+/*
+ * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */

-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
 #pragma once

 #include <stdint.h>
@ -41,6 +34,7 @@ extern "C" {
 #define MALLOC_CAP_DEFAULT          (1<<12) ///< Memory can be returned in a non-capability-specific memory allocation (e.g. malloc(), calloc()) call
 #define MALLOC_CAP_IRAM_8BIT        (1<<13) ///< Memory must be in IRAM and allow unaligned access
 #define MALLOC_CAP_RETENTION        (1<<14)
+#define MALLOC_CAP_RTCRAM           (1<<15) ///< Memory must be in RTC fast memory

 #define MALLOC_CAP_INVALID          (1<<31) ///< Memory can't be used / list end marker

--- a/components/heap/port/esp32s3/memory_layout.c
+++ b/components/heap/port/esp32s3/memory_layout.c
@ -1,16 +1,9 @@
-// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 #ifndef BOOTLOADER_BUILD

 #include <stdint.h>
@ -46,6 +39,8 @@ const soc_memory_type_desc_t soc_memory_types[] = {
    { "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}, false, false},
    // Type 5: DRAM which is not DMA accesible
    { "NON_DMA_DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT, 0 }, false, false},
+    // Type 6: RTC Fast RAM
+    { "RTCRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT, MALLOC_CAP_RTCRAM }, false, false},
 };

 const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t);
@ -78,13 +73,13 @@ const soc_memory_region_t soc_memory_regions[] = {
    { 0x3C000000, 0x4000,  5, 0}
 #endif
 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
-    { 0x50000000, 0x2000,  4, 0}, //Fast RTC memory
+    { 0x600fe000, 0x2000,  6, 0}, //Fast RTC memory
 #endif
 };

 const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);

-extern int _data_start, _heap_start, _iram_start, _iram_end; // defined in sections.ld.in
+extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_fast_end, _rtc_noinit_end; // defined in sections.ld.in

 /**
 * Reserved memory regions.
@ -115,4 +110,13 @@ SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH, extram_dat
 SOC_RESERVE_MEMORY_REGION(0x3fffc000 - CONFIG_ESP32S3_TRACEMEM_RESERVE_DRAM, 0x3fffc000, trace_mem);
 #endif

+// RTC Fast RAM region
+#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
+#ifdef CONFIG_ESP32S3_RTCDATA_IN_FAST_MEM
+SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_noinit_end, rtcram_data);
+#else
+SOC_RESERVE_MEMORY_REGION(SOC_RTC_DRAM_LOW, (intptr_t)&_rtc_force_fast_end, rtcram_data);
+#endif
+#endif
+
 #endif // BOOTLOADER_BUILD
--- a/components/ieee802154/lib
+++ b/components/ieee802154/lib
@ -1 +1 @@
-Subproject commit 1d3cb8b1adfd6e338f6edd448a555bb25dfb692f
+Subproject commit 387c762a711ca70a1b86d66716736f162a52ff4a
--- a/components/lwip/lwip
+++ b/components/lwip/lwip
@ -1 +1 @@
-Subproject commit 2195f7416fb3136831babf3e96c027a73075bd4f
+Subproject commit 2749568fe15df2003f6c3f37f0dfd44f8f01fcd6
--- a/components/mbedtls/esp_crt_bundle/cacrt_all.pem
+++ b/components/mbedtls/esp_crt_bundle/cacrt_all.pem
--- a/components/mdns/mdns.c
+++ b/components/mdns/mdns.c
@ -310,6 +310,7 @@ static const uint8_t * _mdns_read_fqdn(const uint8_t * packet, const uint8_t * s
            buf[len] = '\0';
            if (name->parts == 1 && buf[0] != '_'
                    && (strcasecmp(buf, MDNS_DEFAULT_DOMAIN) != 0)
+                    && (strcasecmp(buf, "arpa") != 0)
                    && (strcasecmp(buf, "ip6") != 0)
                    && (strcasecmp(buf, "in-addr") != 0)) {
                strlcat(name->host, ".", sizeof(name->host));
@ -2793,7 +2794,8 @@ static const uint8_t * _mdns_parse_fqdn(const uint8_t * packet, const uint8_t *
    if (strcasecmp(name->domain, MDNS_DEFAULT_DOMAIN) == 0 || strcasecmp(name->domain, "arpa") == 0) {
        return next_data;
    }
-    return 0;
+    name->invalid = true; // mark the current name invalid, but continue with other question
+    return next_data;
 }

 /**
--- a/components/newlib/platform_include/endian.h
+++ b/components/newlib/platform_include/endian.h
@ -1,28 +1,3 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-// Copyright 2020 Francesco Giancane <francesco.giancane@accenture.com>
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-/*
- * This is a compatibility header for <endian.h>.
- * In xtensa-newlib distribution it is located in <machine/endian.h>
- * but most program expect to be plain <endian.h>.
- */
-
-#ifndef XTENSA_COMPAT_ENDIAN_H_INCLUDED
-#define XTENSA_COMPAT_ENDIAN_H_INCLUDED
-#include <machine/endian.h>
-
 /*
 * All the code below is a rework of
 * https://github.com/freebsd/freebsd/blob/master/sys/sys/endian.h
@ -32,7 +7,10 @@
 */

 /*-
- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020 Francesco Giancane <francesco.giancane@accenture.com>
+ * SPDX-FileCopyrightText: 2002 Thomas Moestl <tmm@FreeBSD.org>
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND Apache-2.0
 *
 * Copyright (c) 2002 Thomas Moestl <tmm@FreeBSD.org>
 * All rights reserved.
@ -61,6 +39,17 @@
 * $FreeBSD$
 */

+#pragma once
+
+#include <stdint.h>
+
+/*
+ * This is a compatibility header for <endian.h>.
+ * In xtensa-newlib distribution it is located in <machine/endian.h>
+ * but most program expect to be plain <endian.h>.
+ */
+#include <machine/endian.h>
+
 /*
 * General byte order swapping functions.
 */
@ -209,4 +198,3 @@ le64enc(void *pp, uint64_t u)
 	le32enc(p, (uint32_t)(u & 0xffffffffU));
 	le32enc(p + 4, (uint32_t)(u >> 32));
 }
-#endif /* XTENSA_COMPAT_ENDIAN_H_INCLUDED */
--- a/components/newlib/platform_include/sys/uio.h
+++ b/components/newlib/platform_include/sys/uio.h
@ -1,21 +1,24 @@
-// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-#ifndef _ESP_PLATFORM_SYS_UIO_H_
-#define _ESP_PLATFORM_SYS_UIO_H_
+/*
+ * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <sys/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct iovec;

 int writev(int s, const struct iovec *iov, int iovcnt);

 ssize_t readv(int fd, const struct iovec *iov, int iovcnt);

-#endif // _ESP_PLATFORM_SYS_UIO_H_
+#ifdef __cplusplus
+}
+#endif
--- a/components/newlib/stdatomic.c
+++ b/components/newlib/stdatomic.c
@ -200,7 +200,7 @@ CLANG_DECLARE_ALIAS( __sync_bool_compare_and_swap_ ## n )
 }                                                                                \
 CLANG_DECLARE_ALIAS( __sync_val_compare_and_swap_ ## n )

-#define SYNC_LOCK_TEST_AND_SET(n, type) type  CLANG_ATOMIC_SUFFIX(__sync_lock_test_and_set_ ## n)  (type *ptr, type val, ...) \
+#define SYNC_LOCK_TEST_AND_SET(n, type) type  CLANG_ATOMIC_SUFFIX(__sync_lock_test_and_set_ ## n)  (type *ptr, type val) \
 {                                                                                \
    unsigned state = _ATOMIC_ENTER_CRITICAL();                                   \
    type ret = *ptr;                                                             \
@ -210,7 +210,7 @@ CLANG_DECLARE_ALIAS( __sync_val_compare_and_swap_ ## n )
 }
 CLANG_DECLARE_ALIAS( __sync_lock_test_and_set_ ## n )

-#define SYNC_LOCK_RELEASE(n, type) void  CLANG_ATOMIC_SUFFIX(__sync_lock_release_ ## n)  (type *ptr, ...) \
+#define SYNC_LOCK_RELEASE(n, type) void  CLANG_ATOMIC_SUFFIX(__sync_lock_release_ ## n)  (type *ptr) \
 {                                                                                \
    unsigned state = _ATOMIC_ENTER_CRITICAL();                                   \
    *ptr = 0;                                                                    \
@ -277,16 +277,6 @@ SYNC_VAL_CMP_EXCHANGE(1, uint8_t)
 SYNC_VAL_CMP_EXCHANGE(2, uint16_t)
 SYNC_VAL_CMP_EXCHANGE(4, uint32_t)

-#ifdef __clang__
-
-// LLVM has not implemented native atomic load/stores for riscv targets without the Atomic extension
-// therfore we provide libcalls here when building with the clang toolchain. LLVM thread: https://reviews.llvm.org/D47553.
-ATOMIC_LOAD(1, uint8_t)
-ATOMIC_LOAD(2, uint16_t)
-ATOMIC_LOAD(4, uint32_t)
-ATOMIC_STORE(1, uint8_t)
-ATOMIC_STORE(2, uint16_t)
-ATOMIC_STORE(4, uint32_t)

 SYNC_LOCK_TEST_AND_SET(1, uint8_t)
 SYNC_LOCK_TEST_AND_SET(2, uint16_t)
@ -296,16 +286,19 @@ SYNC_LOCK_RELEASE(1, uint8_t)
 SYNC_LOCK_RELEASE(2, uint16_t)
 SYNC_LOCK_RELEASE(4, uint32_t)

-#endif
+// LLVM has not implemented native atomic load/stores for riscv targets without the Atomic extension. LLVM thread: https://reviews.llvm.org/D47553.
+// Even though GCC does transform them, these libcalls need to be available for the case where a LLVM based project links against IDF.
+ATOMIC_LOAD(1, uint8_t)
+ATOMIC_LOAD(2, uint16_t)
+ATOMIC_LOAD(4, uint32_t)
+ATOMIC_STORE(1, uint8_t)
+ATOMIC_STORE(2, uint16_t)
+ATOMIC_STORE(4, uint32_t)

 #endif // !HAS_ATOMICS_32

 #if !HAS_ATOMICS_64

-ATOMIC_LOAD(8, uint64_t)
-
-ATOMIC_STORE(8, uint64_t)
-
 ATOMIC_EXCHANGE(8, uint64_t)

 CMP_EXCHANGE(8, uint64_t)
@ -334,11 +327,12 @@ SYNC_BOOL_CMP_EXCHANGE(8, uint64_t)

 SYNC_VAL_CMP_EXCHANGE(8, uint64_t)

-#ifdef __clang__
-
 SYNC_LOCK_TEST_AND_SET(8, uint64_t)
 SYNC_LOCK_RELEASE(8, uint64_t)

-#endif
+// LLVM has not implemented native atomic load/stores for riscv targets without the Atomic extension. LLVM thread: https://reviews.llvm.org/D47553.
+// Even though GCC does transform them, these libcalls need to be available for the case where a LLVM based project links against IDF.
+ATOMIC_LOAD(8, uint64_t)
+ATOMIC_STORE(8, uint64_t)

 #endif // !HAS_ATOMICS_64
--- a/components/newlib/system_libs.lf
+++ b/components/newlib/system_libs.lf
@ -4,6 +4,8 @@ entries:
    lib2funcs (noflash_text)
    if IDF_TARGET_ESP32 = n:
        _divsf3 (noflash)
+    if IDF_TARGET_ARCH_RISCV:
+        save-restore (noflash)

 [mapping:gcov]
 archive: libgcov.a
--- a/components/openthread/CMakeLists.txt
+++ b/components/openthread/CMakeLists.txt
@ -31,7 +31,7 @@ idf_component_register(SRC_DIRS "${src_dirs}"
                       EXCLUDE_SRCS "${exclude_srcs}"
                       INCLUDE_DIRS "${public_include_dirs}"
                       PRIV_INCLUDE_DIRS "${private_include_dirs}"
-                       REQUIRES mbedtls ieee802154)
+                       REQUIRES mbedtls ieee802154 console)

 if(CONFIG_OPENTHREAD_ENABLED)
    if(CONFIG_OPENTHREAD_RADIO)
@ -50,7 +50,10 @@ if(CONFIG_OPENTHREAD_ENABLED)

    if(CONFIG_OPENTHREAD_ESP_LIB_FROM_INTERNAL_SRC)
        idf_component_get_property(openthread_port_lib openthread_port COMPONENT_LIB)
-        target_link_libraries(${COMPONENT_LIB} PUBLIC $<TARGET_FILE:${openthread_port_lib}>)
+        idf_component_get_property(esp_system_lib esp_system COMPONENT_LIB)
+        target_link_libraries(${COMPONENT_LIB} PUBLIC
+                              $<TARGET_FILE:${openthread_port_lib}>
+                              $<TARGET_FILE:${esp_system_lib}>)

        if(CONFIG_OPENTHREAD_BORDER_ROUTER)
            idf_component_get_property(openthread_br_lib openthread_br COMPONENT_LIB)
--- a/Show More
+++ b/Show More