/** * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ #pragma once #include #include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif /** ASSIST_DEBUG_CORE_0_MONTR_ENA_REG register * core0 monitor enable configuration register */ #define ASSIST_DEBUG_CORE_0_MONTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0) /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0; * Configures whether to monitor read operations in region 0 by the Data bus. \\ * 0: Not monitor\\ * 1: Monitor\\ */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0; * Configures whether to monitor write operations in region 0 by the Data bus.\\ * 0: Not monitor\\ * 1: Monitor\\ */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0; * Configures whether to monitor read operations in region 1 by the Data bus.\\ * 0: Not Monitor\\ * 1: Monitor\\ */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0; * Configures whether to monitor write operations in region 1 by the Data bus.\\ * 0: Not Monitor\\ * 1: Monitor\\ */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 /** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0; * Configures whether to monitor read operations in region 0 by the Peripheral bus.\\ * 0: Not Monitor\\ * 1: Monitor\\ */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4 /** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0; * Configures whether to monitor write operations in region 0 by the Peripheral bus.\\ * 0: Not Monitor\\ * 1: Monitor\\ */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5 /** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0; * Configures whether to monitor read operations in region 1 by the Peripheral bus.\\ * 0: Not Monitor\\ * 1: Monitor\\ */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6 /** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0; * Configures whether to monitor write operations in region 1 by the Peripheral bus.\\ * 0: Not Monitor\\ * 1: Monitor\\ */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7 /** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0; * Configures whether to monitor SP exceeding the lower bound address of SP monitored * region.\\ * 0: Not Monitor\\ * 1: Monitor\\ */ #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8 /** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0; * Configures whether to monitor SP exceeding the upper bound address of SP monitored * region.\\ * 0: Not Monitor\\ * 1: Monitor\\ */ #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9 /** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0; * IBUS busy monitor enable */ #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10)) #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S) #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0; * DBUS busy monitor enbale */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S) #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11 /** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register * core0 monitor interrupt status register */ #define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4) /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0; * The raw interrupt status of read operations in region 0 by Data bus. */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0; * The raw interrupt status of write operations in region 0 by Data bus. */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0; * The raw interrupt status of read operations in region 1 by Data bus. */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0; * The raw interrupt status of write operations in region 1 by Data bus. */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 /** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0; * The raw interrupt status of read operations in region 0 by Peripheral bus. */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4 /** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0; * The raw interrupt status of write operations in region 0 by Peripheral bus. */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5 /** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0; * The raw interrupt status of read operations in region 1 by Peripheral bus. */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6 /** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0; * The raw interrupt status of write operations in region 1 by Peripheral bus. */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7 /** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0; * The raw interrupt status of SP exceeding the lower bound address of SP monitored * region. */ #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8 /** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0; * The raw interrupt status of SP exceeding the upper bound address of SP monitored * region. */ #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9 /** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0; * IBUS busy monitor interrupt status */ #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10)) #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S) #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0; * DBUS busy monitor initerrupt status */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11)) #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S) #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11 /** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register * core0 monitor interrupt enable register */ #define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8) /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA : R/W; bitpos: [0]; default: 0; * Core0 dram0 area0 read monitor interrupt enable */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA (BIT(0)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_INTR_ENA_S 0 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA : R/W; bitpos: [1]; default: 0; * Core0 dram0 area0 write monitor interrupt enable */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA (BIT(1)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_INTR_ENA_S 1 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA : R/W; bitpos: [2]; default: 0; * Core0 dram0 area1 read monitor interrupt enable */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA (BIT(2)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_INTR_ENA_S 2 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA : R/W; bitpos: [3]; default: 0; * Core0 dram0 area1 write monitor interrupt enable */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA (BIT(3)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_INTR_ENA_S 3 /** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA : R/W; bitpos: [4]; default: 0; * Core0 PIF area0 read monitor interrupt enable */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA (BIT(4)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_INTR_ENA_S 4 /** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA : R/W; bitpos: [5]; default: 0; * Core0 PIF area0 write monitor interrupt enable */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA (BIT(5)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_INTR_ENA_S 5 /** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA : R/W; bitpos: [6]; default: 0; * Core0 PIF area1 read monitor interrupt enable */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA (BIT(6)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_INTR_ENA_S 6 /** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA : R/W; bitpos: [7]; default: 0; * Core0 PIF area1 write monitor interrupt enable */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA (BIT(7)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_INTR_ENA_S 7 /** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA : R/W; bitpos: [8]; default: 0; * Core0 stackpoint underflow monitor interrupt enable */ #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA (BIT(8)) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_INTR_ENA_S 8 /** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA : R/W; bitpos: [9]; default: 0; * Core0 stackpoint overflow monitor interrupt enable */ #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA (BIT(9)) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_INTR_ENA_S 9 /** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [10]; default: 0; * IBUS busy monitor interrupt enable */ #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA (BIT(10)) #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S) #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_INTR_ENA_S 10 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA : R/W; bitpos: [11]; default: 0; * DBUS busy monitor interrupt enbale */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA (BIT(11)) #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S) #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_V 0x00000001U #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_INTR_ENA_S 11 /** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register * core0 monitor interrupt clear register */ #define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc) /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : WT; bitpos: [0]; default: 0; * Write 1 to clear the interrupt for read operations in region 0 by Data bus. */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : WT; bitpos: [1]; default: 0; * Write 1 to clear the interrupt for write operations in region 0 by Data bus. */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : WT; bitpos: [2]; default: 0; * Write 1 to clear the interrupt for read operations in region 1 by Data bus. */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : WT; bitpos: [3]; default: 0; * Write 1 to clear the interrupt for write operations in region 1 by Data bus. */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 /** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : WT; bitpos: [4]; default: 0; * Write 1 to clear the interrupt for read operations in region 0 by Peripheral bus. */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4 /** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : WT; bitpos: [5]; default: 0; * Write 1 to clear the interrupt for write operations in region 0 by Peripheral bus. */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5 /** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : WT; bitpos: [6]; default: 0; * Write 1 to clear the interrupt for read operations in region 1 by Peripheral bus. */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6 /** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : WT; bitpos: [7]; default: 0; * Write 1 to clear the interrupt for write operations in region 1 by Peripheral bus. */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7 /** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : WT; bitpos: [8]; default: 0; * Write 1 to clear the interrupt for SP exceeding the lower bound address of SP * monitored region. */ #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U #define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8 /** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : WT; bitpos: [9]; default: 0; * Write 1 to clear the interrupt for SP exceeding the upper bound address of SP * monitored region. */ #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S) #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U #define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9 /** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [10]; default: 0; * IBUS busy monitor interrupt clr */ #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10)) #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S) #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : WT; bitpos: [11]; default: 0; * DBUS busy monitor interrupt clr */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11)) #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S) #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register * Configures lower boundary address of region 0 monitored on Data bus */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10) /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; * Configures the lower bound address of Data bus region 0. */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register * Configures upper boundary address of region 0 monitored on Data bus */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14) /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0; * Configures the upper bound address of Data bus region 0. */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register * Configures lower boundary address of region 1 monitored on Data bus */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18) /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; * Configures the lower bound address of Data bus region 1. */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0 /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register * Configures upper boundary address of region 1 monitored on Data bus */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c) /** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0; * Configures the upper bound address of Data bus region 1. */ #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S) #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0 /** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register * Configures lower boundary address of region 0 monitored on Peripheral bus */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20) /** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295; * Configures the lower bound address of Peripheral bus region 0. */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0 /** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register * Configures upper boundary address of region 0 monitored on Peripheral bus */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24) /** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0; * Configures the upper bound address of Peripheral bus region 0. */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0 /** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register * Configures lower boundary address of region 1 monitored on Peripheral bus */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28) /** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295; * Configures the lower bound address of Peripheral bus region 1. */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0 /** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register * Configures upper boundary address of region 1 monitored on Peripheral bus */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c) /** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0; * Configures the upper bound address of Peripheral bus region 1. */ #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S) #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0 /** ASSIST_DEBUG_CORE_0_AREA_PC_REG register * Region monitoring HP CPU PC status register */ #define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30) /** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0; * Represents the PC value when an interrupt is triggered during region monitoring. */ #define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S) #define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_PC_S 0 /** ASSIST_DEBUG_CORE_0_AREA_SP_REG register * Region monitoring HP CPU SP status register */ #define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34) /** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0; * Represents the SP value when an interrupt is triggered during region monitoring. */ #define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S) #define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_AREA_SP_S 0 /** ASSIST_DEBUG_CORE_0_SP_MIN_REG register * Configures stack monitoring lower boundary address */ #define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38) /** ASSIST_DEBUG_CORE_0_SP_MIN : R/W; bitpos: [31:0]; default: 0; * Configures the lower bound address of SP. */ #define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S) #define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_SP_MIN_S 0 /** ASSIST_DEBUG_CORE_0_SP_MAX_REG register * Configures stack monitoring upper boundary address */ #define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c) /** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295; * Configures the upper bound address of SP. */ #define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S) #define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_SP_MAX_S 0 /** ASSIST_DEBUG_CORE_0_SP_PC_REG register * Stack monitoring HP CPU PC status register */ #define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40) /** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0; * Represents the PC value during stack monitoring. */ #define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S) #define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_SP_PC_S 0 /** ASSIST_DEBUG_CORE_0_RCD_EN_REG register * HP CPU PC logging enable register */ #define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44) /** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : R/W; bitpos: [0]; default: 0; * Configures whether to enable PC logging.\\ * 0: Disable\\ * 1: ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG starts to record PC in real time\\ */ #define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0)) #define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S) #define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U #define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : R/W; bitpos: [1]; default: 0; * Configures whether to enable HP CPU debugging.\\ * 0: Disable\\ * 1: HP CPU outputs PC\\ */ #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1)) #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S) #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register * PC logging register */ #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48) /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0; * Represents the PC value at HP CPU reset. */ #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S) #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register * PC logging register */ #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c) /** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0; * Represents SP. */ #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S) #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0 /** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register * exception monitor status register0 */ #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50) /** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0; * reg_core_0_iram0_recording_addr_0 */ #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x3FFFFFFFU #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S) #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0x3FFFFFFFU #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0 /** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [30]; default: 0; * reg_core_0_iram0_recording_wr_0 */ #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(30)) #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S) #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x00000001U #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 30 /** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [31]; default: 0; * reg_core_0_iram0_recording_loadstore_0 */ #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(31)) #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S) #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x00000001U #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 31 /** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register * exception monitor status register1 */ #define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54) /** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0; * reg_core_0_iram0_recording_addr_1 */ #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x3FFFFFFFU #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S) #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0x3FFFFFFFU #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0 /** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [30]; default: 0; * reg_core_0_iram0_recording_wr_1 */ #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(30)) #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S) #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x00000001U #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 30 /** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [31]; default: 0; * reg_core_0_iram0_recording_loadstore_1 */ #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(31)) #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S) #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x00000001U #define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 31 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register * exception monitor status register2 */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58) /** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [0]; default: 0; * reg_core_0_dram0_recording_wr_0 */ #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(0)) #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S) #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x00000001U #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 0 /** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [4:1]; default: 0; * reg_core_0_dram0_recording_byteen_0 */ #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000FU #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S) #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0x0000000FU #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 1 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register * exception monitor status register3 */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c) /** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [29:0]; default: 0; * reg_core_0_dram0_recording_addr_0 */ #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x3FFFFFFFU #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S) #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0x3FFFFFFFU #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register * exception monitor status register4 */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60) /** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0; * reg_core_0_dram0_recording_pc_0 */ #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S) #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register * exception monitor status register5 */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64) /** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [0]; default: 0; * reg_core_0_dram0_recording_wr_1 */ #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(0)) #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S) #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x00000001U #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 0 /** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [4:1]; default: 0; * reg_core_0_dram0_recording_byteen_1 */ #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000FU #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S) #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0x0000000FU #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 1 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG register * exception monitor status register6 */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68) /** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [29:0]; default: 0; * reg_core_0_dram0_recording_addr_1 */ #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x3FFFFFFFU #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S) #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0x3FFFFFFFU #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0 /** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG register * exception monitor status register7 */ #define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c) /** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0; * reg_core_0_dram0_recording_pc_1 */ #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S) #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0 /** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register * cpu status register */ #define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70) /** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0; * Represents the PC of the last command before the HP CPU enters exception. */ #define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S) #define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU #define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0 /** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register * cpu status register */ #define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74) /** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0; * Represents whether RISC-V CPU (HP CPU) is in debugging mode.\\ * 1: In debugging mode\\ * 0: Not in debugging mode\\ */ #define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0)) #define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S) #define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U #define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0 /** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0; * Represents the status of the RISC-V CPU (HP CPU) debug module.\\ * 1: Active status\\ * Other: Inactive status\\ */ #define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1)) #define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S) #define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U #define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1 /** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register * exception monitor status register8 */ #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x100) /** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0; * reg_core_x_iram0_dram0_limit_cycle_0 */ #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFFU #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S) #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0x000FFFFFU #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0 /** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register * exception monitor status register9 */ #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x104) /** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0; * reg_core_x_iram0_dram0_limit_cycle_1 */ #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFFU #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S) #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0x000FFFFFU #define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0 /** ASSIST_DEBUG_CLOCK_GATE_REG register * Register clock control */ #define ASSIST_DEBUG_CLOCK_GATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x108) /** ASSIST_DEBUG_CLK_EN : R/W; bitpos: [0]; default: 1; * Configures whether to enable the register clock gating. \\ * 0: Disable\\ * 1: Enable\\ */ #define ASSIST_DEBUG_CLK_EN (BIT(0)) #define ASSIST_DEBUG_CLK_EN_M (ASSIST_DEBUG_CLK_EN_V << ASSIST_DEBUG_CLK_EN_S) #define ASSIST_DEBUG_CLK_EN_V 0x00000001U #define ASSIST_DEBUG_CLK_EN_S 0 /** ASSIST_DEBUG_DATE_REG register * Version control register */ #define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3fc) /** ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 34640176; * version register */ #define ASSIST_DEBUG_DATE 0x0FFFFFFFU #define ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_DATE_S) #define ASSIST_DEBUG_DATE_V 0x0FFFFFFFU #define ASSIST_DEBUG_DATE_S 0 #ifdef __cplusplus } #endif