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65 lines
2.7 KiB
Plaintext
65 lines
2.7 KiB
Plaintext
menu "ESP-Driver:Parallel IO Configurations"
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depends on SOC_PARLIO_SUPPORTED
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config PARLIO_TX_ISR_HANDLER_IN_IRAM
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bool "Place Parallel IO TX ISR handler in IRAM to reduce latency"
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default y
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select PARLIO_OBJ_CACHE_SAFE
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help
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Place Parallel IO TX ISR handler in IRAM to reduce latency caused by cache miss.
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config PARLIO_RX_ISR_HANDLER_IN_IRAM
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bool "Place Parallel IO RX ISR handler in IRAM to reduce latency"
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default y
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select PARLIO_OBJ_CACHE_SAFE
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help
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Place Parallel IO RX ISR handler in IRAM to reduce latency caused by cache miss.
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config PARLIO_TX_ISR_CACHE_SAFE
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bool "Allow Parallel IO TX ISR to execute when cache is disabled"
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select PARLIO_TX_ISR_HANDLER_IN_IRAM
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select GDMA_ISR_IRAM_SAFE
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default n
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help
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Enable this option to allow the Parallel IO TX Interrupt Service Routine (ISR)
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to execute even when the cache is disabled. This can be useful in scenarios where the cache
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might be turned off, but the Parallel IO TX functionality is still required to operate correctly.
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config PARLIO_RX_ISR_CACHE_SAFE
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bool "Allow Parallel IO RX ISR to execute when cache is disabled"
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select PARLIO_RX_ISR_HANDLER_IN_IRAM
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select GDMA_ISR_IRAM_SAFE
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default n
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help
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Enable this option to allow the Parallel IO RX Interrupt Service Routine (ISR)
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to execute even when the cache is disabled. This can be useful in scenarios where the cache
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might be turned off, but the Parallel IO RX functionality is still required to operate correctly.
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config PARLIO_OBJ_CACHE_SAFE
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bool
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default n
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help
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This will ensure the driver object will not be allocated from a memory region
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where its cache can be disabled.
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config PARLIO_ENABLE_DEBUG_LOG
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bool "Force enable debug log"
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default n
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help
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If enabled, Parallel IO driver component will:
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1. ignore the global logging settings
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2. compile all log messages into the binary
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3. set the runtime log level to VERBOSE
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Please enable this option by caution, as it will increase the binary size.
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config PARLIO_ISR_IRAM_SAFE
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bool "Parallel IO ISR IRAM-Safe (Deprecated)"
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default n
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select PARLIO_TX_ISR_CACHE_SAFE
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select PARLIO_RX_ISR_CACHE_SAFE
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help
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Ensure the Parallel IO interrupt is IRAM-Safe by allowing the interrupt handler to be
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executable when the cache is disabled (e.g. SPI Flash write).
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endmenu # Parallel IO Configuration
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