mirror of
https://github.com/espressif/esp-idf
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897 lines
45 KiB
C
897 lines
45 KiB
C
/**
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** ASSIST_DEBUG_CORE_0_INTR_ENA_REG register
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* register description
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*/
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#define ASSIST_DEBUG_CORE_0_INTR_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0)
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/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0))
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S)
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0
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/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W; bitpos: [1]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1))
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S)
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1
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/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W; bitpos: [2]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2))
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S)
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2
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/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W; bitpos: [3]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3))
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S)
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3
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/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W; bitpos: [4]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4))
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S)
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4
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/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W; bitpos: [5]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5))
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S)
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5
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/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W; bitpos: [6]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6))
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S)
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6
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/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W; bitpos: [7]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7))
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S)
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7
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/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W; bitpos: [8]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8))
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S)
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8
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/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W; bitpos: [9]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9))
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S)
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9
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/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [10]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10))
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#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S)
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#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10
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/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W; bitpos: [11]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11))
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#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S)
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#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11
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/** ASSIST_DEBUG_CORE_0_INTR_RAW_REG register
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* register description
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*/
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#define ASSIST_DEBUG_CORE_0_INTR_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4)
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/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO; bitpos: [0]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0))
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S)
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0
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/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO; bitpos: [1]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1))
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S)
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1
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/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO; bitpos: [2]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2))
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S)
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2
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/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO; bitpos: [3]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3))
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S)
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3
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/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO; bitpos: [4]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4))
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S)
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4
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/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO; bitpos: [5]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5))
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S)
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5
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/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO; bitpos: [6]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6))
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S)
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6
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/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO; bitpos: [7]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7))
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S)
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7
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/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO; bitpos: [8]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8))
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S)
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8
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/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO; bitpos: [9]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9))
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S)
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9
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/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [10]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10))
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#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S)
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#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10
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/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO; bitpos: [11]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11))
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#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S)
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#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11
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/** ASSIST_DEBUG_CORE_0_INTR_RLS_REG register
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* register description
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*/
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#define ASSIST_DEBUG_CORE_0_INTR_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8)
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/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W; bitpos: [0]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0))
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S)
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0
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/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W; bitpos: [1]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1))
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S)
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1
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/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W; bitpos: [2]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS (BIT(2))
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S)
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S 2
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/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W; bitpos: [3]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS (BIT(3))
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S)
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S 3
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/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W; bitpos: [4]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS (BIT(4))
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S)
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S 4
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/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W; bitpos: [5]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5))
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S)
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5
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/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W; bitpos: [6]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS (BIT(6))
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#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S 6
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|
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W; bitpos: [7]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS (BIT(7))
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S)
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|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S 7
|
|
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W; bitpos: [8]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(8))
|
|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S)
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|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 8
|
|
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W; bitpos: [9]; default: 0;
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|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9))
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|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S)
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|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9
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|
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [10]; default: 0;
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|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10))
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S)
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|
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10
|
|
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W; bitpos: [11]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11))
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|
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S)
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S 11
|
|
|
|
/** ASSIST_DEBUG_CORE_0_INTR_CLR_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_INTR_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0xc)
|
|
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W; bitpos: [0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0))
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0
|
|
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W; bitpos: [1]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1))
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1
|
|
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W; bitpos: [2]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2))
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2
|
|
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W; bitpos: [3]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3))
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3
|
|
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W; bitpos: [4]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4))
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4
|
|
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W; bitpos: [5]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5))
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5
|
|
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W; bitpos: [6]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6))
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6
|
|
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W; bitpos: [7]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7))
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7
|
|
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W; bitpos: [8]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8))
|
|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S)
|
|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8
|
|
/** ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W; bitpos: [9]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9))
|
|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V << ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S)
|
|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9
|
|
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W; bitpos: [10]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10))
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S)
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10
|
|
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W; bitpos: [11]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11))
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V << ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S)
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11
|
|
|
|
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10)
|
|
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14)
|
|
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W; bitpos: [31:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x18)
|
|
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1c)
|
|
/** ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W; bitpos: [31:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x20)
|
|
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x24)
|
|
/** ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W; bitpos: [31:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x28)
|
|
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W; bitpos: [31:0]; default: 4294967295;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x2c)
|
|
/** ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W; bitpos: [31:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V << ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_AREA_PC_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x30)
|
|
/** ASSIST_DEBUG_CORE_0_AREA_PC : RO; bitpos: [31:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PC_M (ASSIST_DEBUG_CORE_0_AREA_PC_V << ASSIST_DEBUG_CORE_0_AREA_PC_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_AREA_SP_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x34)
|
|
/** ASSIST_DEBUG_CORE_0_AREA_SP : RO; bitpos: [31:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_SP_M (ASSIST_DEBUG_CORE_0_AREA_SP_V << ASSIST_DEBUG_CORE_0_AREA_SP_S)
|
|
#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_SP_MIN_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x38)
|
|
/** ASSIST_DEBUG_CORE_0_SP_MIN : RW; bitpos: [31:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_SP_MIN_M (ASSIST_DEBUG_CORE_0_SP_MIN_V << ASSIST_DEBUG_CORE_0_SP_MIN_S)
|
|
#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_SP_MAX_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x3c)
|
|
/** ASSIST_DEBUG_CORE_0_SP_MAX : R/W; bitpos: [31:0]; default: 4294967295;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_SP_MAX_M (ASSIST_DEBUG_CORE_0_SP_MAX_V << ASSIST_DEBUG_CORE_0_SP_MAX_S)
|
|
#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_SP_PC_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x40)
|
|
/** ASSIST_DEBUG_CORE_0_SP_PC : RO; bitpos: [31:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_SP_PC_M (ASSIST_DEBUG_CORE_0_SP_PC_V << ASSIST_DEBUG_CORE_0_SP_PC_S)
|
|
#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_SP_PC_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_RCD_EN_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_RCD_EN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x44)
|
|
/** ASSIST_DEBUG_CORE_0_RCD_RECORDEN : RW; bitpos: [0]; default: 0;
|
|
* enable recording function, if enable, assist_debug will update PdebugPC, so you can
|
|
* read it
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN (BIT(0))
|
|
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_M (ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V << ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S)
|
|
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_RCD_RECORDEN_S 0
|
|
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN : RW; bitpos: [1]; default: 0;
|
|
* enable CPU Pdebug function, if enable, CPU will update PdebugPC
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN (BIT(1))
|
|
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S)
|
|
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN_S 1
|
|
|
|
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x48)
|
|
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO; bitpos: [31:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)
|
|
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x4c)
|
|
/** ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP : RO; bitpos: [31:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_M (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V << ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S)
|
|
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x50)
|
|
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x00FFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0x00FFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0
|
|
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(24))
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S)
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 24
|
|
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO; bitpos: [25]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25))
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S)
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25
|
|
|
|
/** ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x54)
|
|
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x00FFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0x00FFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0
|
|
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(24))
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S)
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 24
|
|
/** ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO; bitpos: [25]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25))
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V << ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S)
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25
|
|
|
|
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x58)
|
|
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO; bitpos: [23:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x00FFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0x00FFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0
|
|
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO; bitpos: [24]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(24))
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S)
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 24
|
|
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO; bitpos: [28:25]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000000FU
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0x0000000FU
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 25
|
|
|
|
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x5c)
|
|
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO; bitpos: [31:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x60)
|
|
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO; bitpos: [23:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x00FFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0x00FFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0
|
|
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO; bitpos: [24]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(24))
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S)
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 24
|
|
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO; bitpos: [28:25]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000000FU
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0x0000000FU
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 25
|
|
|
|
/** ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x64)
|
|
/** ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO; bitpos: [31:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V << ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x68)
|
|
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W; bitpos: [19:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFFU
|
|
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)
|
|
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0x000FFFFFU
|
|
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0
|
|
|
|
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x6c)
|
|
/** ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W; bitpos: [19:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFFU
|
|
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V << ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)
|
|
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0x000FFFFFU
|
|
#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0
|
|
|
|
/** ASSIST_DEBUG_LOG_SETTING_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_LOG_SETTING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x70)
|
|
/** ASSIST_DEBUG_LOG_ENA : R/W; bitpos: [2:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_LOG_ENA 0x00000007U
|
|
#define ASSIST_DEBUG_LOG_ENA_M (ASSIST_DEBUG_LOG_ENA_V << ASSIST_DEBUG_LOG_ENA_S)
|
|
#define ASSIST_DEBUG_LOG_ENA_V 0x00000007U
|
|
#define ASSIST_DEBUG_LOG_ENA_S 0
|
|
/** ASSIST_DEBUG_LOG_MODE : R/W; bitpos: [6:3]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_LOG_MODE 0x0000000FU
|
|
#define ASSIST_DEBUG_LOG_MODE_M (ASSIST_DEBUG_LOG_MODE_V << ASSIST_DEBUG_LOG_MODE_S)
|
|
#define ASSIST_DEBUG_LOG_MODE_V 0x0000000FU
|
|
#define ASSIST_DEBUG_LOG_MODE_S 3
|
|
/** ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W; bitpos: [7]; default: 1;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE (BIT(7))
|
|
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M (ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V << ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S)
|
|
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V 0x00000001U
|
|
#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S 7
|
|
|
|
/** ASSIST_DEBUG_LOG_DATA_0_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_LOG_DATA_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x74)
|
|
/** ASSIST_DEBUG_LOG_DATA_0 : R/W; bitpos: [31:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_LOG_DATA_0 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_LOG_DATA_0_M (ASSIST_DEBUG_LOG_DATA_0_V << ASSIST_DEBUG_LOG_DATA_0_S)
|
|
#define ASSIST_DEBUG_LOG_DATA_0_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_LOG_DATA_0_S 0
|
|
|
|
/** ASSIST_DEBUG_LOG_DATA_MASK_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_LOG_DATA_MASK_REG (DR_REG_ASSIST_DEBUG_BASE + 0x78)
|
|
/** ASSIST_DEBUG_LOG_DATA_SIZE : R/W; bitpos: [15:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_LOG_DATA_SIZE 0x0000FFFFU
|
|
#define ASSIST_DEBUG_LOG_DATA_SIZE_M (ASSIST_DEBUG_LOG_DATA_SIZE_V << ASSIST_DEBUG_LOG_DATA_SIZE_S)
|
|
#define ASSIST_DEBUG_LOG_DATA_SIZE_V 0x0000FFFFU
|
|
#define ASSIST_DEBUG_LOG_DATA_SIZE_S 0
|
|
|
|
/** ASSIST_DEBUG_LOG_MIN_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_LOG_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x7c)
|
|
/** ASSIST_DEBUG_LOG_MIN : R/W; bitpos: [31:0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_LOG_MIN 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_LOG_MIN_M (ASSIST_DEBUG_LOG_MIN_V << ASSIST_DEBUG_LOG_MIN_S)
|
|
#define ASSIST_DEBUG_LOG_MIN_V 0xFFFFFFFFU
|
|
#define ASSIST_DEBUG_LOG_MIN_S 0
|
|
|
|
/** ASSIST_DEBUG_LOG_MAX_REG register
|
|
* register description
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*/
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#define ASSIST_DEBUG_LOG_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x80)
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/** ASSIST_DEBUG_LOG_MAX : R/W; bitpos: [31:0]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_LOG_MAX 0xFFFFFFFFU
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#define ASSIST_DEBUG_LOG_MAX_M (ASSIST_DEBUG_LOG_MAX_V << ASSIST_DEBUG_LOG_MAX_S)
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#define ASSIST_DEBUG_LOG_MAX_V 0xFFFFFFFFU
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#define ASSIST_DEBUG_LOG_MAX_S 0
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/** ASSIST_DEBUG_LOG_MEM_START_REG register
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* register description
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*/
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#define ASSIST_DEBUG_LOG_MEM_START_REG (DR_REG_ASSIST_DEBUG_BASE + 0x84)
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/** ASSIST_DEBUG_LOG_MEM_START : R/W; bitpos: [31:0]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_LOG_MEM_START 0xFFFFFFFFU
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#define ASSIST_DEBUG_LOG_MEM_START_M (ASSIST_DEBUG_LOG_MEM_START_V << ASSIST_DEBUG_LOG_MEM_START_S)
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#define ASSIST_DEBUG_LOG_MEM_START_V 0xFFFFFFFFU
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#define ASSIST_DEBUG_LOG_MEM_START_S 0
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/** ASSIST_DEBUG_LOG_MEM_END_REG register
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* register description
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*/
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#define ASSIST_DEBUG_LOG_MEM_END_REG (DR_REG_ASSIST_DEBUG_BASE + 0x88)
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/** ASSIST_DEBUG_LOG_MEM_END : R/W; bitpos: [31:0]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_LOG_MEM_END 0xFFFFFFFFU
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#define ASSIST_DEBUG_LOG_MEM_END_M (ASSIST_DEBUG_LOG_MEM_END_V << ASSIST_DEBUG_LOG_MEM_END_S)
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#define ASSIST_DEBUG_LOG_MEM_END_V 0xFFFFFFFFU
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#define ASSIST_DEBUG_LOG_MEM_END_S 0
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/** ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG register
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* register description
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*/
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#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x8c)
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/** ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO; bitpos: [31:0]; default: 0;
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* Need add description
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*/
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#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR 0xFFFFFFFFU
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#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M (ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V << ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S)
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#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V 0xFFFFFFFFU
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#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S 0
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/** ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG register
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* register description
|
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*/
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#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG (DR_REG_ASSIST_DEBUG_BASE + 0x90)
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/** ASSIST_DEBUG_LOG_MEM_FULL_FLAG : RO; bitpos: [0]; default: 0;
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* Need add description
|
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*/
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#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG (BIT(0))
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#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M (ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V << ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S)
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#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V 0x00000001U
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#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S 0
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/** ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG : R/W; bitpos: [1]; default: 0;
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* Need add description
|
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*/
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#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG (BIT(1))
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#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_M (ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V << ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S)
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#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_V 0x00000001U
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#define ASSIST_DEBUG_CLR_LOG_MEM_FULL_FLAG_S 1
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/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG register
|
|
* register description
|
|
*/
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#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXCEPTION_REG (DR_REG_ASSIST_DEBUG_BASE + 0x94)
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/** ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC : RO; bitpos: [31:0]; default: 0;
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|
* Need add description
|
|
*/
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#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC 0xFFFFFFFFU
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#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_M (ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V << ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S)
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#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_V 0xFFFFFFFFU
|
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#define ASSIST_DEBUG_CORE_0_LASTPC_BEFORE_EXC_S 0
|
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/** ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG register
|
|
* register description
|
|
*/
|
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#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x98)
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/** ASSIST_DEBUG_CORE_0_DEBUG_MODE : RO; bitpos: [0]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DEBUG_MODE (BIT(0))
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#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODE_S)
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#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_V 0x00000001U
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#define ASSIST_DEBUG_CORE_0_DEBUG_MODE_S 0
|
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/** ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE : RO; bitpos: [1]; default: 0;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE (BIT(1))
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#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_M (ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V << ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S)
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#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_V 0x00000001U
|
|
#define ASSIST_DEBUG_CORE_0_DEBUG_MODULE_ACTIVE_S 1
|
|
|
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/** ASSIST_DEBUG_DATE_REG register
|
|
* register description
|
|
*/
|
|
#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1fc)
|
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/** ASSIST_DEBUG_ASSIST_DEBUG_DATE : R/W; bitpos: [27:0]; default: 33587216;
|
|
* Need add description
|
|
*/
|
|
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE 0x0FFFFFFFU
|
|
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_M (ASSIST_DEBUG_ASSIST_DEBUG_DATE_V << ASSIST_DEBUG_ASSIST_DEBUG_DATE_S)
|
|
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_V 0x0FFFFFFFU
|
|
#define ASSIST_DEBUG_ASSIST_DEBUG_DATE_S 0
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|