Marius Vikhammer 9f49fa2c1b Merge branch 'bugfix/s3_ulp_riscv_cocpu_trap_v5.0' into 'release/v5.0' ...

ulp-riscv: always force COCPU clock on S3 (v5.0)

See merge request espressif/esp-idf!20768

2022-12-05 14:50:48 +08:00

..

cmake

tools: cmake: check tool supported version with idf_tools.py

2022-10-18 12:27:55 +04:00

ld

ulp-riscv: add support for using ADC as well as an example show-casing it.

2022-07-11 09:31:22 +08:00

test_apps

ulp: fix -Wformat errors in ULP tests

2022-08-04 12:19:28 +08:00

ulp_common

rtc_clk: Clean up some clock related enum and macro in soc/rtc.h, replace with new ones in

2022-05-24 22:59:41 +08:00

ulp_fsm

ulp: remove ESP32 ULP TSENS references

2022-07-05 17:37:13 +08:00

ulp_riscv

ulp-riscv: always force COCPU clock on S3

2022-10-25 13:50:55 +08:00

.build-test-rules.yml

ulp: migrate tests to pytest embedded

2022-08-03 09:36:17 +08:00

CMakeLists.txt

build system: re-add -Wno-format as private flag for some components

2022-08-03 16:42:47 +04:00

component_ulp_common.cmake

…

esp32ulp_mapgen.py

…

Kconfig

Add ULP-RISCV print and bitbanged UART tx API

2022-07-29 12:18:01 +08:00

project_include.cmake

ulp-riscv: add support for using ADC as well as an example show-casing it.

2022-07-11 09:31:22 +08:00

sdkconfig.rename.esp32

soc: moved kconfig options out of the target component.

2022-04-21 12:09:43 +08:00

sdkconfig.rename.esp32s2

soc: moved kconfig options out of the target component.

2022-04-21 12:09:43 +08:00