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esp-idf/components/esp32s2/test
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Marius Vikhammer 0a95151a75 unit_test: Refactor all performance tests that rely on cache compensated timer 
There is no ccomp timer on C3, which means our performance tests will start
failing again due to variance caused by cache misses.

This MR adds TEST_PERFORMANCE_CCOMP_ macro that will only fail
performance test if CCOMP timer is supported on the target
2020-12-22 18:56:24 +11:00
..
CMakeLists.txt
Whitespace: Automated whitespace fixes (large commit)
2020-11-11 07:36:35 +00:00
component.mk
…
digital_signature_test_cases.h
Digital Signature HW: adding S2 support
2020-04-01 13:47:13 +08:00
gen_digital_signature_tests.py
Digital Signature HW: adding S2 support
2020-04-01 13:47:13 +08:00
test_ds.c
esp_rom: extract common efuse apis into esp_rom_efuse.h
2020-07-15 10:40:50 +08:00
test_hmac.c
HMAC: adds test case for downstream JTAG Re-enable support
2020-09-28 23:41:52 +05:30
test_random.c
esp32s2: add more unit test for esp32s2
2020-06-03 13:16:13 +08:00
test_sha.c
unit_test: Refactor all performance tests that rely on cache compensated timer
2020-12-22 18:56:24 +11:00
test_spiram_cache_flush.c
…
test_stack_check_cxx.cpp
…
test_stack_check.c
…