mirror of
https://github.com/espressif/esp-idf
synced 2025-04-06 23:00:12 -04:00
416 lines
11 KiB
C
416 lines
11 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Key Registers */
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/** Type of key_n register
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* AES key data register 0
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*/
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typedef union {
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struct {
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/** key_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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uint32_t key_0:32;
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};
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uint32_t val;
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} aes_key_n_reg_t;
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/** Group: TEXT_IN Registers */
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/** Type of text_in_n register
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* Source text data register 0
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*/
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typedef union {
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struct {
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/** text_in_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_in_0 that is a part of source text material.
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*/
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uint32_t text_in_0:32;
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};
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uint32_t val;
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} aes_text_in_n_reg_t;
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/** Group: TEXT_OUT Registers */
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/** Type of text_out_n register
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* Result text data register 0
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*/
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typedef union {
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struct {
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/** text_out_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_out_0 that is a part of result text material.
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*/
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uint32_t text_out_0:32;
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};
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uint32_t val;
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} aes_text_out_n_reg_t;
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/** Group: Control / Configuration Registers */
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/** Type of mode register
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* Defines key length and encryption / decryption
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*/
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typedef union {
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struct {
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/** mode : R/W; bitpos: [2:0]; default: 0;
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* Configures the key length and encryption / decryption of the AES accelerator.\\
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* 0: AES-128 encryption\\
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* 1: AES-192 encryption\\
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* 2: AES-256 encryption\\
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* 3: Reserved\\
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* 4: AES-128 decryption\\
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* 5: AES-192 decryption\\
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* 6: AES-256 decryption\\
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* 7: Reserved\\
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*/
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uint32_t mode:3;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} aes_mode_reg_t;
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/** Type of trigger register
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* Operation start controlling register
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*/
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typedef union {
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struct {
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/** trigger : WT; bitpos: [0]; default: 0;
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* Configures whether or not to start AES operation. \\
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* 0: No effect\\
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* 1: Start\\
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*/
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uint32_t trigger:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} aes_trigger_reg_t;
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/** Type of dma_enable register
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* Selects the working mode of the AES accelerator
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*/
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typedef union {
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struct {
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/** dma_enable : R/W; bitpos: [0]; default: 0;
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* Configures the working mode of the AES accelerator. \\
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* 0: Typical AES\\
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* 1: DMA-AES\\
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*/
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uint32_t dma_enable:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} aes_dma_enable_reg_t;
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/** Type of block_mode register
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* Defines the block cipher mode
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*/
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typedef union {
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struct {
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/** block_mode : R/W; bitpos: [2:0]; default: 0;
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* Configures the block cipher mode of the AES accelerator operating under the DMA-AES
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* working mode. \\
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* 0: ECB (Electronic Code Block)\\
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* 1: CBC (Cipher Block Chaining)\\
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* 2: OFB (Output FeedBack)\\
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* 3: CTR (Counter)\\
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* 4: CFB8 (8-bit Cipher FeedBack)\\
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* 5: CFB128 (128-bit Cipher FeedBack)\\
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* 6: GCM\\
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* 7: Reserved\\
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*/
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uint32_t block_mode:3;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} aes_block_mode_reg_t;
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/** Type of block_num register
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* Block number configuration register
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*/
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typedef union {
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struct {
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/** block_num : R/W; bitpos: [31:0]; default: 0;
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* Represents the Block Number of plaintext or ciphertext when the AES accelerator
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* operates under the DMA-AES working mode. For details, see Section <a
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* href=sec:aes-block-number">link</a>. "
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*/
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uint32_t block_num:32;
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};
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uint32_t val;
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} aes_block_num_reg_t;
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/** Type of inc_sel register
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* Standard incrementing function register
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*/
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typedef union {
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struct {
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/** inc_sel : R/W; bitpos: [0]; default: 0;
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* Configures the Standard Incrementing Function for CTR block operation. \\
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* 0: INC<SUB>32</SUB>\\
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* 1: INC<SUB>128</SUB>\\
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*/
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uint32_t inc_sel:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} aes_inc_sel_reg_t;
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/** Type of dma_exit register
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* Operation exit controlling register
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*/
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typedef union {
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struct {
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/** dma_exit : WT; bitpos: [0]; default: 0;
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* Configures whether or not to exit AES operation. \\
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* 0: No effect\\
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* 1: Exit\\
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* Only valid for DMA-AES operation.
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*/
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uint32_t dma_exit:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} aes_dma_exit_reg_t;
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/** Type of rx_reset register
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* AES-DMA reset rx-fifo register
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*/
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typedef union {
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struct {
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/** rx_reset : WT; bitpos: [0]; default: 0;
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* Set this bit to reset rx_fifo under dma_aes working mode.
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*/
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uint32_t rx_reset:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} aes_rx_reset_reg_t;
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/** Type of tx_reset register
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* AES-DMA reset tx-fifo register
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*/
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typedef union {
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struct {
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/** tx_reset : WT; bitpos: [0]; default: 0;
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* Set this bit to reset tx_fifo under dma_aes working mode.
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*/
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uint32_t tx_reset:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} aes_tx_reset_reg_t;
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/** Group: Configuration register */
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/** Type of endian register
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* AES Endian configure register
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*/
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typedef union {
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struct {
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/** endian : R/W; bitpos: [5:0]; default: 0;
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* endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out
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* endian or out_stream endian
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*/
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uint32_t endian:6;
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uint32_t reserved_6:26;
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};
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uint32_t val;
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} aes_endian_reg_t;
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/** Type of aad_block_num register
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* Additional Authential Data block number register
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*/
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typedef union {
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struct {
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/** aad_block_num : R/W; bitpos: [31:0]; default: 0;
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* Those bits stores the number of AAD block.
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*/
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uint32_t aad_block_num:32;
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};
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uint32_t val;
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} aes_aad_block_num_reg_t;
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/** Type of remainder_bit_num register
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* AES remainder bit number register
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*/
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typedef union {
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struct {
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/** remainder_bit_num : R/W; bitpos: [6:0]; default: 0;
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* Those bits stores the number of remainder bit.
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*/
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uint32_t remainder_bit_num:7;
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uint32_t reserved_7:25;
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};
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uint32_t val;
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} aes_remainder_bit_num_reg_t;
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/** Type of pseudo register
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* AES PSEUDO function configure register
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*/
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typedef union {
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struct {
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/** pseudo_en : R/W; bitpos: [0]; default: 0;
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* This bit decides whether the pseudo round function is enable or not.
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*/
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uint32_t pseudo_en:1;
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/** pseudo_base : R/W; bitpos: [4:1]; default: 2;
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* Those bits decides the basic number of pseudo round number.
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*/
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uint32_t pseudo_base:4;
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/** pseudo_inc : R/W; bitpos: [6:5]; default: 2;
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* Those bits decides the increment number of pseudo round number
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*/
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uint32_t pseudo_inc:2;
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/** pseudo_rng_cnt : R/W; bitpos: [9:7]; default: 7;
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* Those bits decides the update frequency of the pseudo-key.
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*/
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uint32_t pseudo_rng_cnt:3;
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uint32_t reserved_10:22;
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};
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uint32_t val;
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} aes_pseudo_reg_t;
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/** Group: Status Register */
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/** Type of state register
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* Operation status register
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*/
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typedef union {
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struct {
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/** state : RO; bitpos: [1:0]; default: 0;
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* Represents the working status of the AES accelerator. \\
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* In Typical AES working mode:\\
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* 0: IDLE\\
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* 1: WORK\\
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* 2: No effect\\
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* 3: No effect\\
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* In DMA-AES working mode:\\
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* 0: IDLE\\
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* 1: WORK\\
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* 2: DONE\\
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* 3: No effect\\
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*/
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uint32_t state:2;
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uint32_t reserved_2:30;
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};
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uint32_t val;
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} aes_state_reg_t;
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/** Group: memory type */
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/** Group: Control/Status register */
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/** Type of continue register
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* AES continue register
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*/
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typedef union {
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struct {
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/** conti : WT; bitpos: [0]; default: 0;
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* Set this bit to continue GCM operation.
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*/
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uint32_t conti:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} aes_continue_reg_t;
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/** Group: Interrupt Registers */
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/** Type of int_clear register
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* DMA-AES interrupt clear register
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*/
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typedef union {
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struct {
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/** int_clear : WT; bitpos: [0]; default: 0;
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* Configures whether or not to clear AES interrupt. \\
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* 0: No effect \\
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* 1: Clear \\
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*/
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uint32_t int_clear:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} aes_int_clear_reg_t;
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/** Type of int_ena register
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* DMA-AES interrupt enable register
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*/
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typedef union {
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struct {
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/** int_ena : R/W; bitpos: [0]; default: 0;
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* Configures whether or not to enable AES interrupt.\\
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* 0: Disable\\
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* 1: Enable \\
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*/
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uint32_t int_ena:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} aes_int_ena_reg_t;
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/** Group: Version control register */
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/** Type of date register
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* AES version control register
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*/
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typedef union {
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struct {
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/** date : R/W; bitpos: [27:0]; default: 36774000;
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* This bits stores the version information of AES.
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*/
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uint32_t date:28;
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uint32_t reserved_28:4;
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};
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uint32_t val;
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} aes_date_reg_t;
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typedef struct {
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volatile aes_key_n_reg_t key_n[8];
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volatile aes_text_in_n_reg_t text_in_n[4];
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volatile aes_text_out_n_reg_t text_out_n[4];
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volatile aes_mode_reg_t mode;
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volatile aes_endian_reg_t endian;
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volatile aes_trigger_reg_t trigger;
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volatile aes_state_reg_t state;
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volatile uint32_t iv[4];
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volatile uint32_t h[4];
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volatile uint32_t j0[4];
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volatile uint32_t t0[4];
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volatile aes_dma_enable_reg_t dma_enable;
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volatile aes_block_mode_reg_t block_mode;
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volatile aes_block_num_reg_t block_num;
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volatile aes_inc_sel_reg_t inc_sel;
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volatile aes_aad_block_num_reg_t aad_block_num;
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volatile aes_remainder_bit_num_reg_t remainder_bit_num;
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volatile aes_continue_reg_t conti;
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volatile aes_int_clear_reg_t int_clear;
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volatile aes_int_ena_reg_t int_ena;
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volatile aes_date_reg_t date;
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volatile aes_dma_exit_reg_t dma_exit;
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uint32_t reserved_0bc;
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volatile aes_rx_reset_reg_t rx_reset;
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volatile aes_tx_reset_reg_t tx_reset;
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uint32_t reserved_0c8[2];
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volatile aes_pseudo_reg_t pseudo;
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} aes_dev_t;
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extern aes_dev_t AES;
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#ifndef __cplusplus
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_Static_assert(sizeof(aes_dev_t) == 0xd4, "Invalid size of aes_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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