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https://github.com/espressif/esp-idf
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2d37bfa126
- add lock for single read and continuous read APIs - update onetime read start singal delay for hardware limitation[*] - move adc_caps to soc_caps.h - update license dates [*] There is a hardware limitation. If the APB clock frequency is high, the step of this reg signal: ``onetime_start`` may not be captured by the ADC digital controller (when its clock frequency is too slow). A rough estimate for this step should be at least 3 ADC digital controller clock cycle.
32 lines
1.1 KiB
C
32 lines
1.1 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#define SOC_ADC1_DATA_INVERT_DEFAULT (0)
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#define SOC_ADC2_DATA_INVERT_DEFAULT (0)
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#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
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#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8)
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#define SOC_ADC_FSM_START_WAIT_DEFAULT (5)
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#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100)
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#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2)
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#define SOC_ADC_PWDET_CCT_DEFAULT (4)
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#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
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#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (1)
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