mirror of
https://github.com/espressif/esp-idf
synced 2025-03-29 19:00:12 -04:00
200f69e6eb
modem retention: Support esp32c6 wifi MAC and baseband sleep retention sleep_modem: wifi MAC modem wakeup protect in modem state before PMU trigger sleep enable request sleep modem: provide a interface to get whether the Modem power domain is allowed to power off during sleep add i2c_ana master header file to project auto beacon: release PMU's lock on root clock source (it is locked in the PLL) wifi receiving beacon frame in PMU modem state strongly depends on the BBPLL clock, PMU will forcibly lock the root clock source as PLL, when the root clock source of the software system is selected as PLL, we need to release the root clock source locking. When it is judged that the PLL is locked by PMU after wakeing up from the PMU modem state, switch the root clock source to the PLL in the sleep process (a critical section). auto beacon: fix the failure to receive broadcast/multicast frames in modem state When the multicast field in the beacon frame received in the PMU modem state is True, the PMU switches to the PMU active state (the PMU waits for the HP LDO to stabilize and then restores the MAC context) and starts to receive broadcast/multicast frames (Broadcast/Multicast frames will be sent after a minimum delay of 48 us after the beacon frame), because the PMU waits for the HP LDO to stabilize too long (~154 us), which will cause broadcast/multicast frame reception to be missed. auto beacon: select the PLL clock source as the REGDMA backup clock source when the PMU switches to ACTIVE from MODEM state update Digital Peripheral (M2A switch) REGDMA restore time parameter auto beacon: fix the issue that only channel 1 can connect to AP in modem state
105 lines
3.5 KiB
C
105 lines
3.5 KiB
C
/**
|
|
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
|
|
*
|
|
* SPDX-License-Identifier: Apache-2.0
|
|
*/
|
|
|
|
#pragma once
|
|
|
|
#include <stdint.h>
|
|
#include "soc/soc.h"
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0000)
|
|
#define I2C_ANA_MST_I2C0_BUSY (BIT(25))
|
|
#define I2C_ANA_MST_I2C0_BUSY_S 25
|
|
#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF
|
|
#define I2C_ANA_MST_I2C0_CTRL_S 0
|
|
|
|
#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0004)
|
|
#define I2C_ANA_MST_I2C1_BUSY (BIT(25))
|
|
#define I2C_ANA_MST_I2C1_BUSY_S 25
|
|
#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF
|
|
#define I2C_ANA_MST_I2C1_CTRL_S 0
|
|
|
|
#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x0008)
|
|
#define I2C_ANA_MST_I2C0_STATUS 0x000000FF
|
|
#define I2C_ANA_MST_I2C0_STATUS_S 24
|
|
#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF
|
|
#define I2C_ANA_MST_I2C0_CONF_S 0
|
|
|
|
#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x000C)
|
|
#define I2C_ANA_MST_I2C1_STATUS 0x000000FF
|
|
#define I2C_ANA_MST_I2C1_STATUS_S 24
|
|
#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF
|
|
#define I2C_ANA_MST_I2C1_CONF_S 0
|
|
|
|
#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x0010)
|
|
#define I2C_ANA_MST_BURST_CTRL 0xFFFFFFFF
|
|
#define I2C_ANA_MST_BURST_CTRL_S 0
|
|
|
|
#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x0014)
|
|
#define I2C_ANA_MST_BURST_TIMEOUT_CNT 0x00000FFF
|
|
#define I2C_ANA_MST_BURST_TIMEOUT_CNT_S 20
|
|
#define I2C_ANA_MST1_BURST_ERR_FLAG (BIT(2))
|
|
#define I2C_ANA_MST1_BURST_ERR_FLAG_S 2
|
|
#define I2C_ANA_MST0_BURST_ERR_FLAG (BIT(1))
|
|
#define I2C_ANA_MST0_BURST_ERR_FLAG_S 1
|
|
#define I2C_ANA_MST_BURST_DONE (BIT(0))
|
|
#define I2C_ANA_MST_BURST_DONE_S 0
|
|
|
|
#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x0018)
|
|
#define I2C_ANA_MST_ANA_STATUS0 0x000000FF
|
|
#define I2C_ANA_MST_ANA_STATUS0_S 24
|
|
#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFF
|
|
#define I2C_ANA_MST_ANA_CONF0_S 0
|
|
|
|
#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x001C)
|
|
#define I2C_ANA_MST_ANA_STATUS1 0x000000FF
|
|
#define I2C_ANA_MST_ANA_STATUS1_S 24
|
|
#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF
|
|
#define I2C_ANA_MST_ANA_CONF1_S 0
|
|
|
|
#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x0020)
|
|
#define I2C_ANA_MST_ANA_STATUS2 0x000000FF
|
|
#define I2C_ANA_MST_ANA_STATUS2_S 24
|
|
#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFF
|
|
#define I2C_ANA_MST_ANA_CONF2_S 0
|
|
|
|
#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x0024)
|
|
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F
|
|
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6
|
|
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F
|
|
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0
|
|
|
|
#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x0028)
|
|
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F
|
|
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6
|
|
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F
|
|
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0
|
|
|
|
#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x002C)
|
|
#define I2C_ANA_MST_ARBITER_DIS (BIT(11))
|
|
#define I2C_ANA_MST_ARBITER_DIS_S 11
|
|
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F
|
|
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6
|
|
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F
|
|
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0
|
|
|
|
#define I2C_ANA_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x0030)
|
|
#define I2C_ANA_MST_NOUSE 0xFFFFFFFF
|
|
#define I2C_ANA_MST_NOUSE_S 0
|
|
|
|
#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x0034)
|
|
#define I2C_ANA_MST_CLK_EN (BIT(28))
|
|
#define I2C_ANA_MST_CLK_EN_S 28
|
|
#define I2C_ANA_MST_DATE 0x0FFFFFFF
|
|
#define I2C_ANA_MST_DATE_S 0
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|