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4230acb971
This commit adds a new example which demonstrates how the ULP RISC-V co-processor handles interrupts.
10 lines
282 B
Plaintext
10 lines
282 B
Plaintext
# Enable ULP
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CONFIG_ULP_COPROC_ENABLED=y
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CONFIG_ULP_COPROC_TYPE_RISCV=y
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CONFIG_ULP_COPROC_RESERVE_MEM=4096
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# Set log level to Warning to produce clean output
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CONFIG_BOOTLOADER_LOG_LEVEL_WARN=y
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CONFIG_BOOTLOADER_LOG_LEVEL=2
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CONFIG_LOG_DEFAULT_LEVEL_WARN=y
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CONFIG_LOG_DEFAULT_LEVEL=2
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