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4359d5985e
Since commit 94250e4, EXT0 wakeup mechanism, when wakeup level was set
to 0, started waking up chip immediately after entering deep sleep.
This failure was triggered in that commit by a change of
RTC_CNTL_MIN_SLP_VAL (i.e. minimum time in sleep mode until wakeup
can happen) from 128 cycles to 2 cycles.
The reason for this behaviour is related to the way input enable (IE)
signal going into an RTC pad is obtained:
PAD_IE = (SLP_SEL) ? SLP_IE & CHIP_SLEEP : IE,
where SLP_IE, SLP_SEL, and IE are bits of an RTC_IO register related
to the given pad. CHIP_SLEEP is the signal indicating that chip has
entered sleep mode.
The code in prepare_ext{0,1}_wakeup did not enable IE, but did enable
SLP_SEL and SLP_IE. This meant that until CHIP_SLEEP went high, PAD_IE
was 0, hence the input from the pad read 0 even if external signal
was 1. CHIP_SLEEP went high on the 2nd cycle of sleep. So when
RTC_CNTL_MIN_SLP_VAL was set to 2, the input signal from the pad was
latched as 0 at the moment when CHIP_SLEEP went high, causing EXT0
wakeup with level 0 to trigger.
This commit changes the way PAD_IE is enabled: SLP_SEL and SLP_IE are
no longer used, and IE is set to 1. If EXT0 wakeup is used, RTC_IO is
not powered down, so IE signal stays 1 both before CHIP_SLEEP goes
high and after. If EXT1 wakeup is used, RTC_IO may be powered down.
However prepare_ext1_wakeup enables Hold on the pad, locking states
of all the control signals, including IE.
Closes https://github.com/espressif/esp-idf/issues/1931
Closes https://github.com/espressif/esp-idf/issues/2043