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https://github.com/espressif/esp-idf
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2c2a62e323
- Support SOC ROOT clock source switch - Support CPU frequency change - Support RTC SLOW clock source switch - Support RTC SLOW clock + RC FAST calibration Remove FPGA build for esp32h2
36 lines
955 B
C
36 lines
955 B
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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/**
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* @file regi2c_bbpll.h
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* @brief Register definitions for digital PLL (BBPLL)
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*
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* This file lists register fields of BBPLL, located on an internal configuration
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* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
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* rtc_clk_cpu_freq_set function in rtc_clk.c.
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*/
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#define I2C_BBPLL 0x66
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#define I2C_BBPLL_HOSTID 0
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#define I2C_BBPLL_OC_REF_DIV 2
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#define I2C_BBPLL_OC_REF_DIV_MSB 3
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#define I2C_BBPLL_OC_REF_DIV_LSB 0
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#define I2C_BBPLL_OC_DIV 3
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#define I2C_BBPLL_OC_DIV_MSB 5
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#define I2C_BBPLL_OC_DIV_LSB 0
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#define I2C_BBPLL_OC_DHREF_SEL 5
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#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
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#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
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#define I2C_BBPLL_OC_DLREF_SEL 5
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#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
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#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
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