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esp-idf/components/soc/esp32c2/include
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Omar Chebib 5bcd9b2db8 G0: RISC-V targets have now an independent G0 layer 
G0 doesn't depend on any G1+ layer for RISC-V based targets
2022-06-14 15:00:53 +08:00
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soc
G0: RISC-V targets have now an independent G0 layer
2022-06-14 15:00:53 +08:00