mirror of
https://github.com/espressif/esp-idf
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182e937c5a
- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32c6
38 lines
921 B
C
38 lines
921 B
C
/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "esp_bit_defs.h"
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/* Analog function control register */
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#define I2C_MST_ANA_CONF0_REG 0x600AF818
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#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
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#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
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#define I2C_MST_BBPLL_CAL_DONE (BIT(24))
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#define ANA_CONFIG_REG 0x600AF81C
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#define ANA_CONFIG_S (8)
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#define ANA_CONFIG_M (0x3FF)
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#define ANA_I2C_SAR_FORCE_PD BIT(18)
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#define ANA_I2C_BBPLL_M BIT(17) /* Clear to enable BBPLL */
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#define ANA_CONFIG2_REG 0x600AF820
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#define ANA_CONFIG2_M BIT(18)
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#define ANA_I2C_SAR_FORCE_PU BIT(16)
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/**
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* Restore regi2c analog calibration related configuration registers.
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* This is a workaround, and is fixed on later chips
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*/
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#define REGI2C_ANA_CALI_PD_WORKAROUND 1
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#define REGI2C_ANA_CALI_BYTE_NUM 8
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