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https://github.com/espressif/esp-idf
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f38f77a7fc
This configuration bit is required for ADC operation as well and hence should not be cleared in the RNG API sequence. Ideally, the ADC driver should take care of initializing this bit but still the RNG layer change is required because of interleaved API usage scenario described in following linked issue. Closes https://github.com/espressif/esp-idf/issues/14124 Closes https://github.com/espressif/esp-idf/issues/14280
97 lines
4.0 KiB
C
97 lines
4.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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#include "bootloader_random.h"
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#include "soc/soc.h"
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#include "soc/pcr_reg.h"
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#include "soc/apb_saradc_reg.h"
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#include "soc/pmu_reg.h"
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#include "hal/regi2c_ctrl.h"
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#include "soc/regi2c_saradc.h"
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#include "esp_log.h"
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static const uint32_t SAR2_CHANNEL = 9;
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static const uint32_t PATTERN_BIT_WIDTH = 6;
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static const uint32_t SAR1_ATTEN = 1;
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static const uint32_t SAR2_ATTEN = 1;
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void bootloader_random_enable(void)
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{
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// pull SAR ADC out of reset
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REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
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REG_CLR_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_RST_EN);
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// enable SAR ADC APB clock
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REG_SET_BIT(PCR_SARADC_CONF_REG, PCR_SARADC_REG_CLK_EN);
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// enable ADC_CTRL_CLK (SAR ADC function clock)
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REG_SET_BIT(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_EN);
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// select XTAL clock (40 MHz) source for ADC_CTRL_CLK
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REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_SEL, 0);
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// set the clock divider for ADC_CTRL_CLK to default value (in case it has been changed)
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REG_SET_FIELD(PCR_SARADC_CLKM_CONF_REG, PCR_SARADC_CLKM_DIV_NUM, 0);
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// some ADC sensor registers are in power group PERIF_I2C and need to be enabled via PMU
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SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_PERIF_I2C_RSTB);
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SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
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// Config ADC circuit (Analog part) with I2C(HOST ID 0x69) and chose internal voltage as sampling source
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR , 2);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR , 1);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 1);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 1);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x08);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x66);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x08);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x66);
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// create patterns and set them in pattern table
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uint32_t pattern_one = (SAR2_CHANNEL << 2) | SAR2_ATTEN; // we want channel 9 with max attenuation
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uint32_t pattern_two = (SAR2_CHANNEL << 2) | SAR1_ATTEN; // we want channel 9 with max attenuation
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uint32_t pattern_table = 0 | (pattern_two << 3 * PATTERN_BIT_WIDTH) | pattern_one << 2 * PATTERN_BIT_WIDTH;
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REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, pattern_table);
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// set pattern length to 2 (APB_SARADC_SAR_PATT_LEN counts from 0)
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REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_PATT_LEN, 1);
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// Same as in C3
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REG_SET_FIELD(APB_SARADC_CTRL_REG, APB_SARADC_SARADC_SAR_CLK_DIV, 15);
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// set timer expiry (timer is ADC_CTRL_CLK)
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REG_SET_FIELD(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_TARGET, 200);
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// enable timer
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REG_SET_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
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}
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void bootloader_random_disable(void)
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{
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// disable timer
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REG_CLR_BIT(APB_SARADC_CTRL2_REG, APB_SARADC_SARADC_TIMER_EN);
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// Write reset value of this register
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REG_WRITE(APB_SARADC_SAR_PATT_TAB1_REG, 0xFFFFFF);
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// Revert ADC I2C configuration and initial voltage source setting
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, 0x60);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, 0x0);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, 0x60);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, 0x0);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_DTEST_RTC_ADDR, 0);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC_ENT_RTC_ADDR, 0);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC1_ENCAL_REF_ADDR, 0);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SARADC2_ENCAL_REF_ADDR, 0);
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// disable ADC_CTRL_CLK (SAR ADC function clock)
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REG_WRITE(PCR_SARADC_CLKM_CONF_REG, 0x00404000);
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// Set PCR_SARADC_CONF_REG to initial state
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REG_WRITE(PCR_SARADC_CONF_REG, 0x5);
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}
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