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https://github.com/espressif/esp-idf
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234 lines
9.8 KiB
C
234 lines
9.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/timer_periph.h"
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const timer_group_signal_conn_t timer_group_periph_signals = {
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.groups = {
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[0] = {
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.module = PERIPH_TIMG0_MODULE,
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.timer_irq_id = {
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[0] = ETS_TG0_T0_INTR_SOURCE,
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[1] = ETS_TG0_T1_INTR_SOURCE,
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}
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},
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[1] = {
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.module = PERIPH_TIMG1_MODULE,
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.timer_irq_id = {
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[0] = ETS_TG1_T0_INTR_SOURCE,
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[1] = ETS_TG1_T1_INTR_SOURCE,
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}
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}
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}
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};
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/* Registers in retention context:
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* TIMG_T0CONFIG_REG
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* TIMG_T0ALARMLO_REG
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* TIMG_T0ALARMHI_REG
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* TIMG_T0LOADLO_REG
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* TIMG_T0LOADHI_REG
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* TIMG_INT_ENA_TIMERS_REG
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* TIMG_REGCLK_REG
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*/
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#define TG0_TIMER0_RETENTION_REGS_BASE (REG_TIMG_BASE(0))
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#define TG1_TIMER0_RETENTION_REGS_BASE (REG_TIMG_BASE(1))
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#define TG_TIMER0_RETENTION_REGS_CNT 7
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static const uint32_t tg_timer0_regs_map[4] = {0x100000f1, 0x80000000, 0x0, 0x0};
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/* Registers in retention context:
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* TIMG_T1CONFIG_REG
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* TIMG_T1ALARMLO_REG
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* TIMG_T1ALARMHI_REG
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* TIMG_T1LOADLO_REG
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* TIMG_T1LOADHI_REG
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* TIMG_INT_ENA_TIMERS_REG
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* TIMG_REGCLK_REG
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*/
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#define TG0_TIMER1_RETENTION_REGS_BASE (REG_TIMG_BASE(0) + 0x24)
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#define TG1_TIMER1_RETENTION_REGS_BASE (REG_TIMG_BASE(1) + 0x24)
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#define TG_TIMER1_RETENTION_REGS_CNT 7
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static const uint32_t tg_timer1_regs_map[4] = {0x800f1, 0x400000, 0x0, 0x0};
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const regdma_entries_config_t tg0_timer0_regdma_entries[] = {
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// backup stage: trigger a soft capture
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[0] = {
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.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x00),
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TIMG_T0UPDATE_REG(0), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1),
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.owner = ENTRY(0)
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},
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// backup stage: wait for the capture done
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[1] = {
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.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x01),
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TIMG_T0UPDATE_REG(0), 0x0, TIMG_T0_UPDATE_M, 0, 1),
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.owner = ENTRY(0)
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},
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// backup stage: save the captured counter value
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// restore stage: store the captured counter value to the loader register
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[2] = {
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.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x02),
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TIMG_T0LO_REG(0), TIMG_T0LOADLO_REG(0), 2, 0, 0),
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.owner = ENTRY(0)
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},
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// restore stage: trigger a soft reload, so the timer can continue from where it was backed up
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[3] = {
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.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x03),
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TIMG_T0LOAD_REG(0), 0x1, TIMG_T0_LOAD_M, 1, 0),
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.owner = ENTRY(0)
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},
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// backup stage: save other configuration and status registers
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// restore stage: restore the configuration and status registers
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[4] = {
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.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x04),
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TG0_TIMER0_RETENTION_REGS_BASE, TG0_TIMER0_RETENTION_REGS_BASE,
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TG_TIMER0_RETENTION_REGS_CNT, 0, 0,
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tg_timer0_regs_map[0], tg_timer0_regs_map[1],
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tg_timer0_regs_map[2], tg_timer0_regs_map[3]),
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.owner = ENTRY(0)
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},
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};
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const regdma_entries_config_t tg0_timer1_regdma_entries[] = {
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// backup stage: trigger a soft capture
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[0] = {
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.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x05),
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TIMG_T1UPDATE_REG(0), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1),
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.owner = ENTRY(0)
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},
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// backup stage: wait for the capture done
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[1] = {
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.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG0_TIMER_LINK(0x06),
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TIMG_T1UPDATE_REG(0), 0x0, TIMG_T1_UPDATE_M, 0, 1),
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.owner = ENTRY(0)
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},
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// backup stage: save the captured counter value
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// restore stage: store the captured counter value to the loader register
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[2] = {
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.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG0_TIMER_LINK(0x07),
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TIMG_T1LO_REG(0), TIMG_T1LOADLO_REG(0), 2, 0, 0),
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.owner = ENTRY(0)
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},
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// restore stage: trigger a soft reload, so the timer can continue from where it was backed up
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[3] = {
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.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG0_TIMER_LINK(0x08),
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TIMG_T1LOAD_REG(0), 0x1, TIMG_T1_LOAD_M, 1, 0),
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.owner = ENTRY(0)
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},
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// backup stage: save other configuration and status registers
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// restore stage: restore the configuration and status registers
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[4] = {
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.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG0_TIMER_LINK(0x09),
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TG0_TIMER1_RETENTION_REGS_BASE, TG0_TIMER1_RETENTION_REGS_BASE,
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TG_TIMER1_RETENTION_REGS_CNT, 0, 0,
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tg_timer1_regs_map[0], tg_timer1_regs_map[1],
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tg_timer1_regs_map[2], tg_timer1_regs_map[3]),
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.owner = ENTRY(0)
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},
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};
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const regdma_entries_config_t tg1_timer0_regdma_entries[] = {
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// backup stage: trigger a soft capture
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[0] = {
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.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x00),
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TIMG_T0UPDATE_REG(1), TIMG_T0_UPDATE, TIMG_T0_UPDATE_M, 0, 1),
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.owner = ENTRY(0)
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},
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// backup stage: wait for the capture done
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[1] = {
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.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x01),
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TIMG_T0UPDATE_REG(1), 0x0, TIMG_T0_UPDATE_M, 0, 1),
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.owner = ENTRY(0)
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},
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// backup stage: save the captured counter value
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// restore stage: store the captured counter value to the loader register
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[2] = {
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.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x02),
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TIMG_T0LO_REG(1), TIMG_T0LOADLO_REG(1), 2, 0, 0),
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.owner = ENTRY(0)
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},
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// restore stage: trigger a soft reload, so the timer can continue from where it was backed up
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[3] = {
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.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x03),
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TIMG_T0LOAD_REG(1), 0x1, TIMG_T0_LOAD_M, 1, 0),
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.owner = ENTRY(0)
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},
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// backup stage: save other configuration and status registers
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// restore stage: restore the configuration and status registers
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[4] = {
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.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x04),
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TG1_TIMER0_RETENTION_REGS_BASE, TG1_TIMER0_RETENTION_REGS_BASE,
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TG_TIMER0_RETENTION_REGS_CNT, 0, 0,
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tg_timer0_regs_map[0], tg_timer0_regs_map[1],
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tg_timer0_regs_map[2], tg_timer0_regs_map[3]),
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.owner = ENTRY(0)
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},
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};
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const regdma_entries_config_t tg1_timer1_regdma_entries[] = {
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// backup stage: trigger a soft capture
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[0] = {
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.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x05),
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TIMG_T1UPDATE_REG(1), TIMG_T1_UPDATE, TIMG_T1_UPDATE_M, 0, 1),
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.owner = ENTRY(0)
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},
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// backup stage: wait for the capture done
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[1] = {
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.config = REGDMA_LINK_WAIT_INIT(REGDMA_TG1_TIMER_LINK(0x06),
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TIMG_T1UPDATE_REG(1), 0x0, TIMG_T1_UPDATE_M, 0, 1),
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.owner = ENTRY(0)
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},
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// backup stage: save the captured counter value
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// restore stage: store the captured counter value to the loader register
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[2] = {
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.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_TG1_TIMER_LINK(0x07),
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TIMG_T1LO_REG(1), TIMG_T1LOADLO_REG(1), 2, 0, 0),
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.owner = ENTRY(0)
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},
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// restore stage: trigger a soft reload, so the timer can continue from where it was backed up
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[3] = {
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.config = REGDMA_LINK_WRITE_INIT(REGDMA_TG1_TIMER_LINK(0x08),
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TIMG_T1LOAD_REG(1), 0x1, TIMG_T1_LOAD_M, 1, 0),
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.owner = ENTRY(0)
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},
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// backup stage: save other configuration and status registers
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// restore stage: restore the configuration and status registers
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[4] = {
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.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_TG1_TIMER_LINK(0x09),
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TG1_TIMER1_RETENTION_REGS_BASE, TG1_TIMER1_RETENTION_REGS_BASE,
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TG_TIMER1_RETENTION_REGS_CNT, 0, 0,
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tg_timer1_regs_map[0], tg_timer1_regs_map[1],
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tg_timer1_regs_map[2], tg_timer1_regs_map[3]),
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.owner = ENTRY(0)
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},
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};
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const tg_timer_reg_retention_info_t tg_timer_reg_retention_info[SOC_TIMER_GROUPS][SOC_TIMER_GROUP_TIMERS_PER_GROUP] = {
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[0] = {
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[0] = {
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.module = SLEEP_RETENTION_MODULE_TG0_TIMER0,
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.regdma_entry_array = tg0_timer0_regdma_entries,
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.array_size = ARRAY_SIZE(tg0_timer0_regdma_entries)
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},
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[1] = {
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.module = SLEEP_RETENTION_MODULE_TG0_TIMER1,
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.regdma_entry_array = tg0_timer1_regdma_entries,
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.array_size = ARRAY_SIZE(tg0_timer1_regdma_entries)
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},
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},
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[1] = {
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[0] = {
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.module = SLEEP_RETENTION_MODULE_TG1_TIMER0,
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.regdma_entry_array = tg1_timer0_regdma_entries,
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.array_size = ARRAY_SIZE(tg1_timer0_regdma_entries)
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},
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[1] = {
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.module = SLEEP_RETENTION_MODULE_TG1_TIMER1,
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.regdma_entry_array = tg1_timer1_regdma_entries,
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.array_size = ARRAY_SIZE(tg1_timer1_regdma_entries)
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},
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},
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};
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