mirror of
https://github.com/espressif/esp-idf
synced 2025-03-10 01:29:21 -04:00
d0f05cd690
ERROR: A fatal error occurred: Segment loaded at 0x3c01d150 lands in same 64KB flash mapping as segment loaded at 0x3c018020. Can't generate binary. Suggest changing linker script or ELF to merge sections. Seems binary generator does not handle well empty sections that contains aligning only. I did not investigate much but this change helped.
91 lines
3.2 KiB
Plaintext
91 lines
3.2 KiB
Plaintext
/*
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* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "sdkconfig.h"
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/* CPU instruction prefetch padding size for flash mmap scenario */
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#define _esp_flash_mmap_prefetch_pad_size 16
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/*
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* PMP region granularity size
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* Software may determine the PMP granularity by writing zero to pmp0cfg, then writing all ones
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* to pmpaddr0, then reading back pmpaddr0. If G is the index of the least-significant bit set,
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* the PMP granularity is 2^G+2 bytes.
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*/
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#ifdef CONFIG_SOC_CPU_PMP_REGION_GRANULARITY
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#define _esp_pmp_align_size CONFIG_SOC_CPU_PMP_REGION_GRANULARITY
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#else
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#define _esp_pmp_align_size 0
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#endif
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/* CPU instruction prefetch padding size for memory protection scenario */
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#ifdef CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE
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#define _esp_memprot_prefetch_pad_size CONFIG_SOC_MEMPROT_CPU_PREFETCH_PAD_SIZE
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#else
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#define _esp_memprot_prefetch_pad_size 0
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#endif
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/* Memory alignment size for PMS */
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#ifdef CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE
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#define _esp_memprot_align_size CONFIG_SOC_MEMPROT_MEM_ALIGN_SIZE
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#else
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#define _esp_memprot_align_size 0
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#endif
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#if CONFIG_APP_BUILD_TYPE_RAM
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#define _esp_mmu_page_size 0
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#else
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#define _esp_mmu_page_size CONFIG_MMU_PAGE_SIZE
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#endif
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#define ALIGN_UP(SIZE, AL) (((SIZE) + (AL - 1)) & ~(AL - 1))
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#if CONFIG_SOC_RTC_MEM_SUPPORTED
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#if CONFIG_BOOTLOADER_RESERVE_RTC_MEM
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#ifdef CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
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#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE + CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC_SIZE)
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#else
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#define ESP_BOOTLOADER_RESERVE_RTC (CONFIG_BOOTLOADER_RESERVE_RTC_SIZE)
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#endif // not CONFIG_BOOTLOADER_CUSTOM_RESERVE_RTC
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#else
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#define ESP_BOOTLOADER_RESERVE_RTC 0
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#endif // not CONFIG_BOOTLOADER_RESERVE_RTC_MEM
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/* rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). For rtc_timer_data_in_rtc_mem section. */
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#define RTC_TIMER_RESERVE_RTC (24)
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#if CONFIG_IDF_TARGET_ESP32
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#define RESERVE_RTC_MEM (RTC_TIMER_RESERVE_RTC)
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#elif CONFIG_ESP_ROM_HAS_LP_ROM && CONFIG_ULP_COPROC_ENABLED
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/* RTC Reserved is placed before ULP memory, expand it to make sure the ULP start address
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has the required alignment */
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#define ULP_ALIGNMENT_REQ_BYTES 256
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#define RESERVE_RTC_MEM ALIGN_UP(ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC, ULP_ALIGNMENT_REQ_BYTES)
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#else
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#define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC)
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#endif
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#endif // SOC_RTC_MEM_SUPPORTED
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#define QUOTED_STRING(STRING) #STRING
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#define ASSERT_SECTIONS_GAP(PREV_SECTION, NEXT_SECTION) \
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ASSERT((ADDR(NEXT_SECTION) == ADDR(PREV_SECTION) + SIZEOF(PREV_SECTION)), \
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QUOTED_STRING(The gap between PREV_SECTION and NEXT_SECTION must not exist to produce the final bin image.))
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#define ALIGNED_SYMBOL(X, SYMBOL) \
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\n . = ALIGN(X); \
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\n SYMBOL = ABSOLUTE(.);
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#if CONFIG_COMPILER_CXX_EXCEPTIONS || CONFIG_ESP_SYSTEM_USE_EH_FRAME
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#define EH_FRAME_LINKING_ENABLED 1
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#endif
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#if EH_FRAME_LINKING_ENABLED
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#define SECTION_AFTER_FLASH_RODATA .eh_frame_hdr
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#else
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#define SECTION_AFTER_FLASH_RODATA .flash.tdata
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#endif
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