mirror of
https://github.com/espressif/esp-idf
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124 lines
4.5 KiB
C
124 lines
4.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stddef.h>
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#include "soc/spi_periph.h"
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/*
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Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
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*/
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const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
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{
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// MSPI on P4 has dedicated iomux pins
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}, {
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.spiclk_out = SPI2_CK_PAD_OUT_IDX,
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.spiclk_in = SPI2_CK_PAD_IN_IDX,
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.spid_out = SPI2_D_PAD_OUT_IDX,
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.spiq_out = SPI2_Q_PAD_OUT_IDX,
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.spiwp_out = SPI2_WP_PAD_OUT_IDX,
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.spihd_out = SPI2_HOLD_PAD_OUT_IDX,
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.spid4_out = SPI2_IO4_PAD_OUT_IDX,
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.spid5_out = SPI2_IO5_PAD_OUT_IDX,
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.spid6_out = SPI2_IO6_PAD_OUT_IDX,
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.spid7_out = SPI2_IO7_PAD_OUT_IDX,
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.spid_in = SPI2_D_PAD_IN_IDX,
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.spiq_in = SPI2_Q_PAD_IN_IDX,
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.spiwp_in = SPI2_WP_PAD_IN_IDX,
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.spihd_in = SPI2_HOLD_PAD_IN_IDX,
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.spid4_in = SPI2_IO4_PAD_IN_IDX,
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.spid5_in = SPI2_IO5_PAD_IN_IDX,
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.spid6_in = SPI2_IO6_PAD_IN_IDX,
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.spid7_in = SPI2_IO7_PAD_IN_IDX,
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.spics_out = {SPI2_CS_PAD_OUT_IDX, SPI2_CS1_PAD_OUT_IDX, SPI2_CS2_PAD_OUT_IDX, SPI2_CS3_PAD_OUT_IDX, SPI2_CS4_PAD_OUT_IDX, SPI2_CS5_PAD_OUT_IDX},
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.spics_in = SPI2_CS_PAD_IN_IDX,
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.spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
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.spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,
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.spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO,
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.spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP,
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.spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD,
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.spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
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.irq = ETS_SPI2_INTR_SOURCE,
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.irq_dma = -1,
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.hw = &GPSPI2,
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.func = SPI2_FUNC_NUM,
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}, {
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.spiclk_out = SPI3_CK_PAD_OUT_IDX,
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.spiclk_in = SPI3_CK_PAD_IN_IDX,
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.spid_out = SPI3_D_PAD_OUT_IDX,
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.spiq_out = SPI3_QO_PAD_OUT_IDX,
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.spiwp_out = SPI3_WP_PAD_OUT_IDX,
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.spihd_out = SPI3_HOLD_PAD_OUT_IDX,
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.spid_in = SPI3_D_PAD_IN_IDX,
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.spiq_in = SPI3_Q_PAD_IN_IDX,
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.spiwp_in = SPI3_WP_PAD_IN_IDX,
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.spihd_in = SPI3_HOLD_PAD_IN_IDX,
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.spics_out = {SPI3_CS_PAD_OUT_IDX, SPI3_CS1_PAD_OUT_IDX, SPI3_CS2_PAD_OUT_IDX},
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.spics_in = SPI3_CS_PAD_IN_IDX,
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//SPI3 doesn't have iomux pins
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.spiclk_iomux_pin = -1,
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.spid_iomux_pin = -1,
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.spiq_iomux_pin = -1,
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.spiwp_iomux_pin = -1,
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.spihd_iomux_pin = -1,
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.spics0_iomux_pin = -1,
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.irq = ETS_SPI3_INTR_SOURCE,
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.irq_dma = -1,
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.hw = &GPSPI3,
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.func = -1,
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}
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};
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/**
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* Backup registers in Light sleep: (total cnt 29)
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*
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* cmd
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* addr
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* ctrl
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* clock
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* user
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* user1
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* user2
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* ms_dlen
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* misc
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* dma_conf
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* dma_int_ena
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* data_buf[0-15] // slave driver only
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* slave
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* slave1
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*/
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#define SPI_RETENTION_REGS_CNT 29
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static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0};
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#define SPI_REG_RETENTION_ENTRIES(num) { \
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[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \
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REG_SPI_BASE(num), REG_SPI_BASE(num), \
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SPI_RETENTION_REGS_CNT, 0, 0, \
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spi_regs_map[0], spi_regs_map[1], \
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spi_regs_map[2], spi_regs_map[3]), \
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.owner = ENTRY(0) }, \
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/* Additional interrupt setting is required by idf SPI drivers after register recovered */ \
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[1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \
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SPI_DMA_INT_SET_REG(num), \
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SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \
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UINT32_MAX, 1, 0), \
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.owner = ENTRY(0) }, \
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}
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static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2); // '2' for GPSPI2
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static const regdma_entries_config_t spi3_regs_retention[] = SPI_REG_RETENTION_ENTRIES(3);
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const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = { // '-1' to except mspi
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{
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.module_id = SLEEP_RETENTION_MODULE_GPSPI2,
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.entry_array = spi2_regs_retention,
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.array_size = ARRAY_SIZE(spi2_regs_retention),
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},
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{
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.module_id = SLEEP_RETENTION_MODULE_GPSPI3,
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.entry_array = spi3_regs_retention,
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.array_size = ARRAY_SIZE(spi3_regs_retention),
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},
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};
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