mirror of
https://github.com/espressif/esp-idf
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178 lines
5.2 KiB
C
178 lines
5.2 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** SHA_MODE_REG register
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* Configures SHA algorithm
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*/
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#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0)
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/** SHA_MODE : R/W; bitpos: [2:0]; default: 0;
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* Configures the SHA algorithm. \\
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* 0: SHA-1\\
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* 1: SHA-224\\
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* 2: SHA-256\\
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*/
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#define SHA_MODE 0x00000007U
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#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S)
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#define SHA_MODE_V 0x00000007U
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#define SHA_MODE_S 0
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/** SHA_T_STRING_REG register
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* SHA 512/t configuration register 0.
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*/
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#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4)
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/** SHA_T_STRING : R/W; bitpos: [31:0]; default: 0;
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* Sha t_string (used if and only if mode == SHA_512/t).
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*/
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#define SHA_T_STRING 0xFFFFFFFFU
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#define SHA_T_STRING_M (SHA_T_STRING_V << SHA_T_STRING_S)
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#define SHA_T_STRING_V 0xFFFFFFFFU
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#define SHA_T_STRING_S 0
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/** SHA_T_LENGTH_REG register
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* SHA 512/t configuration register 1.
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*/
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#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8)
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/** SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0;
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* Sha t_length (used if and only if mode == SHA_512/t).
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*/
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#define SHA_T_LENGTH 0x0000003FU
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#define SHA_T_LENGTH_M (SHA_T_LENGTH_V << SHA_T_LENGTH_S)
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#define SHA_T_LENGTH_V 0x0000003FU
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#define SHA_T_LENGTH_S 0
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/** SHA_DMA_BLOCK_NUM_REG register
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* Block number register (only effective for DMA-SHA)
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*/
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#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc)
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/** SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0;
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* Configures the DMA-SHA block number.
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*/
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#define SHA_DMA_BLOCK_NUM 0x0000003FU
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#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S)
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#define SHA_DMA_BLOCK_NUM_V 0x0000003FU
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#define SHA_DMA_BLOCK_NUM_S 0
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/** SHA_START_REG register
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* Starts the SHA accelerator for Typical SHA operation
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*/
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#define SHA_START_REG (DR_REG_SHA_BASE + 0x10)
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/** SHA_START : RO; bitpos: [31:1]; default: 0;
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* Write 1 to start Typical SHA calculation.
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*/
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#define SHA_START 0x7FFFFFFFU
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#define SHA_START_M (SHA_START_V << SHA_START_S)
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#define SHA_START_V 0x7FFFFFFFU
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#define SHA_START_S 1
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/** SHA_CONTINUE_REG register
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* Continues SHA operation (only effective in Typical SHA mode)
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*/
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#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14)
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/** SHA_CONTINUE : RO; bitpos: [31:1]; default: 0;
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* Write 1 to continue Typical SHA calculation.
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*/
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#define SHA_CONTINUE 0x7FFFFFFFU
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#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S)
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#define SHA_CONTINUE_V 0x7FFFFFFFU
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#define SHA_CONTINUE_S 1
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/** SHA_BUSY_REG register
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* Represents if SHA Accelerator is busy or not
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*/
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#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18)
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/** SHA_BUSY_STATE : RO; bitpos: [0]; default: 0;
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* Represents the states of SHA accelerator. \\
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* 0: idle\\
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* 1: busy\\
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*/
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#define SHA_BUSY_STATE (BIT(0))
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#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S)
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#define SHA_BUSY_STATE_V 0x00000001U
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#define SHA_BUSY_STATE_S 0
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/** SHA_DMA_START_REG register
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* Starts the SHA accelerator for DMA-SHA operation
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*/
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#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c)
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/** SHA_DMA_START : WO; bitpos: [0]; default: 0;
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* Write 1 to start DMA-SHA calculation.
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*/
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#define SHA_DMA_START (BIT(0))
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#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S)
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#define SHA_DMA_START_V 0x00000001U
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#define SHA_DMA_START_S 0
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/** SHA_DMA_CONTINUE_REG register
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* Continues SHA operation (only effective in DMA-SHA mode)
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*/
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#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20)
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/** SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0;
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* Write 1 to continue DMA-SHA calculation.
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*/
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#define SHA_DMA_CONTINUE (BIT(0))
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#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S)
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#define SHA_DMA_CONTINUE_V 0x00000001U
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#define SHA_DMA_CONTINUE_S 0
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/** SHA_CLEAR_IRQ_REG register
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* DMA-SHA interrupt clear register
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*/
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#define SHA_CLEAR_IRQ_REG (DR_REG_SHA_BASE + 0x24)
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/** SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0;
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* Write 1 to clear DMA-SHA interrupt.
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*/
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#define SHA_CLEAR_INTERRUPT (BIT(0))
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#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S)
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#define SHA_CLEAR_INTERRUPT_V 0x00000001U
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#define SHA_CLEAR_INTERRUPT_S 0
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/** SHA_IRQ_ENA_REG register
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* DMA-SHA interrupt enable register
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*/
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#define SHA_IRQ_ENA_REG (DR_REG_SHA_BASE + 0x28)
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/** SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0;
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* Write 1 to enable DMA-SHA interrupt.
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*/
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#define SHA_INTERRUPT_ENA (BIT(0))
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#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S)
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#define SHA_INTERRUPT_ENA_V 0x00000001U
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#define SHA_INTERRUPT_ENA_S 0
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/** SHA_DATE_REG register
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* Version control register
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*/
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#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c)
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/** SHA_DATE : R/W; bitpos: [29:0]; default: 538972713;
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* Version control register.
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*/
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#define SHA_DATE 0x3FFFFFFFU
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#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S)
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#define SHA_DATE_V 0x3FFFFFFFU
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#define SHA_DATE_S 0
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/** SHA_H_MEM register
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* Sha H memory which contains intermediate hash or finial hash.
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*/
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#define SHA_H_MEM (DR_REG_SHA_BASE + 0x40)
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#define SHA_H_MEM_SIZE_BYTES 64
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/** SHA_M_MEM register
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* Sha M memory which contains message.
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*/
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#define SHA_M_MEM (DR_REG_SHA_BASE + 0x80)
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#define SHA_M_MEM_SIZE_BYTES 64
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#ifdef __cplusplus
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}
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#endif
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