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https://github.com/espressif/esp-idf
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557 lines
17 KiB
C
557 lines
17 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for Cache register operations
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#pragma once
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#include <stdbool.h>
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#include "soc/extmem_reg.h"
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#include "soc/ext_mem_defs.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#include "esp32s2/rom/cache.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
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#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_IBUS2
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#define CACHE_LL_ID_ALL 1 //All of the caches in a type and level, make this value greater than any ID
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#define CACHE_LL_LEVEL_INT_MEM 0 //Cache level for accessing internal mem
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#define CACHE_LL_LEVEL_EXT_MEM 1 //Cache level for accessing external mem
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#define CACHE_LL_LEVEL_ALL 2 //All of the cache levels, make this value greater than any level
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#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
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#define CACHE_LL_L1_ICACHE_AUTOLOAD (1<<0)
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#define CACHE_LL_L1_DCACHE_AUTOLOAD (1<<0)
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/**
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* @brief Check if ICache auto preload is enabled or not
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*
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* @return true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_l1_is_icache_autoload_enabled(void)
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{
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bool enabled = false;
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if (REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_AUTOLOAD_ENA)) {
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enabled = true;
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}
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return enabled;
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}
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/**
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* @brief Check if DCache auto preload is enabled or not
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*
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* @return true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_l1_is_dcache_autoload_enabled(void)
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{
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bool enabled = false;
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if (REG_GET_BIT(EXTMEM_PRO_DCACHE_CTRL_REG, EXTMEM_PRO_DCACHE_AUTOLOAD_ENA)) {
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enabled = true;
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}
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return enabled;
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}
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/**
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* @brief Check if Cache auto preload is enabled or not.
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*
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* @return true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_is_cache_autoload_enabled(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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bool enabled = false;
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switch (type)
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{
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case CACHE_TYPE_INSTRUCTION:
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enabled = cache_ll_l1_is_icache_autoload_enabled();
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break;
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case CACHE_TYPE_DATA:
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enabled = cache_ll_l1_is_dcache_autoload_enabled();
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break;
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default: //CACHE_TYPE_ALL
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enabled = cache_ll_l1_is_icache_autoload_enabled() && cache_ll_l1_is_dcache_autoload_enabled();
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break;
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}
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return enabled;
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}
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/**
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* @brief Disable ICache
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_icache(void)
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{
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Cache_Disable_ICache();
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}
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/**
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* @brief Disable DCache
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_dcache(void)
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{
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Cache_Disable_DCache();
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}
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/**
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* @brief Disable Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*/
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__attribute__((always_inline))
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static inline void cache_ll_disable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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switch (type)
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{
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case CACHE_TYPE_INSTRUCTION:
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cache_ll_l1_disable_icache();
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break;
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case CACHE_TYPE_DATA:
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cache_ll_l1_disable_dcache();
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break;
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default: //CACHE_TYPE_ALL
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cache_ll_l1_disable_icache();
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cache_ll_l1_disable_dcache();
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break;
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}
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}
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/**
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* @brief Enable ICache
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*
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* @param inst_autoload_en ICache auto preload enabled
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_enable_icache(bool inst_autoload_en)
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{
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Cache_Enable_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
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}
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/**
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* @brief Enable DCache
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*
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* @param data_autoload_en DCache auto preload enabled
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_enable_dcache(bool data_autoload_en)
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{
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Cache_Enable_DCache(data_autoload_en ? CACHE_LL_L1_DCACHE_AUTOLOAD : 0);
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}
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/**
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* @brief Enable Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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* @param data_autoload_en data autoload enabled or not
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* @param inst_autoload_en inst autoload enabled or not
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*/
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__attribute__((always_inline))
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static inline void cache_ll_enable_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
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{
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switch (type)
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{
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case CACHE_TYPE_INSTRUCTION:
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cache_ll_l1_enable_icache(inst_autoload_en);
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break;
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case CACHE_TYPE_DATA:
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cache_ll_l1_enable_dcache(data_autoload_en);
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break;
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default: //CACHE_TYPE_ALL
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cache_ll_l1_enable_icache(inst_autoload_en);
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cache_ll_l1_enable_dcache(data_autoload_en);
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break;
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}
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}
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/**
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* @brief Suspend ICache
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_suspend_icache(void)
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{
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Cache_Suspend_ICache();
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}
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/**
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* @brief Suspend DCache
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_suspend_dcache(void)
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{
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Cache_Suspend_DCache();
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}
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/**
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* @brief Suspend Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*/
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__attribute__((always_inline))
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static inline void cache_ll_suspend_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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switch (type)
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{
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case CACHE_TYPE_INSTRUCTION:
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cache_ll_l1_suspend_icache();
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break;
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case CACHE_TYPE_DATA:
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cache_ll_l1_suspend_dcache();
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break;
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default: //CACHE_TYPE_ALL
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cache_ll_l1_suspend_icache();
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cache_ll_l1_suspend_dcache();
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break;
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}
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}
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/**
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* @brief Resume ICache
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*
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* @param inst_autoload_en ICache auto preload enabled
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_resume_icache(bool inst_autoload_en)
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{
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Cache_Resume_ICache(inst_autoload_en ? CACHE_LL_L1_ICACHE_AUTOLOAD : 0);
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}
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/**
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* @brief Resume DCache
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*
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* @param data_autoload_en DCache auto preload enabled
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_resume_dcache(bool data_autoload_en)
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{
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Cache_Resume_DCache(data_autoload_en ? CACHE_LL_L1_DCACHE_AUTOLOAD : 0);
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}
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/**
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* @brief Resume Cache
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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* @param data_autoload_en data autoload enabled or not
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* @param inst_autoload_en inst autoload enabled or not
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*/
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__attribute__((always_inline))
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static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type, uint32_t cache_id, bool inst_autoload_en, bool data_autoload_en)
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{
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switch (type)
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{
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case CACHE_TYPE_INSTRUCTION:
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cache_ll_l1_resume_icache(inst_autoload_en);
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break;
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case CACHE_TYPE_DATA:
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cache_ll_l1_resume_dcache(data_autoload_en);
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break;
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default: //CACHE_TYPE_ALL
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cache_ll_l1_resume_icache(inst_autoload_en);
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cache_ll_l1_resume_dcache(data_autoload_en);
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break;
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}
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}
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/**
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* @brief Check if ICache is enabled or not
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*
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* @param cache_id cache ID (when l1 cache is per core)
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*
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* @return true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_l1_is_icache_enabled(uint32_t cache_id){
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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bool enabled;
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enabled = REG_GET_BIT(EXTMEM_PRO_ICACHE_CTRL_REG, EXTMEM_PRO_ICACHE_ENABLE);
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return enabled;
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}
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/**
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* @brief Check if DCache is enabled or not
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*
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* @param cache_id cache ID (when l1 cache is per core)
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*
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* @return true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_l1_is_dcache_enabled(uint32_t cache_id)
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{
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HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
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bool enabled;
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enabled = REG_GET_BIT(EXTMEM_PRO_DCACHE_CTRL_REG, EXTMEM_PRO_DCACHE_ENABLE);
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return enabled;
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}
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/**
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* @brief Check if ICache or DCache or both is enabled or not
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*
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* @param type see `cache_type_t`
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*
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* @return true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_is_cache_enabled(cache_type_t type)
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{
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bool enabled = false;
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switch (type)
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{
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case CACHE_TYPE_DATA:
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enabled = cache_ll_l1_is_dcache_enabled(0);
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break;
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case CACHE_TYPE_INSTRUCTION:
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enabled = cache_ll_l1_is_icache_enabled(0);
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break;
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default: //CACHE_TYPE_ALL
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enabled = cache_ll_l1_is_dcache_enabled(0) && cache_ll_l1_is_icache_enabled(0);
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break;
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}
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return enabled;
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}
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/**
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* @brief Invalidate cache supported addr
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*
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* Invalidate a cache item
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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* @param vaddr start address of the region to be invalidated
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* @param size size of the region to be invalidated
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*/
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__attribute__((always_inline))
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static inline void cache_ll_invalidate_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
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{
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Cache_Invalidate_Addr(vaddr, size);
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}
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/**
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* @brief Writeback cache supported addr
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*
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* Writeback a cache item
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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* @param vaddr start address of the region to be written back
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* @param size size of the region to be written back
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*/
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__attribute__((always_inline))
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static inline void cache_ll_writeback_addr(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size)
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{
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Cache_WriteBack_Addr(vaddr, size);
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}
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/**
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* @brief Get ICache line size, in bytes
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*
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* @return ICache line size, in bytes
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*/
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__attribute__((always_inline))
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static inline uint32_t cache_ll_l1_icache_get_line_size(void)
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{
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uint32_t size = 0;
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size = Cache_Get_ICache_Line_Size();
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return size;
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}
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/**
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* @brief Get DCache line size, in bytes
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*
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* @return DCache line size, in bytes
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*/
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__attribute__((always_inline))
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static inline uint32_t cache_ll_l1_dcache_get_line_size(void)
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{
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uint32_t size = 0;
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size = Cache_Get_DCache_Line_Size();
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return size;
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}
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/**
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* @brief Get Cache line size, in bytes
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*
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* @param cache_level level of the cache
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* @param type see `cache_type_t`
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* @param cache_id id of the cache in this type and level
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*
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* @return Cache line size, in bytes
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*/
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__attribute__((always_inline))
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static inline uint32_t cache_ll_get_line_size(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
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{
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uint32_t size = 0;
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switch (type)
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{
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case CACHE_TYPE_INSTRUCTION:
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size = cache_ll_l1_icache_get_line_size();
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break;
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case CACHE_TYPE_DATA:
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size = cache_ll_l1_dcache_get_line_size();
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break;
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default: //CACHE_TYPE_ALL
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HAL_ASSERT(false);
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break;
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}
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return size;
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}
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/**
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* @brief Get the buses of a particular cache that are mapped to a virtual address range
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*
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* External virtual address can only be accessed when the involved cache buses are enabled.
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* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param vaddr_start virtual address start
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* @param len vaddr length
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
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{
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(void)cache_id;
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cache_bus_mask_t mask = (cache_bus_mask_t)0;
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uint32_t vaddr_end = vaddr_start + len - 1;
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if (vaddr_start >= SOC_IRAM1_ADDRESS_LOW) {
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mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS1);
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} else if (vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) {
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mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS0);
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
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} else if (vaddr_start >= SOC_DRAM0_CACHE_ADDRESS_LOW) {
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mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS0);
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
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} else if (vaddr_start >= SOC_DRAM1_ADDRESS_LOW) {
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mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS1);
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0));
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
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} else if (vaddr_start >= SOC_DPORT_CACHE_ADDRESS_LOW) {
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mask = (cache_bus_mask_t)(mask | CACHE_BUS_DBUS2);
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0));
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0));
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
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} else if (vaddr_start >= SOC_DROM0_ADDRESS_LOW) {
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mask = (cache_bus_mask_t)(mask | CACHE_BUS_IBUS2);
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DPORT_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS2 : 0));
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0));
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0));
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0));
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mask = (cache_bus_mask_t)(mask | ((vaddr_end >= SOC_IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0));
|
|
} else {
|
|
abort();
|
|
}
|
|
|
|
return mask;
|
|
}
|
|
|
|
/**
|
|
* Enable the Cache Buses
|
|
*
|
|
* @param cache_id cache ID (when l1 cache is per core)
|
|
* @param mask To know which buses should be enabled
|
|
*/
|
|
#if !BOOTLOADER_BUILD
|
|
__attribute__((always_inline))
|
|
#endif
|
|
static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
|
|
{
|
|
(void)cache_id;
|
|
|
|
uint32_t ibus_mask = 0;
|
|
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0);
|
|
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0);
|
|
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0);
|
|
REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
|
|
|
|
uint32_t dbus_mask = 0;
|
|
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0);
|
|
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0);
|
|
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0);
|
|
REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask);
|
|
}
|
|
|
|
/**
|
|
* Disable the Cache Buses
|
|
*
|
|
* @param cache_id cache ID (when l1 cache is per core)
|
|
* @param mask To know which buses should be disabled
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
|
|
{
|
|
(void)cache_id;
|
|
|
|
uint32_t ibus_mask = 0;
|
|
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0);
|
|
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0);
|
|
ibus_mask = ibus_mask | ((mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0);
|
|
REG_SET_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
|
|
|
|
uint32_t dbus_mask = 0;
|
|
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0);
|
|
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0);
|
|
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0);
|
|
REG_SET_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask);
|
|
}
|
|
|
|
/**
|
|
* @brief Get Cache level and the ID of the vaddr
|
|
*
|
|
* @param vaddr_start virtual address start
|
|
* @param len vaddr length
|
|
* @param out_level cache level
|
|
* @param out_id cache id
|
|
*
|
|
* @return true for valid
|
|
*/
|
|
__attribute__((always_inline))
|
|
static inline bool cache_ll_vaddr_to_cache_level_id(uint32_t vaddr_start, uint32_t len, uint32_t *out_level, uint32_t *out_id)
|
|
{
|
|
bool valid = false;
|
|
uint32_t vaddr_end = vaddr_start + len - 1;
|
|
|
|
valid |= ((vaddr_start >= SOC_DROM0_ADDRESS_LOW) && (vaddr_end < SOC_DROM0_ADDRESS_HIGH)) || ((vaddr_start >= SOC_DPORT_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_DRAM0_CACHE_ADDRESS_HIGH));
|
|
valid |= ((vaddr_start >= SOC_IRAM0_CACHE_ADDRESS_LOW) && (vaddr_end < SOC_IRAM1_ADDRESS_HIGH));
|
|
|
|
if (valid) {
|
|
*out_level = 1;
|
|
*out_id = 0;
|
|
}
|
|
|
|
return valid;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|