Felipe Neves 810be86f21 freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port. ...

The riscv vectors.S in riscv component contains the trap vector, which is responsible to
defer interrupts and examine if a task context switch is needed, this change cleans up
this code by hiding all freertos details behind on two functions rtos_it_enter/exit and
their implementations are placed in freertos riscv port files.

2021-01-05 15:39:46 +08:00

..

riscv

freertos/riscv: move freertos aware interrupt code from vectors to the freertos riscv port.

2021-01-05 15:39:46 +08:00

xtensa

freertos: always enable static allocation

2020-12-29 16:18:04 +01:00

port_common.c

freertos: Add RISC-V port

2020-11-13 07:49:11 +11:00