mirror of
https://github.com/espressif/esp-idf
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88 lines
3.2 KiB
C
88 lines
3.2 KiB
C
/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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//Commands for PSRAM chip
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#pragma once
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#include "soc/spi_pins.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*---------------------------------------------------------------------------------
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* AP Memory PSRAM
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*-------------------------------------------------------------------------------*/
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#define PSRAM_QUAD_READ 0x03
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#define PSRAM_QUAD_FAST_READ 0x0B
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#define PSRAM_QUAD_FAST_READ_QUAD 0xEB
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#define PSRAM_QUAD_WRITE 0x02
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#define PSRAM_QUAD_WRITE_QUAD 0x38
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#define PSRAM_QUAD_ENTER_QMODE 0x35
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#define PSRAM_QUAD_EXIT_QMODE 0xF5
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#define PSRAM_QUAD_RESET_EN 0x66
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#define PSRAM_QUAD_RESET 0x99
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#define PSRAM_QUAD_SET_BURST_LEN 0xC0
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#define PSRAM_QUAD_DEVICE_ID 0x9F
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#define PSRAM_QUAD_FAST_READ_DUMMY 4
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#define PSRAM_QUAD_FAST_READ_QUAD_DUMMY 6
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// ID
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#define PSRAM_QUAD_ID_BITS_NUM 24
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#define PSRAM_QUAD_EID_BITS_NUM 48
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#define PSRAM_QUAD_ID_KGD_M 0xff
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#define PSRAM_QUAD_ID_KGD_S 8
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#define PSRAM_QUAD_ID_KGD 0x5d
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#define PSRAM_QUAD_ID_EID_BIT_47_40_M 0xff
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#define PSRAM_QUAD_ID_EID_BIT_47_40_S 16
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// Use the [47:45](bit47~bit45) of EID to distinguish the psram size:
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//
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// BIT47 | BIT46 | BIT45 | SIZE(MBIT)
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// -------------------------------------
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// 0 | 0 | 0 | 16
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// 0 | 0 | 1 | 32
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// 0 | 1 | 0 | 64
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#define PSRAM_QUAD_EID_BIT_47_45_M 0x07
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#define PSRAM_QUAD_EID_BIT_47_45_S 5
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#define PSRAM_QUAD_KGD(id) (((id) >> PSRAM_QUAD_ID_KGD_S) & PSRAM_QUAD_ID_KGD_M)
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#define PSRAM_QUAD_EID_BIT_47_40(id) (((id) >> PSRAM_QUAD_ID_EID_BIT_47_40_S) & PSRAM_QUAD_ID_EID_BIT_47_40_M)
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#define PSRAM_QUAD_SIZE_ID(id) ((PSRAM_QUAD_EID_BIT_47_40(id) >> PSRAM_QUAD_EID_BIT_47_45_S) & PSRAM_QUAD_EID_BIT_47_45_M)
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#define PSRAM_QUAD_IS_VALID(id) (PSRAM_QUAD_KGD(id) == PSRAM_QUAD_ID_KGD)
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#define PSRAM_QUAD_IS_64MBIT_TRIAL(id) (PSRAM_QUAD_EID_BIT_47_40(id) == 0x26)
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// IO-pins for PSRAM.
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// PSRAM clock and cs IO should be configured based on hardware design.
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#define PSRAM_QUAD_CLK_IO MSPI_IOMUX_PIN_NUM_CLK
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#define PSRAM_QUAD_CS_IO MSPI_IOMUX_PIN_NUM_CS1
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#define PSRAM_QUAD_SPIQ_SD0_IO MSPI_IOMUX_PIN_NUM_MISO
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#define PSRAM_QUAD_SPID_SD1_IO MSPI_IOMUX_PIN_NUM_MOSI
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#define PSRAM_QUAD_SPIWP_SD3_IO MSPI_IOMUX_PIN_NUM_WP
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#define PSRAM_QUAD_SPIHD_SD2_IO MSPI_IOMUX_PIN_NUM_HD
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#define PSRAM_QUAD_CMD_LENGTH 8
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#define PSRAM_QUAD_ADDR_LENGTH 24
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#define PSRAM_QUAD_CS_HOLD_VAL 1
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#define PSRAM_QUAD_CS_SETUP_VAL 1
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#define PSRAM_QUAD_CS_ECC_HOLD_TIME_VAL 3
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#define PSRAM_QUAD_PAGE_SIZE 512
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#define PSRAM_QUAD_ECC_ENABLE_MASK BIT(8)
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// QEMU has a simulated 16MB and 32MB Quad SPI PSRAM. Use a fake ID for these.
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#define PSRAM_QUAD_QEMU_16MB_ID 0x6a
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#define PSRAM_QUAD_QEMU_32MB_ID 0x8e
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#ifdef __cplusplus
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}
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#endif
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