mirror of
https://github.com/espressif/esp-idf
synced 2025-03-09 17:19:09 -04:00
This is mostly important on ESP32 ECO3 with the ESP32_ECO3_CACHE_LOCK_FIX, because when we stall the other CPU core before we disable the TG1 WDT then the first CPU can get stuck in WDT ISR handle_livelock_int routine waiting for the other CPU.