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https://github.com/espressif/esp-idf
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ddf6fea6a2
Currently, due to the lack of sleep callback feature. We only init sleep module but don't allocate it. Thus the power domain will be kept during the light sleep. And temporarily disable pcnt sleep retention support on P4 due to the lack of retention module ID.
102 lines
4.0 KiB
C
102 lines
4.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "soc/pcnt_periph.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/pcnt_reg.h"
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const pcnt_signal_conn_t pcnt_periph_signals = {
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.groups = {
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[0] = {
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.irq = ETS_PCNT_INTR_SOURCE,
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.units = {
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[0] = {
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.channels = {
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[0] = {
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.control_sig = PCNT_CTRL_CH0_PAD_IN0_IDX,
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.pulse_sig = PCNT_SIG_CH0_PAD_IN0_IDX
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},
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[1] = {
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.control_sig = PCNT_CTRL_CH1_PAD_IN0_IDX,
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.pulse_sig = PCNT_SIG_CH1_PAD_IN0_IDX
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}
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},
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.clear_sig = PCNT_RST_PAD_IN0_IDX
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},
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[1] = {
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.channels = {
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[0] = {
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.control_sig = PCNT_CTRL_CH0_PAD_IN1_IDX,
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.pulse_sig = PCNT_SIG_CH0_PAD_IN1_IDX,
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},
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[1] = {
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.control_sig = PCNT_CTRL_CH1_PAD_IN1_IDX,
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.pulse_sig = PCNT_SIG_CH1_PAD_IN1_IDX
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}
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},
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.clear_sig = PCNT_RST_PAD_IN1_IDX
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},
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[2] = {
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.channels = {
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[0] = {
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.control_sig = PCNT_CTRL_CH0_PAD_IN2_IDX,
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.pulse_sig = PCNT_SIG_CH0_PAD_IN2_IDX,
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},
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[1] = {
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.control_sig = PCNT_CTRL_CH1_PAD_IN2_IDX,
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.pulse_sig = PCNT_SIG_CH1_PAD_IN2_IDX
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}
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},
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.clear_sig = PCNT_RST_PAD_IN2_IDX
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},
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[3] = {
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.channels = {
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[0] = {
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.control_sig = PCNT_CTRL_CH0_PAD_IN3_IDX,
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.pulse_sig = PCNT_SIG_CH0_PAD_IN3_IDX,
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},
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[1] = {
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.control_sig = PCNT_CTRL_CH1_PAD_IN3_IDX,
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.pulse_sig = PCNT_SIG_CH1_PAD_IN3_IDX
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}
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},
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.clear_sig = PCNT_RST_PAD_IN3_IDX
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}
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}
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}
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}
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};
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#if SOC_PCNT_SUPPORT_SLEEP_RETENTION
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/**
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* PCNT Registers to be saved during sleep retention
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* - Configuration registers, e.g.: PCNT_CTRL_REG, PCNT_U0_CONF0_REG, PCNT_U0_CONF1_REG, PCNT_U0_CONF2_REG, PCNT_U1_CONF0_REG...
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* - Step Configuration registers, e.g.: PCNT_U0_CHANGE_CONF_REG, PCNT_U1_CHANGE_CONF_REG, PCNT_U2_CHANGE_CONF_REG, PCNT_U3_CHANGE_CONF_REG
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* - Interrupt enable registers, e.g.: PCNT_INT_ENA_REG
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*/
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#define PCNT_RETENTION_REGS_CNT 18
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#define PCNT_RETENTION_REGS_BASE (DR_REG_PCNT_BASE + 0x0)
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static const uint32_t pcnt_regs_map[4] = {0x1f040fff, 0x0, 0x0, 0x0};
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static const regdma_entries_config_t pcnt_regs_retention[] = {
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// backup stage: save configuration registers
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// restore stage: restore the configuration registers
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[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_PCNT_LINK(0x00), \
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PCNT_RETENTION_REGS_BASE, PCNT_RETENTION_REGS_BASE, \
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PCNT_RETENTION_REGS_CNT, 0, 0, \
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pcnt_regs_map[0], pcnt_regs_map[1], \
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pcnt_regs_map[2], pcnt_regs_map[3]), \
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.owner = ENTRY(0)}, \
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};
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const pcnt_reg_retention_info_t pcnt_reg_retention_info[SOC_PCNT_GROUPS] = {
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[0] = {
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.regdma_entry_array = pcnt_regs_retention,
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.array_size = ARRAY_SIZE(pcnt_regs_retention),
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.retention_module = SLEEP_RETENTION_MODULE_PCNT0
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},
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};
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#endif // SOC_PCNT_SUPPORT_SLEEP_RETENTION
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