mirror of
https://github.com/espressif/esp-idf
synced 2025-03-22 23:49:10 -04:00
355 lines
16 KiB
C
355 lines
16 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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************************ ESP32H4 Root Clock Source ***************************
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* 1) Internal 8MHz RC Oscillator: RC_FAST (usually referred as FOSC or CK8M/CLK8M in TRM and reg. description)
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*
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* This RC oscillator generates a ~8.5MHz clock signal output as the RC_FAST_CLK.
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*
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* The exact frequency of RC_FAST_CLK cannot be computed in runtime through calibration. You can output the RC_FAST
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* clock signal to a gpio pin in order to get the frequency through an oscillscope or a logic analyzer.
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*
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* 2) External 32MHz Crystal Clock: XTAL
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*
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* 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
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*
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* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
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* can be computed in runtime through calibration.
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*
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* 4) External 32kHz Crystal Clock (optional): XTAL32K
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*
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* The clock source for this XTAL32K_CLK can be either a 32kHz crystal connecting to the XTAL_32K_P and XTAL_32K_N
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* pins or a 32kHz clock signal generated by an external circuit. The external signal must be connected to the
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* XTAL_32K_P pin.
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*
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* XTAL32K_CLK can also be calibrated to get its exact frequency.
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*
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* 5) Internal 32kHz RC Oscillator: RC32K
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*
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* The exact frequency of this clock can be computed in runtime through calibration.
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*/
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/* With the default value of CK8M_DFREQ = 600, RC_FAST clock frequency nears 7 MHz +/- 7% */ //<---- DFREQ to be adjusted! */
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#define SOC_CLK_RC_FAST_FREQ_APPROX 7000000 /*!< Approximate RC_FAST_CLK frequency in Hz */
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/* With the default value of DCAP = 128 */ //<---- DCAP to be adjusted!
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#define SOC_CLK_RC_SLOW_FREQ_APPROX 130000 /*!< Approximate RC_SLOW_CLK frequency in Hz */
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/* With the default value of DFREQ = 707 */ //<---- DFREQ to be adjusted!
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#define SOC_CLK_RC32K_FREQ_APPROX 32768 /*!< Approximate RC32K_CLK frequency in Hz */
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#define SOC_CLK_XTAL32K_FREQ_APPROX 32768 /*!< Approximate XTAL32K_CLK frequency in Hz */
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// Naming convention: SOC_ROOT_CLK_{loc}_{type}_[attr]
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// {loc}: EXT, INT
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// {type}: XTAL, RC
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// [attr] - optional: [frequency], FAST, SLOW
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/**
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* @brief Root clock
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*/
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typedef enum {
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SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 8MHz RC oscillator */
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SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */
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SOC_ROOT_CLK_EXT_XTAL, /*!< External 32MHz crystal */
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SOC_ROOT_CLK_EXT_XTAL32K, /*!< External 32kHz crystal/clock signal */
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SOC_ROOT_CLK_INT_RC32K /*!< Internal 32kHz RC oscillator */
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} soc_root_clk_t;
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/**
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* @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
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* @note Enum values are matched with the register field values on purpose
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*/
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typedef enum {
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SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
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SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 32MHz crystal oscillator frequency multiplier, 96MHz) */
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SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */
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SOC_CPU_CLK_SRC_XTAL_D2 = 3, /*!< Select XTAL_D2_CLK as CPU_CLK source */
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SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
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} soc_cpu_clk_src_t;
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/**
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* @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK
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* @note Enum values are matched with the register field values on purpose
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*/
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typedef enum {
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SOC_RTC_SLOW_CLK_SRC_RC_SLOW = 0, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_XTAL32K = 1, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_RC32K = 2, /*!< Select RC32K_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_INVALID, /*!< Invalid RTC_SLOW_CLK source */
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} soc_rtc_slow_clk_src_t;
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/**
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* @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
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* @note Enum values are matched with the register field values on purpose
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*/
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typedef enum {
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SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 0, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
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SOC_RTC_FAST_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
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} soc_rtc_fast_clk_src_t;
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// Naming convention: SOC_MOD_CLK_{[upstream]clock_name}_[attr]
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// {[upstream]clock_name}: AHB etc.
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// [attr] - optional: FAST, SLOW, D<divider>, F<freq>
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/**
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* @brief Supported clock sources for modules (CPU, peripherals, RTC, etc.)
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*
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* @note enum starts from 1, to save 0 for special purpose
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*/
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typedef enum {
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// For CPU domain
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SOC_MOD_CLK_CPU = 1, /*!< CPU_CLK can be sourced from XTAL, PLL, RC_FAST, or XTAL_D2 by configuring soc_cpu_clk_src_t */
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// For RTC domain
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SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
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SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC32K by configuring soc_rtc_slow_clk_src_t */
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// For digital domain: peripherals, WIFI, BLE
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SOC_MOD_CLK_AHB, /*< AHB_CLK sources from CPU with a configurable divider */
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SOC_MOD_CLK_APB, /*< APB_CLK source is derived from AHB clock */
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SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz */
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SOC_MOD_CLK_XTAL32K, /*< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
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SOC_MOD_CLK_RC_FAST, /*< RC_FAST_CLK comes from the internal 8MHz rc oscillator, passing a clock gating to the peripherals */
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SOC_MOD_CLK_XTAL, /*< XTAL_CLK comes from the external 32MHz crystal */
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SOC_MOD_CLK_PLL, /*< PLL_CLK is the output of 32MHz crystal oscillator frequency multiplier, 96MHz */
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SOC_MOD_CLK_INVALID, /*!< Indication of the end of the available module clock sources */
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} soc_module_clk_t;
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//////////////////////////////////////////////////SYSTIMER///////////////////////////////////////////////////////////////
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/**
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* @brief Type of SYSTIMER clock source
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*/
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typedef enum {
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SYSTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock is XTAL */
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SYSTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< SYSTIMER source clock default choice is XTAL */
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} soc_periph_systimer_clk_src_t;
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//////////////////////////////////////////////////GPTimer///////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of GPTimer
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*
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* The following code can be used to iterate all possible clocks:
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* @code{c}
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* soc_periph_gptimer_clk_src_t gptimer_clks[] = (soc_periph_gptimer_clk_src_t)SOC_GPTIMER_CLKS;
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* for (size_t i = 0; i< sizeof(gptimer_clks) / sizeof(gptimer_clks[0]); i++) {
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* soc_periph_gptimer_clk_src_t clk = gptimer_clks[i];
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* // Test GPTimer with the clock `clk`
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* }
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* @endcode
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*/
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#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_AHB, SOC_MOD_CLK_XTAL}
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/**
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* @brief Type of GPTimer clock source
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*/
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typedef enum {
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GPTIMER_CLK_SRC_AHB = SOC_MOD_CLK_AHB, /*!< Select AHB as the source clock */
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GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_AHB, /*!< Select AHB as the default choice */
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} soc_periph_gptimer_clk_src_t;
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/**
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* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
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*/
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typedef enum {
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TIMER_SRC_CLK_AHB = SOC_MOD_CLK_AHB, /*!< Timer group clock source is AHB */
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TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
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TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_AHB, /*!< Timer group clock source default choice is AHB */
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} soc_periph_tg_clk_src_legacy_t;
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//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of RMT
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*/
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#define SOC_RMT_CLKS {SOC_MOD_CLK_AHB, SOC_MOD_CLK_XTAL}
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/**
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* @brief Type of RMT clock source
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*/
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typedef enum {
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RMT_CLK_SRC_AHB = SOC_MOD_CLK_AHB, /*!< Select AHB clock as the source clock */
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RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_AHB, /*!< Select AHB as the default choice */
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} soc_periph_rmt_clk_src_t;
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/**
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* @brief Type of RMT clock source, reserved for the legacy RMT driver
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*/
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typedef enum {
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RMT_BASECLK_AHB = SOC_MOD_CLK_AHB, /*!< RMT source clock is AHB */
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RMT_BASECLK_XTAL = SOC_MOD_CLK_XTAL, /*!< RMT source clock is XTAL */
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RMT_BASECLK_DEFAULT = SOC_MOD_CLK_AHB, /*!< RMT source clock default choice is AHB */
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} soc_periph_rmt_clk_src_legacy_t;
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//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of Temperature Sensor
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*/
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#define SOC_TEMP_SENSOR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
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/**
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* @brief Type of Temp Sensor clock source
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*/
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typedef enum {
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TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
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TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
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} soc_periph_temperature_sensor_clk_src_t;
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///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
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/**
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* @brief Type of UART clock source, reserved for the legacy UART driver
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*/
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typedef enum {
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UART_SCLK_AHB = SOC_MOD_CLK_AHB, /*!< UART source clock is AHB CLK */
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UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
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UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
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UART_SCLK_DEFAULT = SOC_MOD_CLK_AHB, /*!< UART source clock default choice is AHB */
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} soc_periph_uart_clk_src_legacy_t;
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///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of
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*/
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#define SOC_I2S_CLKS {SOC_MOD_CLK_PLL, SOC_MOD_CLK_XTAL}
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/**
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* @brief I2S clock source enum
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*/
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typedef enum {
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I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL, /*!< Select SOC_MOD_CLK_PLL as the default source clock */
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I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL, /*!< Select PLL as the source clock */
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I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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} soc_periph_i2s_clk_src_t;
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/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of I2C
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*/
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#define SOC_I2C_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
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/**
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* @brief Type of I2C clock source.
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*/
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typedef enum {
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I2C_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,
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I2C_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,
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I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
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} soc_periph_i2c_clk_src_t;
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/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of SPI
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*/
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#define SOC_SPI_CLKS {SOC_MOD_CLK_AHB, SOC_MOD_CLK_XTAL}
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/**
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* @brief Type of SPI clock source.
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*/
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typedef enum {
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SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_AHB, /*!< Select AHB 48M as SPI source clock */
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SPI_CLK_SRC_AHB = SOC_MOD_CLK_AHB, /*!< Select AHB 48M as SPI source clock */
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SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL 32M as SPI source clock */
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} soc_periph_spi_clk_src_t;
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//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of SDM
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*/
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#define SOC_SDM_CLKS {SOC_MOD_CLK_APB}
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/**
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* @brief Sigma Delta Modulator clock source
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*/
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typedef enum {
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SDM_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
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SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
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} soc_periph_sdm_clk_src_t;
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//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of Glitch Filter
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*/
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#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_APB}
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/**
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* @brief Glitch filter clock source
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*/
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typedef enum {
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GLITCH_FILTER_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB clock as the source clock */
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GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB clock as the default clock choice */
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} soc_periph_glitch_filter_clk_src_t;
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//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of ADC digital controller
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*/
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// TODO: temporary support, need to check while supporting
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#define SOC_ADC_DIGI_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M}
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/**
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* @brief ADC digital controller clock source
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*/
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// TODO: temporary support, need to check while supporting
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typedef enum {
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ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
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ADC_DIGI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */
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} soc_periph_adc_digi_clk_src_t;
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//////////////////////////////////////////////////MWDT/////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of MWDT
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*/
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#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_APB}
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/**
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* @brief MWDT clock source
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*/
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typedef enum {
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MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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MWDT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
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MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default clock choice */
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} soc_periph_mwdt_clk_src_t;
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//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of LEDC
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*/
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#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_AHB, SOC_MOD_CLK_RC_FAST}
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/**
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* @brief Type of LEDC clock source, reserved for the legacy LEDC driver
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*/
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typedef enum {
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LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
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LEDC_USE_APB_CLK = SOC_MOD_CLK_AHB, /*!< Select APB(=AHB) as the source clock */
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LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
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LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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LEDC_USE_RTC8M_CLK __attribute__((deprecated("please use 'LEDC_USE_RC_FAST_CLK' instead"))) = LEDC_USE_RC_FAST_CLK, /*!< Alias of 'LEDC_USE_RC_FAST_CLK' */
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} soc_periph_ledc_clk_src_legacy_t;
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#ifdef __cplusplus
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}
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#endif
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