mirror of
https://github.com/espressif/esp-idf
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513 lines
16 KiB
C
513 lines
16 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** AES_KEY_0_REG register
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* AES key data register 0
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*/
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#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_KEY_1_REG register
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* AES key data register 0
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*/
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#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_KEY_2_REG register
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* AES key data register 0
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*/
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#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_KEY_3_REG register
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* AES key data register 0
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*/
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#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_KEY_4_REG register
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* AES key data register 0
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*/
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#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_KEY_5_REG register
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* AES key data register 0
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*/
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#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_KEY_6_REG register
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* AES key data register 0
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*/
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#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_KEY_7_REG register
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* AES key data register 0
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*/
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#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores key_0 that is a part of key material.
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*/
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#define AES_KEY_0 0xFFFFFFFFU
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#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S)
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#define AES_KEY_0_V 0xFFFFFFFFU
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#define AES_KEY_0_S 0
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/** AES_TEXT_IN_0_REG register
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* Source text data register 0
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*/
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#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
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/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_in_0 that is a part of source text material.
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*/
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#define AES_TEXT_IN_0 0xFFFFFFFFU
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#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
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#define AES_TEXT_IN_0_V 0xFFFFFFFFU
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#define AES_TEXT_IN_0_S 0
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/** AES_TEXT_IN_1_REG register
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* Source text data register 0
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*/
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#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
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/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_in_0 that is a part of source text material.
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*/
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#define AES_TEXT_IN_0 0xFFFFFFFFU
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#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
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#define AES_TEXT_IN_0_V 0xFFFFFFFFU
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#define AES_TEXT_IN_0_S 0
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/** AES_TEXT_IN_2_REG register
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* Source text data register 0
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*/
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#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
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/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_in_0 that is a part of source text material.
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*/
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#define AES_TEXT_IN_0 0xFFFFFFFFU
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#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
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#define AES_TEXT_IN_0_V 0xFFFFFFFFU
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#define AES_TEXT_IN_0_S 0
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/** AES_TEXT_IN_3_REG register
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* Source text data register 0
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*/
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#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
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/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_in_0 that is a part of source text material.
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*/
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#define AES_TEXT_IN_0 0xFFFFFFFFU
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#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S)
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#define AES_TEXT_IN_0_V 0xFFFFFFFFU
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#define AES_TEXT_IN_0_S 0
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/** AES_TEXT_OUT_0_REG register
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* Result text data register 0
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*/
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#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
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/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_out_0 that is a part of result text material.
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*/
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#define AES_TEXT_OUT_0 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
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#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_S 0
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/** AES_TEXT_OUT_1_REG register
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* Result text data register 0
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*/
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#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
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/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_out_0 that is a part of result text material.
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*/
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#define AES_TEXT_OUT_0 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
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#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_S 0
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/** AES_TEXT_OUT_2_REG register
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* Result text data register 0
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*/
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#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
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/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_out_0 that is a part of result text material.
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*/
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#define AES_TEXT_OUT_0 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
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#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_S 0
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/** AES_TEXT_OUT_3_REG register
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* Result text data register 0
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*/
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#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
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/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
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* This bits stores text_out_0 that is a part of result text material.
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*/
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#define AES_TEXT_OUT_0 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S)
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#define AES_TEXT_OUT_0_V 0xFFFFFFFFU
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#define AES_TEXT_OUT_0_S 0
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/** AES_MODE_REG register
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* Defines key length and encryption / decryption
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*/
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#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
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/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
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* Configures the key length and encryption / decryption of the AES accelerator.\\
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* 0: AES-128 encryption\\
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* 1: AES-192 encryption\\
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* 2: AES-256 encryption\\
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* 3: Reserved\\
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* 4: AES-128 decryption\\
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* 5: AES-192 decryption\\
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* 6: AES-256 decryption\\
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* 7: Reserved\\
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*/
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#define AES_MODE 0x00000007U
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#define AES_MODE_M (AES_MODE_V << AES_MODE_S)
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#define AES_MODE_V 0x00000007U
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#define AES_MODE_S 0
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/** AES_ENDIAN_REG register
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* AES Endian configure register
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*/
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#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44)
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/** AES_ENDIAN : R/W; bitpos: [5:0]; default: 0;
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* endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out
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* endian or out_stream endian
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*/
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#define AES_ENDIAN 0x0000003FU
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#define AES_ENDIAN_M (AES_ENDIAN_V << AES_ENDIAN_S)
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#define AES_ENDIAN_V 0x0000003FU
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#define AES_ENDIAN_S 0
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/** AES_TRIGGER_REG register
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* Operation start controlling register
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*/
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#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
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/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
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* Configures whether or not to start AES operation. \\
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* 0: No effect\\
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* 1: Start\\
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*/
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#define AES_TRIGGER (BIT(0))
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#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S)
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#define AES_TRIGGER_V 0x00000001U
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#define AES_TRIGGER_S 0
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/** AES_STATE_REG register
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* Operation status register
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*/
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#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
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/** AES_STATE : RO; bitpos: [1:0]; default: 0;
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* Represents the working status of the AES accelerator. \\
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* In Typical AES working mode:\\
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* 0: IDLE\\
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* 1: WORK\\
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* 2: No effect\\
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* 3: No effect\\
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* In DMA-AES working mode:\\
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* 0: IDLE\\
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* 1: WORK\\
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* 2: DONE\\
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* 3: No effect\\
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*/
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#define AES_STATE 0x00000003U
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#define AES_STATE_M (AES_STATE_V << AES_STATE_S)
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#define AES_STATE_V 0x00000003U
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#define AES_STATE_S 0
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/** AES_IV_MEM register
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* The memory that stores initialization vector
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*/
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#define AES_IV_MEM (DR_REG_AES_BASE + 0x50)
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#define AES_IV_MEM_SIZE_BYTES 16
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/** AES_H_MEM register
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* The memory that stores GCM hash subkey
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*/
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#define AES_H_MEM (DR_REG_AES_BASE + 0x60)
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#define AES_H_MEM_SIZE_BYTES 16
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/** AES_J0_MEM register
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* The memory that stores J0
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*/
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#define AES_J0_MEM (DR_REG_AES_BASE + 0x70)
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#define AES_J0_MEM_SIZE_BYTES 16
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/** AES_T0_MEM register
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* The memory that stores T0
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*/
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#define AES_T0_MEM (DR_REG_AES_BASE + 0x80)
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#define AES_T0_MEM_SIZE_BYTES 16
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/** AES_DMA_ENABLE_REG register
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* Selects the working mode of the AES accelerator
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*/
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#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
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/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
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* Configures the working mode of the AES accelerator. \\
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* 0: Typical AES\\
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* 1: DMA-AES\\
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*/
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#define AES_DMA_ENABLE (BIT(0))
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#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
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#define AES_DMA_ENABLE_V 0x00000001U
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#define AES_DMA_ENABLE_S 0
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/** AES_BLOCK_MODE_REG register
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* Defines the block cipher mode
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*/
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#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
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/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
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* Configures the block cipher mode of the AES accelerator operating under the DMA-AES
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* working mode. \\
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* 0: ECB (Electronic Code Block)\\
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* 1: CBC (Cipher Block Chaining)\\
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* 2: OFB (Output FeedBack)\\
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* 3: CTR (Counter)\\
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* 4: CFB8 (8-bit Cipher FeedBack)\\
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* 5: CFB128 (128-bit Cipher FeedBack)\\
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* 6: GCM\\
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* 7: Reserved\\
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*/
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#define AES_BLOCK_MODE 0x00000007U
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#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
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#define AES_BLOCK_MODE_V 0x00000007U
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#define AES_BLOCK_MODE_S 0
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/** AES_BLOCK_NUM_REG register
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* Block number configuration register
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*/
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#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
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/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
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* Represents the Block Number of plaintext or ciphertext when the AES accelerator
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* operates under the DMA-AES working mode. For details, see Section <a
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* href=sec:aes-block-number">link</a>. "
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*/
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#define AES_BLOCK_NUM 0xFFFFFFFFU
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#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
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#define AES_BLOCK_NUM_V 0xFFFFFFFFU
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#define AES_BLOCK_NUM_S 0
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/** AES_INC_SEL_REG register
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* Standard incrementing function register
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*/
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#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
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/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
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* Configures the Standard Incrementing Function for CTR block operation. \\
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* 0: INC<SUB>32</SUB>\\
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* 1: INC<SUB>128</SUB>\\
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*/
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#define AES_INC_SEL (BIT(0))
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#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S)
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#define AES_INC_SEL_V 0x00000001U
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#define AES_INC_SEL_S 0
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/** AES_AAD_BLOCK_NUM_REG register
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* Additional Authential Data block number register
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*/
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#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0)
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/** AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
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* Those bits stores the number of AAD block.
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*/
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#define AES_AAD_BLOCK_NUM 0xFFFFFFFFU
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#define AES_AAD_BLOCK_NUM_M (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S)
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#define AES_AAD_BLOCK_NUM_V 0xFFFFFFFFU
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#define AES_AAD_BLOCK_NUM_S 0
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/** AES_REMAINDER_BIT_NUM_REG register
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* AES remainder bit number register
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*/
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#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4)
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/** AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0;
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* Those bits stores the number of remainder bit.
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*/
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#define AES_REMAINDER_BIT_NUM 0x0000007FU
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#define AES_REMAINDER_BIT_NUM_M (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S)
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#define AES_REMAINDER_BIT_NUM_V 0x0000007FU
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#define AES_REMAINDER_BIT_NUM_S 0
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/** AES_CONTINUE_REG register
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* AES continue register
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*/
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#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8)
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/** AES_CONTINUE : WT; bitpos: [0]; default: 0;
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* Set this bit to continue GCM operation.
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*/
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#define AES_CONTINUE (BIT(0))
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#define AES_CONTINUE_M (AES_CONTINUE_V << AES_CONTINUE_S)
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#define AES_CONTINUE_V 0x00000001U
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#define AES_CONTINUE_S 0
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/** AES_INT_CLEAR_REG register
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* DMA-AES interrupt clear register
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*/
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#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
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/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
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* Configures whether or not to clear AES interrupt. \\
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* 0: No effect \\
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* 1: Clear \\
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*/
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#define AES_INT_CLEAR (BIT(0))
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#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
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#define AES_INT_CLEAR_V 0x00000001U
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#define AES_INT_CLEAR_S 0
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/** AES_INT_ENA_REG register
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* DMA-AES interrupt enable register
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*/
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#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
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/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
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* Configures whether or not to enable AES interrupt.\\
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* 0: Disable\\
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* 1: Enable \\
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*/
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#define AES_INT_ENA (BIT(0))
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#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S)
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#define AES_INT_ENA_V 0x00000001U
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#define AES_INT_ENA_S 0
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/** AES_DATE_REG register
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* AES version control register
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*/
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#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
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/** AES_DATE : R/W; bitpos: [27:0]; default: 36774000;
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* This bits stores the version information of AES.
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*/
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#define AES_DATE 0x0FFFFFFFU
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#define AES_DATE_M (AES_DATE_V << AES_DATE_S)
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#define AES_DATE_V 0x0FFFFFFFU
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#define AES_DATE_S 0
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/** AES_DMA_EXIT_REG register
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* Operation exit controlling register
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*/
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#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
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/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
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* Configures whether or not to exit AES operation. \\
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* 0: No effect\\
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* 1: Exit\\
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* Only valid for DMA-AES operation.
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*/
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#define AES_DMA_EXIT (BIT(0))
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#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
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#define AES_DMA_EXIT_V 0x00000001U
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#define AES_DMA_EXIT_S 0
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/** AES_RX_RESET_REG register
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* AES-DMA reset rx-fifo register
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*/
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#define AES_RX_RESET_REG (DR_REG_AES_BASE + 0xc0)
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/** AES_RX_RESET : WT; bitpos: [0]; default: 0;
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* Set this bit to reset rx_fifo under dma_aes working mode.
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*/
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#define AES_RX_RESET (BIT(0))
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#define AES_RX_RESET_M (AES_RX_RESET_V << AES_RX_RESET_S)
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#define AES_RX_RESET_V 0x00000001U
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#define AES_RX_RESET_S 0
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/** AES_TX_RESET_REG register
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* AES-DMA reset tx-fifo register
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*/
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#define AES_TX_RESET_REG (DR_REG_AES_BASE + 0xc4)
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/** AES_TX_RESET : WT; bitpos: [0]; default: 0;
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* Set this bit to reset tx_fifo under dma_aes working mode.
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*/
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#define AES_TX_RESET (BIT(0))
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#define AES_TX_RESET_M (AES_TX_RESET_V << AES_TX_RESET_S)
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#define AES_TX_RESET_V 0x00000001U
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#define AES_TX_RESET_S 0
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/** AES_PSEUDO_REG register
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* AES PSEUDO function configure register
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*/
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#define AES_PSEUDO_REG (DR_REG_AES_BASE + 0xd0)
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/** AES_PSEUDO_EN : R/W; bitpos: [0]; default: 0;
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* This bit decides whether the pseudo round function is enable or not.
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*/
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#define AES_PSEUDO_EN (BIT(0))
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#define AES_PSEUDO_EN_M (AES_PSEUDO_EN_V << AES_PSEUDO_EN_S)
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#define AES_PSEUDO_EN_V 0x00000001U
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#define AES_PSEUDO_EN_S 0
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/** AES_PSEUDO_BASE : R/W; bitpos: [4:1]; default: 2;
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* Those bits decides the basic number of pseudo round number.
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*/
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#define AES_PSEUDO_BASE 0x0000000FU
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#define AES_PSEUDO_BASE_M (AES_PSEUDO_BASE_V << AES_PSEUDO_BASE_S)
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#define AES_PSEUDO_BASE_V 0x0000000FU
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#define AES_PSEUDO_BASE_S 1
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/** AES_PSEUDO_INC : R/W; bitpos: [6:5]; default: 2;
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|
* Those bits decides the increment number of pseudo round number
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|
*/
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#define AES_PSEUDO_INC 0x00000003U
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#define AES_PSEUDO_INC_M (AES_PSEUDO_INC_V << AES_PSEUDO_INC_S)
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#define AES_PSEUDO_INC_V 0x00000003U
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#define AES_PSEUDO_INC_S 5
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/** AES_PSEUDO_RNG_CNT : R/W; bitpos: [9:7]; default: 7;
|
|
* Those bits decides the update frequency of the pseudo-key.
|
|
*/
|
|
#define AES_PSEUDO_RNG_CNT 0x00000007U
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|
#define AES_PSEUDO_RNG_CNT_M (AES_PSEUDO_RNG_CNT_V << AES_PSEUDO_RNG_CNT_S)
|
|
#define AES_PSEUDO_RNG_CNT_V 0x00000007U
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|
#define AES_PSEUDO_RNG_CNT_S 7
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|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|