mirror of
https://github.com/espressif/esp-idf
synced 2025-04-03 05:10:11 -04:00
7f2b85b82b
- Support CPU frequency 360MHz - Support SOC ROOT clock source switch - Support LP SLOW clock source switch - Support clock calibration
92 lines
2.4 KiB
C
92 lines
2.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdbool.h>
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/regi2c_defs.h"
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#include "soc/hp_sys_clkrst_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Start CPLL self-calibration
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*/
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static inline __attribute__((always_inline)) void regi2c_ctrl_ll_cpll_calibration_start(void)
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{
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CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP);
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}
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/**
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* @brief Stop CPLL self-calibration
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*/
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static inline __attribute__((always_inline)) void regi2c_ctrl_ll_cpll_calibration_stop(void)
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{
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SET_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_STOP);
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}
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/**
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* @brief Check whether CPLL calibration is done
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*
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* @return True if calibration is done; otherwise false
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*/
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static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_cpll_calibration_is_done(void)
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{
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return REG_GET_BIT(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_CPU_PLL_CAL_END);
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}
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/**
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* @brief Start MPLL self-calibration
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*/
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static inline __attribute__((always_inline)) void regi2c_ctrl_ll_mpll_calibration_start(void)
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{
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CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_MSPI_CAL_STOP);
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}
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/**
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* @brief Stop MPLL self-calibration
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*/
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static inline __attribute__((always_inline)) void regi2c_ctrl_ll_mpll_calibration_stop(void)
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{
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SET_PERI_REG_MASK(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_MSPI_CAL_STOP);
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}
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/**
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* @brief Check whether MPLL calibration is done
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*
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* @return True if calibration is done; otherwise false
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*/
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static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_mpll_calibration_is_done(void)
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{
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return REG_GET_BIT(HP_SYS_CLKRST_ANA_PLL_CTRL0_REG, HP_SYS_CLKRST_REG_MSPI_CAL_END);
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}
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/**
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* @brief Enable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
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*/
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static inline void regi2c_ctrl_ll_i2c_saradc_enable(void)
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{
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CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PD);
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SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PU);
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}
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/**
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* @brief Disable the I2C internal bus to do I2C read/write operation to the SAR_ADC register
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*/
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static inline void regi2c_ctrl_ll_i2c_saradc_disable(void)
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{
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CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, ANA_I2C_SAR_FORCE_PU);
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SET_PERI_REG_MASK(ANA_CONFIG2_REG, ANA_I2C_SAR_FORCE_PD);
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}
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#ifdef __cplusplus
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}
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#endif
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