mirror of
https://github.com/espressif/esp-idf
synced 2025-03-23 07:59:11 -04:00
363 lines
17 KiB
C
363 lines
17 KiB
C
/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc.h"
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/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
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/* Output enable in sleep mode */
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#define SLP_OE (BIT(0))
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#define SLP_OE_M (BIT(0))
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#define SLP_OE_V 1
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#define SLP_OE_S 0
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/* Used to enable sleep mode pin functions */
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#define SLP_SEL (BIT(1))
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#define SLP_SEL_M (BIT(1))
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#define SLP_SEL_V 1
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#define SLP_SEL_S 1
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/* Pulldown enable in sleep mode */
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#define SLP_PD (BIT(2))
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#define SLP_PD_M (BIT(2))
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#define SLP_PD_V 1
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#define SLP_PD_S 2
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/* Pullup enable in sleep mode */
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#define SLP_PU (BIT(3))
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#define SLP_PU_M (BIT(3))
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#define SLP_PU_V 1
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#define SLP_PU_S 3
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/* Input enable in sleep mode */
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#define SLP_IE (BIT(4))
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#define SLP_IE_M (BIT(4))
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#define SLP_IE_V 1
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#define SLP_IE_S 4
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/* Drive strength in sleep mode */
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#define SLP_DRV 0x3
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#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
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#define SLP_DRV_V 0x3
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#define SLP_DRV_S 5
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/* Pulldown enable */
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#define FUN_PD (BIT(7))
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#define FUN_PD_M (BIT(7))
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#define FUN_PD_V 1
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#define FUN_PD_S 7
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/* Pullup enable */
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#define FUN_PU (BIT(8))
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#define FUN_PU_M (BIT(8))
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#define FUN_PU_V 1
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#define FUN_PU_S 8
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/* Input enable */
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#define FUN_IE (BIT(9))
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#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
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#define FUN_IE_V 1
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#define FUN_IE_S 9
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/* Drive strength */
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#define FUN_DRV 0x3
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#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
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#define FUN_DRV_V 0x3
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#define FUN_DRV_S 10
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/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
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#define MCU_SEL 0x7
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#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
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#define MCU_SEL_V 0x7
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#define MCU_SEL_S 12
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/* Pin filter (Pulse width shorter than 2 clock cycles will be filtered out) */
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#define FILTER_EN (BIT(15))
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#define FILTER_EN_M (FILTER_EN_V << FILTER_EN_S)
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#define FILTER_EN_V 1
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#define FILTER_EN_S 15
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#define PIN_SLP_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_IE)
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#define PIN_SLP_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_IE)
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#define PIN_SLP_OUTPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_OE)
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#define PIN_SLP_OUTPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_OE)
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#define PIN_SLP_PULLUP_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PU)
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#define PIN_SLP_PULLUP_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PU)
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#define PIN_SLP_PULLDOWN_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_PD)
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#define PIN_SLP_PULLDOWN_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_PD)
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#define PIN_SLP_SEL_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,SLP_SEL)
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#define PIN_SLP_SEL_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,SLP_SEL)
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#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
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#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
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#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
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#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
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#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
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#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
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#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
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#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
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#define PIN_FILTER_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FILTER_EN)
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#define PIN_FILTER_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FILTER_EN)
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#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_XTAL_32K_P_U
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#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_XTAL_32K_N_U
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#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
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#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U
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#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_MTMS_U
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#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_MTDI_U
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#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_MTCK_U
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#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_MTDO_U
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#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
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#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
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#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U
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#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U
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#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U
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#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U
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#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_GPIO14_U
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#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_GPIO15_U
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#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_U0TXD_U
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#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_U0RXD_U
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#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_SDIO_CMD_U
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#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_SDIO_CLK_U
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#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_SDIO_DATA0_U
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#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_SDIO_DATA1_U
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#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_SDIO_DATA2_U
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#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_SDIO_DATA3_U
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#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_SPICS0_U
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#define IO_MUX_GPIO25_REG PERIPHS_IO_MUX_SPIQ_U
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#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SPIWP_U
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#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_VDD_SPI_U
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#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SPIHD_U
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#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_SPICLK_U
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#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_SPID_U
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#define PIN_FUNC_GPIO 1
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#define GPIO_PAD_PULLUP(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
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#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
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#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
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#define SPI_HD_GPIO_NUM 28
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#define SPI_WP_GPIO_NUM 26
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#define SPI_CS0_GPIO_NUM 24
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#define SPI_CLK_GPIO_NUM 29
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#define SPI_D_GPIO_NUM 30
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#define SPI_Q_GPIO_NUM 25
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#define SD_CLK_GPIO_NUM 19
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#define SD_CMD_GPIO_NUM 18
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#define SD_DATA0_GPIO_NUM 20
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#define SD_DATA1_GPIO_NUM 21
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#define SD_DATA2_GPIO_NUM 22
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#define SD_DATA3_GPIO_NUM 23
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#define USB_INT_PHY0_DM_GPIO_NUM 12
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#define USB_INT_PHY0_DP_GPIO_NUM 13
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#define EXT_OSC_SLOW_GPIO_NUM 0
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#define MAX_RTC_GPIO_NUM 8
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#define MAX_PAD_GPIO_NUM 30
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#define MAX_GPIO_NUM 34
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#define DIG_IO_HOLD_BIT_SHIFT 32
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#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
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#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
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#define CLK_OUT3 0x1f
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#define CLK_OUT3_V CLK_OUT3
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#define CLK_OUT3_S 10
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#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
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#define CLK_OUT2 0x1f
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#define CLK_OUT2_V CLK_OUT2
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#define CLK_OUT2_S 5
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#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
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#define CLK_OUT1 0x1f
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#define CLK_OUT1_V CLK_OUT1
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#define CLK_OUT1_S 0
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#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
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// definitions above are inherited from previous version of code, should double check
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// definitions below are generated from pin_txt.csv
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#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE + 0x4)
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#define FUNC_XTAL_32K_P_GPIO0 1
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#define FUNC_XTAL_32K_P_GPIO0_0 0
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#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE + 0x8)
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#define FUNC_XTAL_32K_N_GPIO1 1
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#define FUNC_XTAL_32K_N_GPIO1_0 0
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#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE + 0xC)
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#define FUNC_GPIO2_FSPIQ 2
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#define FUNC_GPIO2_GPIO2 1
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#define FUNC_GPIO2_GPIO2_0 0
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#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE + 0x10)
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#define FUNC_GPIO3_GPIO3 1
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#define FUNC_GPIO3_GPIO3_0 0
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#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE + 0x14)
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#define FUNC_MTMS_FSPIHD 2
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#define FUNC_MTMS_GPIO4 1
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#define FUNC_MTMS_MTMS 0
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#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE + 0x18)
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#define FUNC_MTDI_FSPIWP 2
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#define FUNC_MTDI_GPIO5 1
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#define FUNC_MTDI_MTDI 0
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#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE + 0x1C)
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#define FUNC_MTCK_FSPICLK 2
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#define FUNC_MTCK_GPIO6 1
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#define FUNC_MTCK_MTCK 0
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#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE + 0x20)
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#define FUNC_MTDO_FSPID 2
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#define FUNC_MTDO_GPIO7 1
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#define FUNC_MTDO_MTDO 0
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#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE + 0x24)
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#define FUNC_GPIO8_GPIO8 1
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#define FUNC_GPIO8_GPIO8_0 0
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#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE + 0x28)
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#define FUNC_GPIO9_GPIO9 1
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#define FUNC_GPIO9_GPIO9_0 0
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#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE + 0x2C)
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#define FUNC_GPIO10_GPIO10 1
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#define FUNC_GPIO10_GPIO10_0 0
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#define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE + 0x30)
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#define FUNC_GPIO11_GPIO11 1
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#define FUNC_GPIO11_GPIO11_0 0
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#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE + 0x34)
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#define FUNC_GPIO12_GPIO12 1
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#define FUNC_GPIO12_GPIO12_0 0
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#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE + 0x38)
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#define FUNC_GPIO13_GPIO13 1
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#define FUNC_GPIO13_GPIO13_0 0
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#define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE + 0x3C)
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#define FUNC_GPIO14_GPIO14 1
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#define FUNC_GPIO14_GPIO14_0 0
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#define PERIPHS_IO_MUX_GPIO15_U (REG_IO_MUX_BASE + 0x40)
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#define FUNC_GPIO15_GPIO15 1
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#define FUNC_GPIO15_GPIO15_0 0
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#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE + 0x44)
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#define FUNC_U0TXD_FSPICS0 2
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#define FUNC_U0TXD_GPIO16 1
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#define FUNC_U0TXD_U0TXD 0
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#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE + 0x48)
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#define FUNC_U0RXD_FSPICS1 2
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#define FUNC_U0RXD_GPIO17 1
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#define FUNC_U0RXD_U0RXD 0
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#define PERIPHS_IO_MUX_SDIO_CMD_U (REG_IO_MUX_BASE + 0x4C)
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#define FUNC_SDIO_CMD_FSPICS2 2
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#define FUNC_SDIO_CMD_GPIO18 1
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#define FUNC_SDIO_CMD_SDIO_CMD 0
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#define PERIPHS_IO_MUX_SDIO_CLK_U (REG_IO_MUX_BASE + 0x50)
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#define FUNC_SDIO_CLK_FSPICS3 2
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#define FUNC_SDIO_CLK_GPIO19 1
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#define FUNC_SDIO_CLK_SDIO_CLK 0
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#define PERIPHS_IO_MUX_SDIO_DATA0_U (REG_IO_MUX_BASE + 0x54)
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#define FUNC_SDIO_DATA0_FSPICS4 2
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#define FUNC_SDIO_DATA0_GPIO20 1
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#define FUNC_SDIO_DATA0_SDIO_DATA0 0
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#define PERIPHS_IO_MUX_SDIO_DATA1_U (REG_IO_MUX_BASE + 0x58)
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#define FUNC_SDIO_DATA1_FSPICS5 2
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#define FUNC_SDIO_DATA1_GPIO21 1
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#define FUNC_SDIO_DATA1_SDIO_DATA1 0
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#define PERIPHS_IO_MUX_SDIO_DATA2_U (REG_IO_MUX_BASE + 0x5C)
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#define FUNC_SDIO_DATA2_GPIO22 1
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#define FUNC_SDIO_DATA2_SDIO_DATA2 0
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#define PERIPHS_IO_MUX_SDIO_DATA3_U (REG_IO_MUX_BASE + 0x60)
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#define FUNC_SDIO_DATA3_GPIO23 1
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#define FUNC_SDIO_DATA3_SDIO_DATA3 0
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#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE + 0x64)
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#define FUNC_SPICS0_GPIO24 1
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#define FUNC_SPICS0_SPICS0 0
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#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE + 0x68)
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#define FUNC_SPIQ_GPIO25 1
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#define FUNC_SPIQ_SPIQ 0
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#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE + 0x6C)
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#define FUNC_SPIWP_GPIO26 1
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#define FUNC_SPIWP_SPIWP 0
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#define PERIPHS_IO_MUX_VDD_SPI_U (REG_IO_MUX_BASE + 0x70)
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#define FUNC_VDD_SPI_GPIO27 1
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#define FUNC_VDD_SPI_GPIO27_0 0
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#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE + 0x74)
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#define FUNC_SPIHD_GPIO28 1
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#define FUNC_SPIHD_SPIHD 0
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#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE + 0x78)
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#define FUNC_SPICLK_GPIO29 1
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#define FUNC_SPICLK_SPICLK 0
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#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE + 0x7C)
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#define FUNC_SPID_GPIO30 1
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#define FUNC_SPID_SPID 0
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/** IO_MUX_PIN_CTRL_REG register
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* Clock Output Configuration Register
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*/
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#define IO_MUX_PIN_CTRL_REG (REG_IO_MUX_BASE + 0x0)
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/** IO_MUX_CLK_OUT1 : R/W; bitpos: [4:0]; default: 15;
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* If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
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* CLK_OUT_out1 can be found in peripheral output signals.
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*/
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#define IO_MUX_CLK_OUT1 0x0000001FU
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#define IO_MUX_CLK_OUT1_M (IO_MUX_CLK_OUT1_V << IO_MUX_CLK_OUT1_S)
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#define IO_MUX_CLK_OUT1_V 0x0000001FU
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#define IO_MUX_CLK_OUT1_S 0
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/** IO_MUX_CLK_OUT2 : R/W; bitpos: [9:5]; default: 15;
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* If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
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* CLK_OUT_out2 can be found in peripheral output signals.
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*/
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#define IO_MUX_CLK_OUT2 0x0000001FU
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#define IO_MUX_CLK_OUT2_M (IO_MUX_CLK_OUT2_V << IO_MUX_CLK_OUT2_S)
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#define IO_MUX_CLK_OUT2_V 0x0000001FU
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#define IO_MUX_CLK_OUT2_S 5
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/** IO_MUX_CLK_OUT3 : R/W; bitpos: [14:10]; default: 7;
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* If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
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* CLK_OUT_out3 can be found in peripheral output signals.
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*/
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#define IO_MUX_CLK_OUT3 0x0000001FU
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#define IO_MUX_CLK_OUT3_M (IO_MUX_CLK_OUT3_V << IO_MUX_CLK_OUT3_S)
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#define IO_MUX_CLK_OUT3_V 0x0000001FU
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#define IO_MUX_CLK_OUT3_S 10
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/** IO_MUX_MODEM_DIAG_EN_REG register
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* GPIO MATRIX Configure Register for modem diag
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*/
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#define IO_MUX_MODEM_DIAG_EN_REG (REG_IO_MUX_BASE + 0xbc)
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/** IO_MUX_MODEM_DIAG_EN : R/W; bitpos: [31:0]; default: 0;
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* bit i to enable modem_diag[i] into gpio matrix. 1:enable modem_diag[i] into gpio
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* matrix. 0:enable other signals into gpio matrix
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*/
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#define IO_MUX_MODEM_DIAG_EN 0xFFFFFFFFU
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#define IO_MUX_MODEM_DIAG_EN_M (IO_MUX_MODEM_DIAG_EN_V << IO_MUX_MODEM_DIAG_EN_S)
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#define IO_MUX_MODEM_DIAG_EN_V 0xFFFFFFFFU
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#define IO_MUX_MODEM_DIAG_EN_S 0
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/** IO_MUX_DATE_REG register
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* IO MUX Version Control Register
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*/
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#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
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/** IO_MUX_REG_DATE : R/W; bitpos: [27:0]; default: 35655776;
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* Version control register
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*/
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#define IO_MUX_REG_DATE 0x0FFFFFFFU
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#define IO_MUX_REG_DATE_M (IO_MUX_REG_DATE_V << IO_MUX_REG_DATE_S)
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#define IO_MUX_REG_DATE_V 0x0FFFFFFFU
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#define IO_MUX_REG_DATE_S 0
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