mirror of
https://github.com/espressif/esp-idf
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305 lines
8.9 KiB
C
305 lines
8.9 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for Cache register operations
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#pragma once
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#include <stdbool.h>
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#include "soc/extmem_reg.h"
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#include "soc/ext_mem_defs.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#include "esp32c2/rom/cache.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
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#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_DBUS0
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#define CACHE_LL_L1_ACCESS_EVENT_MASK (0x3f)
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#define CACHE_LL_L1_ACCESS_EVENT_DBUS_WR_IC (1<<5)
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#define CACHE_LL_L1_ACCESS_EVENT_DBUS_REJECT (1<<4)
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#define CACHE_LL_L1_ACCESS_EVENT_DBUS_ACS_MSK_IC (1<<3)
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#define CACHE_LL_L1_ACCESS_EVENT_IBUS_REJECT (1<<2)
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#define CACHE_LL_L1_ACCESS_EVENT_IBUS_WR_IC (1<<1)
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#define CACHE_LL_L1_ACCESS_EVENT_IBUS_ACS_MSK_IC (1<<0)
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#define CACHE_LL_L1_ILG_EVENT_MASK (0x23)
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#define CACHE_LL_L1_ILG_EVENT_MMU_ENTRY_FAULT (1<<5)
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#define CACHE_LL_L1_ILG_EVENT_PRELOAD_OP_FAULT (1<<1)
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#define CACHE_LL_L1_ILG_EVENT_SYNC_OP_FAULT (1<<0)
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//On ESP32C2, the auto preload flag is always 0
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#define CACHE_LL_L1_ICACHE_AUTOLOAD 0
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/**
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* @brief Check if Cache auto preload is enabled or not. On ESP32C2, instructions and data share Cache
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*
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* @param type see `cache_type_t`
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*
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* @return false (On ESP32C2, it's always false)
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_is_cache_autoload_enabled(cache_type_t type)
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{
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bool enabled = false;
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return enabled;
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}
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/**
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* @brief Disable Cache. On ESP32C2, instructions and data share Cache
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*
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* @param type see `cache_type_t`
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*/
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__attribute__((always_inline))
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static inline void cache_ll_disable_cache(cache_type_t type)
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{
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(void) type;
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Cache_Disable_ICache();
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}
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/**
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* @brief Enable Cache. On ESP32C2, instructions and data share Cache
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*
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* @param type see `cache_type_t`
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*
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* @param data_autoload_en Dcache auto preload enabled
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*
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* @param inst_autoload_en Icache auto preload enabled
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*/
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__attribute__((always_inline))
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static inline void cache_ll_enable_cache(cache_type_t type, bool inst_autoload_en, bool data_autoload_en)
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{
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Cache_Enable_ICache(CACHE_LL_L1_ICACHE_AUTOLOAD);
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}
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/**
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* @brief Suspend Cache. On ESP32C2, instructions and data share Cache
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*
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* @param type see `cache_type_t`
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*/
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__attribute__((always_inline))
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static inline void cache_ll_suspend_cache(cache_type_t type)
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{
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Cache_Suspend_ICache();
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}
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/**
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* @brief Resume Cache. On ESP32C2, instructions and data share Cache
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*
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* @param type see `cache_type_t`
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*
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* @param data_autoload_en Dcache auto preload enabled
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*
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* @param inst_autoload_en Icache auto preload enabled
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*/
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__attribute__((always_inline))
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static inline void cache_ll_resume_cache(cache_type_t type, bool inst_autoload_en, bool data_autoload_en)
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{
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Cache_Resume_ICache(CACHE_LL_L1_ICACHE_AUTOLOAD);
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}
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/**
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* @brief Check if Cache is enabled or not. On ESP32C2, instructions and data share Cache
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*
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* @param type see `cache_type_t`
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*
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* @return true: enabled; false: disabled
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*/
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__attribute__((always_inline))
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static inline bool cache_ll_is_cache_enabled(cache_type_t type)
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{
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bool enabled = false;
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enabled = REG_GET_BIT(EXTMEM_ICACHE_CTRL_REG, EXTMEM_ICACHE_ENABLE);
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return enabled;
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}
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/**
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* @brief Invalidate cache supported addr
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*
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* Invalidate a Cache item
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*
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* @param vaddr Start address of the region to be invalidated
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* @param size Size of the region to be invalidated
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*/
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__attribute__((always_inline))
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static inline void cache_ll_invalidate_addr(uint32_t vaddr, uint32_t size)
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{
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Cache_Invalidate_Addr(vaddr, size);
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}
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/**
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* @brief Get Cache line size, in bytes
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*
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* @param type see `cache_type_t`
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*
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* @return Cache line size, in bytes
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*/
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__attribute__((always_inline))
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static inline uint32_t cache_ll_get_line_size(cache_type_t type)
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{
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uint32_t size = 0;
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size = Cache_Get_ICache_Line_Size();
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return size;
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}
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/**
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* @brief Get the buses of a particular cache that are mapped to a virtual address range
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*
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* External virtual address can only be accessed when the involved cache buses are enabled.
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* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param vaddr_start virtual address start
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* @param len vaddr length
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
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{
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HAL_ASSERT(cache_id == 0);
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cache_bus_mask_t mask = 0;
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uint32_t vaddr_end = vaddr_start + len - 1;
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if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW && vaddr_end < IRAM0_CACHE_ADDRESS_HIGH) {
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mask |= CACHE_BUS_IBUS0;
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} else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW && vaddr_end < DRAM0_CACHE_ADDRESS_HIGH) {
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mask |= CACHE_BUS_DBUS0;
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} else {
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HAL_ASSERT(0); //Out of region
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}
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return mask;
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}
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/**
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* Enable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param mask To know which buses should be enabled
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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HAL_ASSERT(cache_id == 0);
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//On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
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HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
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uint32_t ibus_mask = 0;
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ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0;
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
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uint32_t dbus_mask = 0;
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dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0;
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REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
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}
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/**
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* Disable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param mask To know which buses should be disabled
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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HAL_ASSERT(cache_id == 0);
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//On esp32c2, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first
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HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
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uint32_t ibus_mask = 0;
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ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_ICACHE_SHUT_IBUS : 0;
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REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, ibus_mask);
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uint32_t dbus_mask = 0;
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dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_ICACHE_SHUT_DBUS : 0;
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REG_SET_BIT(EXTMEM_ICACHE_CTRL1_REG, dbus_mask);
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}
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/*------------------------------------------------------------------------------
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* Interrupt
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*----------------------------------------------------------------------------*/
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/**
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* @brief Enable Cache access error interrupt
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*
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* @param cache_id Cache ID, not used on C2. For compabitlity
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* @param mask Interrupt mask
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*/
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static inline void cache_ll_l1_enable_access_error_intr(uint32_t cache_id, uint32_t mask)
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{
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SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG, mask);
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}
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/**
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* @brief Clear Cache access error interrupt status
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*
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* @param cache_id Cache ID, not used on C2. For compabitlity
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* @param mask Interrupt mask
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*/
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static inline void cache_ll_l1_clear_access_error_intr(uint32_t cache_id, uint32_t mask)
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{
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SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG, mask);
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}
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/**
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* @brief Get Cache access error interrupt status
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*
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* @param cache_id Cache ID, not used on C2. For compabitlity
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* @param mask Interrupt mask
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*
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* @return Status mask
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*/
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static inline uint32_t cache_ll_l1_get_access_error_intr_status(uint32_t cache_id, uint32_t mask)
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{
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return GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, mask);
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}
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/**
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* @brief Enable Cache illegal error interrupt
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*
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* @param cache_id Cache ID, not used on C2. For compabitlity
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* @param mask Interrupt mask
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*/
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static inline void cache_ll_l1_enable_illegal_error_intr(uint32_t cache_id, uint32_t mask)
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{
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SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG, mask);
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}
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/**
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* @brief Clear Cache illegal error interrupt status
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*
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* @param cache_id Cache ID, not used on C2. For compabitlity
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* @param mask Interrupt mask
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*/
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static inline void cache_ll_l1_clear_illegal_error_intr(uint32_t cache_id, uint32_t mask)
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{
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SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG, mask);
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}
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/**
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* @brief Get Cache illegal error interrupt status
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*
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* @param cache_id Cache ID, not used on C2. For compabitlity
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* @param mask Interrupt mask
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*
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* @return Status mask
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*/
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static inline uint32_t cache_ll_l1_get_illegal_error_intr_status(uint32_t cache_id, uint32_t mask)
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{
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return GET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ST_REG, mask);
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}
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#ifdef __cplusplus
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}
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#endif
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