mirror of
https://github.com/espressif/esp-idf
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7f2b85b82b
- Support CPU frequency 360MHz - Support SOC ROOT clock source switch - Support LP SLOW clock source switch - Support clock calibration
66 lines
2.6 KiB
C
66 lines
2.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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// TODO: IDF-5731
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#define PMU_ICG_APB_ENA_CORE0_CPU 0
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#define PMU_ICG_APB_ENA_CORE1_CPU 1
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#define PMU_ICG_APB_ENA_CORE0_CLIC 2
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#define PMU_ICG_APB_ENA_CORE1_CLIC 3
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#define PMU_ICG_APB_ENA_MISC_CPU 4
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#define PMU_ICG_APB_ENA_MISC_SYS 5
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#define PMU_ICG_APB_ENA_ICM_SYS 6
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#define PMU_ICG_APB_ENA_ICM_CPU 7
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#define PMU_ICG_APB_ENA_ICM_MEM 8
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#define PMU_ICG_APB_ENA_ICM_APB 9
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#define PMU_ICG_APB_ENA_TCM_CPU 10
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#define PMU_ICG_APB_ENA_L2MEM_MEM 11
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#define PMU_ICG_APB_ENA_L2MEM_SYS 12
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#define PMU_ICG_APB_ENA_L1CACHE_CPU 13
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#define PMU_ICG_APB_ENA_L1CACHE_D_CPU 14
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#define PMU_ICG_APB_ENA_L1CACHE_I0_CPU 15
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#define PMU_ICG_APB_ENA_L1CACHE_I1_CPU 16
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#define PMU_ICG_APB_ENA_L1CACHE_MEM 17
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#define PMU_ICG_APB_ENA_L1CACHE_D_MEM 18
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#define PMU_ICG_APB_ENA_L1CACHE_I0_MEM 19
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#define PMU_ICG_APB_ENA_L1CACHE_I1_MEM 20
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#define PMU_ICG_APB_ENA_L2CACHE_MEM 21
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#define PMU_ICG_APB_ENA_L2CACHE_SYS 22
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#define PMU_ICG_APB_ENA_REGDMA 23
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#define PMU_ICG_APB_ENA_HP_CLKRST 24
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#define PMU_ICG_APB_ENA_SYSREG_APB 25
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#define PMU_ICG_APB_ENA_INTRMTX_APB 26
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#define PMU_ICG_FUNC_ENA_CORE0_CPU 0
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#define PMU_ICG_FUNC_ENA_CORE1_CPU 1
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#define PMU_ICG_FUNC_ENA_CORE0_CLIC 2
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#define PMU_ICG_FUNC_ENA_CORE1_CLIC 3
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#define PMU_ICG_FUNC_ENA_MISC_CPU 4
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#define PMU_ICG_FUNC_ENA_MISC_SYS 5
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#define PMU_ICG_FUNC_ENA_ICM_SYS 6
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#define PMU_ICG_FUNC_ENA_ICM_CPU 7
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#define PMU_ICG_FUNC_ENA_ICM_MEM 8
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#define PMU_ICG_FUNC_ENA_ICM_APB 9
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#define PMU_ICG_FUNC_ENA_TCM_CPU 10
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#define PMU_ICG_FUNC_ENA_L2MEM_MEM 11
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#define PMU_ICG_FUNC_ENA_L2MEM_SYS 12
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#define PMU_ICG_FUNC_ENA_L1CACHE_CPU 13
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#define PMU_ICG_FUNC_ENA_L1CACHE_D_CPU 14
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#define PMU_ICG_FUNC_ENA_L1CACHE_I0_CPU 15
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#define PMU_ICG_FUNC_ENA_L1CACHE_I1_CPU 16
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#define PMU_ICG_FUNC_ENA_L1CACHE_MEM 17
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#define PMU_ICG_FUNC_ENA_L1CACHE_D_MEM 18
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#define PMU_ICG_FUNC_ENA_L1CACHE_I0_MEM 19
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#define PMU_ICG_FUNC_ENA_L1CACHE_I1_MEM 20
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#define PMU_ICG_FUNC_ENA_L2CACHE_MEM 21
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#define PMU_ICG_FUNC_ENA_L2CACHE_SYS 22
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#define PMU_ICG_FUNC_ENA_REGDMA 23
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#define PMU_ICG_FUNC_ENA_HP_CLKRST 24
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#define PMU_ICG_FUNC_ENA_SYSREG_APB 25
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#define PMU_ICG_FUNC_ENA_INTRMTX_APB 26
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