Jiang Jiang Jian d431971fed Merge branch 'feat/ci_check_ll_rw_register_half_word_v5.3' into 'release/v5.3' ...

fix(hal): LL function read write the register by half-world (v5.3)

See merge request espressif/esp-idf!31722

2024-07-26 11:46:40 +08:00

..

include/hal

Merge branch 'feat/ci_check_ll_rw_register_half_word_v5.3' into 'release/v5.3'

2024-07-26 11:46:40 +08:00

clk_tree_hal.c

feat(esp_hw_support): support esp32p4 clock output

2024-04-17 15:09:49 +08:00

efuse_hal.c

fix(test): check call graph for hal component

2023-07-05 09:09:01 +08:00

modem_clock_hal.c

fix(esp_hw_support): fix ble on esp32c6eco1 depends on wifipwr clock domain

2023-12-07 14:02:04 +08:00

pau_hal.c

fix(ci): bypass c5mp ci check

2024-04-10 20:45:49 +08:00

pmu_hal.c

fix(esp_pm): fix PM_SLP_IRAM_OPT/PM_RTOS_IDLE_OPT feature

2023-07-14 21:21:19 +08:00