Chen Jichang 4b3a2b2f8b fix(parlio): fix rempty interrupt during resetting fifo ...

Move the fifo reset to after disabling the tx core clock.
And add external non-free running clock src test.

2025-01-23 17:54:00 +08:00

..

parlio

fix(parlio): fix rempty interrupt during resetting fifo

2025-01-23 17:54:00 +08:00

.build-test-rules.yml

ci(parlio_rx): enable target test for h2 and p4

2024-06-20 16:02:21 +08:00