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https://github.com/espressif/esp-idf
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3d0466ccd1
Ref. https://github.com/espressif/esp-idf/issues/1684 This change allows RTTI to be enabled in menuconfig. For full RTTI support, libstdc++.a in the toolchain should be built without -fno-rtti, as it is done now. Generally if libstdc++.a is built with RTTI, applications which do not use RTTI (and build with -fno-rtti) could still include typeinfo structures referenced from STL classes’ vtables. This change works around this, by moving all typeinfo structures from libstdc++.a into a non-loadable section, placed into a non-existent memory region starting at address 0. This can be done because when the application is compiled with -fno-rtti, typeinfo structures are not used at run time. This way, typeinfo structures do not contribute to the application binary size. If the application is build with RTTI support, typeinfo structures are linked into the application .rodata section as usual. Note that this commit does not actually enable RTTI support. The respective Kconfig option is hidden, and will be made visible when the toolchain is updated.
116 lines
4.1 KiB
Plaintext
116 lines
4.1 KiB
Plaintext
/* ESP32 Linker Script Memory Layout
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This file describes the memory layout (memory blocks) as virtual
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memory addresses.
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esp32.project.ld contains output sections to link compiler output
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into these memory blocks.
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***
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This linker script is passed through the C preprocessor to include
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configuration options.
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Please use preprocessor features sparingly! Restrict
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to simple macros with numeric values, and/or #if/#endif blocks.
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*/
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#include "sdkconfig.h"
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/* If BT is not built at all */
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#ifndef CONFIG_BT_RESERVE_DRAM
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#define CONFIG_BT_RESERVE_DRAM 0
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#endif
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#if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE)
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ASSERT((CONFIG_ESP32_FIXED_STATIC_RAM_SIZE <= 0x2c200),
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"Fixed static ram data does not fit.")
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#define DRAM0_0_SEG_LEN CONFIG_ESP32_FIXED_STATIC_RAM_SIZE
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#else
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#define DRAM0_0_SEG_LEN 0x2c200
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#endif
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
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/* Even though the segment name is iram, it is actually mapped to flash
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*/
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000-0x18
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/*
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(0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file
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which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash
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cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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Enabling Bluetooth & Trace Memory features in menuconfig will decrease
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the amount of RAM available.
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Note: Length of this section *should* be 0x50000, and this extra DRAM is available
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in heap at runtime. However due to static ROM memory usage at this 176KB mark, the
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additional static memory temporarily cannot be used.
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*/
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dram0_0_seg (RW) : org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM,
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len = DRAM0_0_SEG_LEN - CONFIG_BT_RESERVE_DRAM
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/* Flash mapped constant data */
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drom0_0_seg (R) : org = 0x3F400018, len = 0x400000-0x18
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/* (See iram0_2_seg for meaning of 0x18 offset in the above.) */
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/* RTC fast memory (executable). Persists over deep sleep.
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*/
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rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
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/* RTC fast memory (same block as above), viewed from data bus */
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rtc_data_seg(RW) : org = 0x3ff80000, len = 0x2000
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/* RTC slow memory (data accessible). Persists over deep sleep.
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Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
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*/
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rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ESP32_ULP_COPROC_RESERVE_MEM,
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len = 0x1000 - CONFIG_ESP32_ULP_COPROC_RESERVE_MEM
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/* external memory ,including data and text */
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extern_ram_seg(RWX) : org = 0x3F800000,
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len = 0x400000
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/* This is not a memory range which can really be accessed; we use it as a "bitbucket"
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where non-loadable sections, which aren't used at run time, can be discarded.
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*/
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discard_seg (R) : org = 0x00000000, len = 0x10000000
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}
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#if defined(CONFIG_ESP32_USE_FIXED_STATIC_RAM_SIZE)
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/* static data ends at defined address */
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_static_data_end = 0x3FFB0000 + DRAM0_0_SEG_LEN;
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#else
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_static_data_end = _bss_end;
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#endif
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/* Heap ends at top of dram0_0_seg */
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_heap_end = 0x40000000 - CONFIG_ESP32_TRACEMEM_RESERVE_DRAM;
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_data_seg_org = ORIGIN(rtc_data_seg);
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/* The lines below define location alias for .rtc.data section based on Kconfig option.
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When the option is not defined then use slow memory segment
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else the data will be placed in fast memory segment */
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#ifndef CONFIG_ESP32_RTCDATA_IN_FAST_MEM
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REGION_ALIAS("rtc_data_location", rtc_slow_seg );
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#else
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REGION_ALIAS("rtc_data_location", rtc_data_seg );
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#endif
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