mirror of
https://github.com/espressif/esp-idf
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194 lines
7.0 KiB
C
194 lines
7.0 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_DPORT_REG_H_
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#define _SOC_DPORT_REG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include"extmem_reg.h"
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#include"interrupt_reg.h"
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#include"system_reg.h"
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#include "sensitive_reg.h"
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#include "soc.h"
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/*IRAM0 connected with Cache IBUS0*/
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#define IRAM0_ADDRESS_LOW 0x40000000
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#define IRAM0_ADDRESS_HIGH 0x40400000
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#define IRAM0_CACHE_ADDRESS_LOW 0x40080000
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#define IRAM0_CACHE_ADDRESS_HIGH 0x40400000
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/*IRAM1 and AHB_IBUS1 connected with Cache IBUS1, alternative*/
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#define IRAM1_ADDRESS_LOW 0x40400000
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#define IRAM1_ADDRESS_HIGH 0x40800000
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#define AHB_IBUS1_ADDRESS_LOW 0x60400000
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#define AHB_IBUS1_ADDRESS_HIGH 0x60800000
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/*IROM0 and AHB_IBUS2 connected with Cache IBUS2, alternative*/
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#define IROM0_ADDRESS_LOW 0x40800000
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#define IROM0_ADDRESS_HIGH 0x40c00000
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#define AHB_IBUS2_ADDRESS_LOW 0x60800000
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#define AHB_IBUS2_ADDRESS_HIGH 0x60c00000
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/*DROM0 and AHB_IBUS2 connected with Cache IBUS3, alternative*/
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/*DROM0 and AHB_DBUS2 connected with Cache DBUS3, alternative*/
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#define DROM0_ADDRESS_LOW 0x3f000000
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#define DROM0_ADDRESS_HIGH 0x3f400000
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#define AHB_IBUS3_ADDRESS_LOW 0x60c00000
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#define AHB_IBUS3_ADDRESS_HIGH 0x61000000
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#define AHB_DBUS3_ADDRESS_LOW 0x61800000
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#define AHB_DBUS3_ADDRESS_HIGH 0x61c00000
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/*DRAM0 and AHB_DBUS2 connected with Cache DBUS0, alternative*/
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#define DRAM0_ADDRESS_LOW 0x3fc00000
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#define DRAM0_ADDRESS_HIGH 0x40000000
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#define DRAM0_CACHE_ADDRESS_LOW 0x3fc00000
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#define DRAM0_CACHE_ADDRESS_HIGH 0x3ff90000
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#define AHB_DBUS0_ADDRESS_LOW 0x61000000
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#define AHB_DBUS0_ADDRESS_HIGH 0x61400000
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/*DRAM1 connected with Cache DBUS1*/
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#define DRAM1_ADDRESS_LOW 0x3f800000
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#define DRAM1_ADDRESS_HIGH 0x3fc00000
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/*DPORT and AHB_DBUS2 connected with Cache DBUS2, alternative*/
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#define DPORT_ADDRESS_LOW 0x3f400000
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#define DPORT_ADDRESS_HIGH 0x3f800000
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#define DPORT_CACHE_ADDRESS_LOW 0x3f500000
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#define DPORT_CACHE_ADDRESS_HIGH 0x3f800000
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#define AHB_DBUS2_ADDRESS_LOW 0x61400000
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#define AHB_DBUS2_ADDRESS_HIGH 0x61800000
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#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
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#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
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#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
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#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
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#define ADDRESS_IN_IRAM1(vaddr) ADDRESS_IN_BUS(IRAM1, vaddr)
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#define ADDRESS_IN_AHB_IBUS1(vaddr) ADDRESS_IN_BUS(AHB_IBUS1, vaddr)
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#define ADDRESS_IN_IROM0(vaddr) ADDRESS_IN_BUS(IROM0, vaddr)
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#define ADDRESS_IN_AHB_IBUS2(vaddr) ADDRESS_IN_BUS(AHB_IBUS2, vaddr)
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#define ADDRESS_IN_DROM0(vaddr) ADDRESS_IN_BUS(DROM0, vaddr)
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#define ADDRESS_IN_AHB_IBUS3(vaddr) ADDRESS_IN_BUS(AHB_IBUS3, vaddr)
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#define ADDRESS_IN_AHB_DBUS3(vaddr) ADDRESS_IN_BUS(AHB_DBUS3, vaddr)
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#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
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#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
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#define ADDRESS_IN_AHB_DBUS0(vaddr) ADDRESS_IN_BUS(AHB_DBUS0, vaddr)
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#define ADDRESS_IN_DRAM1(vaddr) ADDRESS_IN_BUS(DRAM1, vaddr)
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#define ADDRESS_IN_DPORT(vaddr) ADDRESS_IN_BUS(DPORT, vaddr)
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#define ADDRESS_IN_DPORT_CACHE(vaddr) ADDRESS_IN_BUS(DPORT_CACHE, vaddr)
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#define ADDRESS_IN_AHB_DBUS2(vaddr) ADDRESS_IN_BUS(AHB_DBUS2, vaddr)
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#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
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#define BUS_IRAM1_CACHE_SIZE BUS_SIZE(IRAM1)
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#define BUS_IROM0_CACHE_SIZE BUS_SIZE(IROM0)
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#define BUS_DROM0_CACHE_SIZE BUS_SIZE(DROM0)
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#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
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#define BUS_DRAM1_CACHE_SIZE BUS_SIZE(DRAM1)
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#define BUS_DPORT_CACHE_SIZE BUS_SIZE(DPORT)
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#define BUS_AHB_IBUS1_CACHE_SIZE BUS_SIZE(AHB_IBUS1)
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#define BUS_AHB_IBUS2_CACHE_SIZE BUS_SIZE(AHB_IBUS2)
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#define BUS_AHB_IBUS3_CACHE_SIZE BUS_SIZE(AHB_IBUS3)
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#define BUS_AHB_DBUS0_CACHE_SIZE BUS_SIZE(AHB_DBUS0)
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#define BUS_AHB_DBUS2_CACHE_SIZE BUS_SIZE(AHB_DBUS2)
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#define BUS_AHB_DBUS3_CACHE_SIZE BUS_SIZE(AHB_DBUS3)
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#define PRO_CACHE_IBUS0 0
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#define PRO_CACHE_IBUS0_MMU_START 0
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#define PRO_CACHE_IBUS0_MMU_END 0x100
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#define PRO_CACHE_IBUS1 1
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#define PRO_CACHE_IBUS1_MMU_START 0x100
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#define PRO_CACHE_IBUS1_MMU_END 0x200
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#define PRO_CACHE_IBUS2 2
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#define PRO_CACHE_IBUS2_MMU_START 0x200
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#define PRO_CACHE_IBUS2_MMU_END 0x300
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#define PRO_CACHE_IBUS3 3
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#define PRO_CACHE_IBUS3_MMU_START 0x300
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#define PRO_CACHE_IBUS3_MMU_END 0x400
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#define PRO_CACHE_DBUS0 4
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#define PRO_CACHE_DBUS0_MMU_START 0x400
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#define PRO_CACHE_DBUS0_MMU_END 0x500
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#define PRO_CACHE_DBUS1 5
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#define PRO_CACHE_DBUS1_MMU_START 0x500
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#define PRO_CACHE_DBUS1_MMU_END 0x600
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#define PRO_CACHE_DBUS2 6
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#define PRO_CACHE_DBUS2_MMU_START 0x600
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#define PRO_CACHE_DBUS2_MMU_END 0x700
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#define PRO_CACHE_DBUS3 7
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#define PRO_CACHE_DBUS3_MMU_START 0x700
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#define PRO_CACHE_DBUS3_MMU_END 0x800
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#define DPORT_MMU_SIZE 0x800
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#define DPORT_ICACHE_MMU_SIZE 0x400
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#define DPORT_DCACHE_MMU_SIZE 0x400
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#define DPORT_MMU_BUS_START(i) ((i) * 0x100)
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#define DPORT_MMU_BUS_SIZE 0x100
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#define DPORT_MMU_INVALID BIT(14)
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#define DPORT_MMU_ACCESS_FLASH BIT(15)
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#define DPORT_MMU_ACCESS_SPIRAM BIT(16)
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/* Flash MMU table for PRO CPU */
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#define DPORT_PRO_FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
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#define DPORT_FLASH_MMU_TABLE_SIZE (DPORT_ICACHE_MMU_SIZE/sizeof(uint32_t))
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#define DPORT_MMU_TABLE_INVALID_VAL 0x4000
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#define DPORT_FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
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#define DPORT_MMU_ADDRESS_MASK 0x3fff
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#define BUS_ADDR_SIZE 0x400000
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#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
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#define BUS_NUM_MASK 0x3
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#define CACHE_MEMORY_BLOCK_SIZE 8192
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#define CACHE_MEMORY_BLOCK_NUM 4
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#define CACHE_MEMORY_BLOCK_NUM_MASK 0x3
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#define CACHE_MEMORY_LAYOUT_SHIFT 4
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#define CACHE_MEMORY_LAYOUT_SHIFT0 0
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#define CACHE_MEMORY_LAYOUT_SHIFT1 4
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#define CACHE_MEMORY_LAYOUT_SHIFT2 8
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#define CACHE_MEMORY_LAYOUT_SHIFT3 12
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#define CACHE_MEMORY_LAYOUT_MASK 0xf
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#define CACHE_MEMORY_BLOCK0_ADDR 0x40020000
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#define CACHE_MEMORY_BLOCK1_ADDR 0x40022000
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#define CACHE_MEMORY_BLOCK2_ADDR 0x40024000
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#define CACHE_MEMORY_BLOCK3_ADDR 0x40026000
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#define DPORT_DATE_REG SYSTEM_DATE_REG
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#ifndef __ASSEMBLER__
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#include "dport_access.h"
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /*_SOC_DPORT_REG_H_ */
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