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update reset reason for c3/s3/h2

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wuzhenghui 2021-08-11 17:35:21 +08:00 committed by Michael (XIAO Xufeng)
parent 673d0371ba
commit 1ef989a1b5
2 changed files with 9 additions and 2 deletions
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8
components/esp_rom/include/esp32c3/rom/rtc.h
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@ -82,8 +82,7 @@ typedef enum {
NO_MEAN = 0,
POWERON_RESET = 1, /**<1, Vbat power on reset*/
RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/
DEEPSLEEP_RESET = 5, /**<3, Deep Sleep reset digital core*/
SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core*/
DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core*/
TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core*/
RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
@ -95,6 +94,11 @@ typedef enum {
RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
EFUSE_RESET = 20, /**<20, efuse reset digital core*/
USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */
USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */
POWER_GLITCH_RESET = 23, /**<23, power glitch reset digital core and rtc module*/
} RESET_REASON;
typedef enum {

3
components/esp_rom/include/esp32s3/rom/rtc.h
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@ -90,6 +90,9 @@ typedef enum {
SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
EFUSE_RESET = 20, /**<20, efuse reset digital core*/
USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core */
USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core */
POWER_GLITCH_RESET = 23, /**<23, power glitch reset digital core and rtc module*/
} RESET_REASON;
typedef enum {