blackbeard420/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf synced 2025-03-10 01:29:21 -04:00
Code Issues Projects Releases Wiki Activity

Merge branch 'fix/remove_esp32c6_h2_solved_todos' into 'master'

Browse Source 
change(esp_hw_support): remove esp32c6 & esp32h2 solved todos

Closes IDF-5781 and IDF-6254

See merge request espressif/esp-idf!31401
This commit is contained in:
Wu Zheng Hui 2024-06-24 13:35:04 +08:00
commit 2d36e81ccd
12 changed files with 15 additions and 88 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
components/bootloader_support/src/bootloader_clock_init.c
View File

@ -66,19 +66,22 @@ __attribute__((weak)) void bootloader_clock_configure(void)
} }
#endif #endif
//TODO: [ESP32C61] IDF-9274, basic rtc support
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
// TODO: IDF-5781 Some of esp32c6 SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue
// Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader
clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST;
#else
// Use RTC_FAST clock source sel register field's default value, XTAL_DIV, for 2nd stage bootloader // Use RTC_FAST clock source sel register field's default value, XTAL_DIV, for 2nd stage bootloader
// RTC_FAST clock source will be switched to RC_FAST at application startup // RTC_FAST clock source will be switched to RC_FAST at application startup
clk_cfg.fast_clk_src = rtc_clk_fast_src_get(); clk_cfg.fast_clk_src = rtc_clk_fast_src_get();
if (clk_cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_INVALID) { if (clk_cfg.fast_clk_src == SOC_RTC_FAST_CLK_SRC_INVALID) {
clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_XTAL_DIV; clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_XTAL_DIV;
} }
#if CONFIG_IDF_TARGET_ESP32C6
if (efuse_hal_chip_revision() == 0) {
// Some of ESP32C6-ECO0 chip's SOC_RTC_FAST_CLK_SRC_XTAL_D2 rtc_fast clock has timing issue,
// which will cause the chip to be unable to capture the reset reason when it is reset.
// Force to use SOC_RTC_FAST_CLK_SRC_RC_FAST since 2nd stage bootloader
clk_cfg.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST;
}
#endif #endif
rtc_clk_init(clk_cfg); rtc_clk_init(clk_cfg);
} }

9
components/esp_hw_support/port/esp32c5/include/soc/rtc.h
View File

@ -405,15 +405,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
*/ */
uint64_t rtc_time_get(void); uint64_t rtc_time_get(void);
/**
* @brief Busy loop until next RTC_SLOW_CLK cycle
*
* This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
* In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
* one RTC_SLOW_CLK cycle later.
*/
void rtc_clk_wait_for_slow_cycle(void);
/** /**
* @brief Enable the rtc digital 8M clock * @brief Enable the rtc digital 8M clock
* *

8
components/esp_hw_support/port/esp32c5/rtc_time.c
View File

@ -18,7 +18,7 @@
#include "soc/chip_revision.h" #include "soc/chip_revision.h"
#include "esp_private/periph_ctrl.h" #include "esp_private/periph_ctrl.h"
static const char *TAG = "rtc_time"; __attribute__((unused)) static const char *TAG = "rtc_time";
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of * This feature counts the number of XTAL clock cycles within a given number of
@ -250,12 +250,6 @@ uint64_t rtc_time_get(void)
return 0; return 0;
} }
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
{
// TODO: IDF-5781
ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val) uint32_t rtc_clk_freq_cal(uint32_t cal_val)
{ {
if (cal_val == 0) { if (cal_val == 0) {

9
components/esp_hw_support/port/esp32c6/include/soc/rtc.h
View File

@ -413,15 +413,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
*/ */
uint64_t rtc_time_get(void); uint64_t rtc_time_get(void);
/**
* @brief Busy loop until next RTC_SLOW_CLK cycle
*
* This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
* In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
* one RTC_SLOW_CLK cycle later.
*/
void rtc_clk_wait_for_slow_cycle(void);
/** /**
* @brief Enable the rtc digital 8M clock * @brief Enable the rtc digital 8M clock
* *

8
components/esp_hw_support/port/esp32c6/rtc_time.c
View File

@ -18,7 +18,7 @@
#include "soc/chip_revision.h" #include "soc/chip_revision.h"
#include "esp_private/periph_ctrl.h" #include "esp_private/periph_ctrl.h"
static const char *TAG = "rtc_time"; __attribute__((unused)) static const char *TAG = "rtc_time";
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of * This feature counts the number of XTAL clock cycles within a given number of
@ -257,12 +257,6 @@ uint64_t rtc_time_get(void)
return lp_timer_hal_get_cycle_count(); return lp_timer_hal_get_cycle_count();
} }
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
{
// TODO: IDF-5781
ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val) uint32_t rtc_clk_freq_cal(uint32_t cal_val)
{ {
if (cal_val == 0) { if (cal_val == 0) {

9
components/esp_hw_support/port/esp32c61/include/soc/rtc.h
View File

@ -413,15 +413,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
*/ */
uint64_t rtc_time_get(void); uint64_t rtc_time_get(void);
/**
* @brief Busy loop until next RTC_SLOW_CLK cycle
*
* This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
* In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
* one RTC_SLOW_CLK cycle later.
*/
void rtc_clk_wait_for_slow_cycle(void);
/** /**
* @brief Enable the rtc digital 8M clock * @brief Enable the rtc digital 8M clock
* *

8
components/esp_hw_support/port/esp32c61/rtc_time.c
View File

@ -17,7 +17,7 @@
#include "soc/chip_revision.h" #include "soc/chip_revision.h"
#include "esp_private/periph_ctrl.h" #include "esp_private/periph_ctrl.h"
static const char *TAG = "rtc_time"; __attribute__((unused)) static const char *TAG = "rtc_time";
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of * This feature counts the number of XTAL clock cycles within a given number of
@ -254,12 +254,6 @@ uint64_t rtc_time_get(void)
return 0; return 0;
} }
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
{
// TODO: IDF-5781
ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val) uint32_t rtc_clk_freq_cal(uint32_t cal_val)
{ {
if (cal_val == 0) { if (cal_val == 0) {

9
components/esp_hw_support/port/esp32h2/include/soc/rtc.h
View File

@ -411,15 +411,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
*/ */
uint64_t rtc_time_get(void); uint64_t rtc_time_get(void);
/**
* @brief Busy loop until next RTC_SLOW_CLK cycle
*
* This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
* In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
* one RTC_SLOW_CLK cycle later.
*/
void rtc_clk_wait_for_slow_cycle(void);
/** /**
* @brief Enable the rtc digital 8M clock * @brief Enable the rtc digital 8M clock
* *

1
components/esp_hw_support/port/esp32h2/pmu_param.c
View File

@ -22,7 +22,6 @@ static __attribute__((unused)) const char *TAG = "pmu_param";
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
#endif #endif
//TODO: IDF-6254
#define PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT() { \ #define PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT() { \
.dig_power = { \ .dig_power = { \
.vdd_spi_pd_en = 0, \ .vdd_spi_pd_en = 0, \

8
components/esp_hw_support/port/esp32h2/rtc_time.c
View File

@ -18,7 +18,7 @@
#include "soc/chip_revision.h" #include "soc/chip_revision.h"
#include "esp_private/periph_ctrl.h" #include "esp_private/periph_ctrl.h"
static const char *TAG = "rtc_time"; __attribute__((unused)) static const char *TAG = "rtc_time";
/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0. /* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of * This feature counts the number of XTAL clock cycles within a given number of
@ -257,12 +257,6 @@ uint64_t rtc_time_get(void)
return lp_timer_hal_get_cycle_count(); return lp_timer_hal_get_cycle_count();
} }
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
{
// TODO: IDF-6254
ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val) uint32_t rtc_clk_freq_cal(uint32_t cal_val)
{ {
if (cal_val == 0) { if (cal_val == 0) {

11
components/esp_hw_support/port/esp32p4/include/soc/rtc.h
View File

@ -432,15 +432,6 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
*/ */
uint64_t rtc_time_get(void); uint64_t rtc_time_get(void);
/**
* @brief Busy loop until next RTC_SLOW_CLK cycle
*
* This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
* In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
* one RTC_SLOW_CLK cycle later.
*/
void rtc_clk_wait_for_slow_cycle(void);
/** /**
* @brief Enable the rtc digital 8M clock * @brief Enable the rtc digital 8M clock
* *
@ -494,7 +485,7 @@ void rtc_clk_apll_enable(bool enable);
* *
* @return * @return
* - 0 Failed * - 0 Failed
* - else Sucess * - else Success
*/ */
uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm0, uint32_t *_sdm1, uint32_t *_sdm2); uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm0, uint32_t *_sdm1, uint32_t *_sdm2);

8
components/esp_hw_support/port/esp32p4/rtc_time.c
View File

@ -16,7 +16,7 @@
#include "esp_rom_sys.h" #include "esp_rom_sys.h"
#include "esp_private/periph_ctrl.h" #include "esp_private/periph_ctrl.h"
static const char *TAG = "rtc_time"; __attribute__((unused)) static const char *TAG = "rtc_time";
/* Calibration of clock frequency is performed using a special feature of TIMG0. /* Calibration of clock frequency is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of * This feature counts the number of XTAL clock cycles within a given number of
@ -214,12 +214,6 @@ uint64_t rtc_time_get(void)
return lp_timer_hal_get_cycle_count(); return lp_timer_hal_get_cycle_count();
} }
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
{
// TODO: IDF-5781
ESP_EARLY_LOGW(TAG, "rtc_clk_wait_for_slow_cycle() has not been implemented yet");
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val) uint32_t rtc_clk_freq_cal(uint32_t cal_val)
{ {
if (cal_val == 0) { if (cal_val == 0) {