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fix: fix s3 bbpll cali fail bug

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hongshuqing 2024-02-19 14:33:40 +08:00
parent 2769144e64
commit 64a99ef412
1 changed files with 1 additions and 7 deletions
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8
components/hal/esp32s3/include/hal/clk_tree_ll.h
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@ -305,7 +305,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
uint8_t dr3;
uint8_t dchgp;
uint8_t dcur;
uint8_t dbias;
uint8_t dbias = 3;
if (pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) {
/* Configure 480M PLL */
@ -317,7 +317,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
case RTC_XTAL_FREQ_32M:
div_ref = 1;
@ -326,7 +325,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dr3 = 1;
dchgp = 4;
dcur = 0;
dbias = 2;
break;
default:
div_ref = 0;
@ -335,7 +333,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
}
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B);
@ -349,7 +346,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
case RTC_XTAL_FREQ_32M:
div_ref = 1;
@ -358,7 +354,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
default:
div_ref = 0;
@ -367,7 +362,6 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dr3 = 0;
dchgp = 5;
dcur = 3;
dbias = 2;
break;
}
REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);