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Merge branch 'bugfix/idf-11064_v5.4' into 'release/v5.4'

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backport v5.4: fix some issues on esp32c5 eco1

See merge request espressif/esp-idf!34790
This commit is contained in:
Jiang Jiang Jian 2024-11-20 19:38:13 +08:00
commit 914a4810a9
5 changed files with 30 additions and 7 deletions
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18
components/esp_hw_support/lowpower/port/esp32c5/sleep_clock.c
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@ -10,6 +10,8 @@
#include "modem/modem_syscon_reg.h"
#include "modem/modem_lpcon_reg.h"
#include "soc/i2c_ana_mst_reg.h"
#include "soc/chip_revision.h"
#include "hal/efuse_hal.h"
static const char *TAG = "sleep_clock";
@ -35,7 +37,6 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP && CONFIG_XTAL_FREQ_AUTO
uint32_t xtal_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
if (xtal_freq_mhz == SOC_XTAL_FREQ_48M) {
/* For the 48 MHz main XTAL, we need regdma to configured BBPLL by exec
* the PHY_I2C_MST_CMD_TYPE_BBPLL_CFG command from PHY i2c master
* command memory */
@ -52,6 +53,21 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
}
#endif
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
/* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG (it's located
* in TOP domain) is used to fix the issue where the modem module fails
* to transmit and receive packets due to the loss of The modem root clock
* caused by automatic clock gating during soc root clock source switching.
* For detailed information, refer to IDF-11064 */
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
const static sleep_retention_entries_config_t rootclk_workaround[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(9), PCR_FPGA_DEBUG_REG, PCR_FPGA_DEBUG_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(1) }
};
err = sleep_retention_entries_create(rootclk_workaround, ARRAY_SIZE(rootclk_workaround), 1, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem root clock workaround, 1 level priority");
}
#endif
ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
return ESP_OK;
}

3
components/esp_hw_support/port/esp32c5/rtc_clk.c
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@ -268,7 +268,8 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
} else if (freq_mhz == 80) {
real_freq_mhz = freq_mhz;
if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
// ESP32C5 has a root clock ICG issue when switching SOC_CPU_CLK_SRC from PLL_F160M to PLL_F240M
/* ESP32C5 has a root clock ICG issue when switching SOC_CPU_CLK_SRC from PLL_F160M to PLL_F240M
* For detailed information, refer to IDF-11064 */
source = SOC_CPU_CLK_SRC_PLL_F240M;
source_freq_mhz = CLK_LL_PLL_240M_FREQ_MHZ;
divider = 3;

11
components/esp_system/port/soc/esp32c5/clk.c
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@ -19,7 +19,9 @@
#include "soc/rtc.h"
#include "soc/rtc_periph.h"
#include "soc/i2s_reg.h"
#include "soc/chip_revision.h"
#include "esp_cpu.h"
#include "hal/efuse_hal.h"
#include "hal/wdt_hal.h"
#if SOC_MODEM_CLOCK_SUPPORTED
#include "hal/modem_lpcon_ll.h"
@ -215,6 +217,15 @@ __attribute__((weak)) void esp_perip_clk_init(void)
modem_clock_select_lp_clock_source(PERIPH_WIFI_MODULE, modem_lpclk_src, 0);
#endif
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
/* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG is used to fix
* the issue where the modem module fails to transmit and receive packets
* due to the loss of the modem root clock caused by automatic clock gating
* during soc root clock source switching. For detailed information, refer
* to IDF-11064. */
REG_CLR_BIT(PCR_FPGA_DEBUG_REG, BIT(31));
}
ESP_EARLY_LOGW(TAG, "esp_perip_clk_init() has not been implemented yet");
#if 0 // TODO: [ESP32C5] IDF-8844
uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;

4
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@ -1379,10 +1379,6 @@ config SOC_PM_MODEM_RETENTION_BY_REGDMA
bool
default y
config SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD
bool
default y
config SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN
bool
default y

1
components/soc/esp32c5/include/soc/soc_caps.h
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@ -578,7 +578,6 @@
#define SOC_PM_CPU_RETENTION_BY_SW (1)
#define SOC_PM_MODEM_RETENTION_BY_REGDMA (1)
#define SOC_PM_MMU_TABLE_RETENTION_WHEN_TOP_PD (1)
#define SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN (1)
#define SOC_PM_PAU_LINK_NUM (5)