78 Commits

Author SHA1 Message Date
igor.udot
daf2d31008 test: format all test scripts 2025-03-05 12:08:48 +08:00
Armando
fd09700aab test(mmu): added test for checking esp_mmu_vaddr_to_paddr with psram vaddrs 2025-02-17 16:15:09 +08:00
Armando
299d8115ed fix(mmu): fixed esp_mmu_vaddr_to_paddr cannot figure out psram vaddr issue on esp32p4 2025-02-17 16:15:09 +08:00
Chen Ji Chang
9342b3fba1 Merge branch 'feat/h4_introduce_step1_add_target' into 'master'
feat(esp32h4): introduce target esp32h4(stage 1)

See merge request espressif/esp-idf!36780
2025-02-11 18:11:08 +08:00
morris
88e3ea2ea5 Merge branch 'bugfix/cache_invalidate_should_respect_size' into 'master'
bugfix(cache): cache invalidate operation should respect the cache line size

See merge request espressif/esp-idf!36805
2025-02-11 11:47:22 +08:00
morris
5558028870 bugfix(cache): cache invalidate operation should respect the cache line size
not only the buffer address but also the buffer size should aligned to
the cache line size
2025-02-10 17:48:46 +08:00
Armando
462c9f2510 test(mmu): test can find paddr caps by any paddr offset 2025-02-10 17:12:51 +08:00
Armando
cdaf777b22 feat(mmu): supported find paddr caps by any paddr offset
Closes https://github.com/espressif/esp-idf/issues/14988
2025-02-10 15:07:47 +08:00
Chen Jichang
6f83f39dce feat(esp32h4): introduce target esp32h4(stage 1) 2025-02-08 17:07:44 +08:00
gaoxu
5ef4f20778 feat(esp32h21): disable unsupported build test 2025-02-06 15:47:51 +08:00
Song Ruo Jing
20eb6ca5e9 feat(heap): add a MALLOC_CAP_SIMD flag
MALLOC_CAP_SIMD can be used to allocate memory to be used for SIMD instructions
2025-01-16 14:39:12 +08:00
morris
c8d4e1b094 Merge branch 'feature/bitscrambler_support' into 'master'
feature(driver): BitScrambler loopback support

See merge request espressif/esp-idf!31236
2025-01-03 16:08:52 +08:00
gaoxu
25731d0c1e feat(esp32h21): finnal introduce hello world support 2024-12-30 20:14:40 +08:00
Jeroen Domburg
a88e719e33 feat(driver): BitScrambler support
This adds an assembler for the BitScrambler assembly language,
plus unit tests for it. It also adds the loopback driver,
which can do BitScrambler operations on memory-to-memory
transfers. Documentation is also included.
2024-12-30 09:39:23 +08:00
Laukik Hase
733741bbac
feat(esp_tee): Support for ESP-TEE - esp_system component 2024-12-02 12:20:04 +05:30
gaoxu
64bbb53b8f feat(esp32h21): introduce target esp32h21(stage 1) 2024-11-12 15:42:27 +08:00
Alexey Gerenkov
391dd7b9ad fix(build): Fix declaration of linker labels for ROM reserved regions
It looks like as a part of optimization for inlined functions like 'mmu_ll_vaddr_to_laddr' Clang aligns constant value
used for bitwise AND operation with the pointer to external symbol passed to the function as parameter.
That led to assertion failures because boundaries can be unaligned to 4 bytes.
2024-09-18 21:40:39 +03:00
Marius Vikhammer
0d140f38ea fix(system): fixed warnings related to ununsed var if asserts disabled 2024-08-26 10:25:04 +08:00
C.S.M
7c08d417d2 fix(mmu_map): make a static function force inline in order not be put in flash 2024-08-02 15:51:22 +08:00
Armando
67b8dbb5e5 feat(cache): supported cache on c61 2024-08-01 09:34:18 +08:00
Armando (Dou Yiwen)
23ee0b65ff Merge branch 'feat/cache_msync_c2m_sliced_ops' into 'master'
cache: supported msync c2m sliced ops

Closes IDF-10510 and IDF-10414

See merge request espressif/esp-idf!32155
2024-07-29 11:37:24 +08:00
Armando
074ed08251 change(cache): added mutex to guarantee the atomicity
This mutex is only added when msync is called from the task. This means only one task will compete with the msync-calls from ISRs.
2024-07-25 14:25:19 +08:00
Armando
3bfc134a23 feat(cache): supported msync c2m sliced ops
This commit adds sliced C2M ops, when the msync is called in task. This way it gives a breath of the critical section, so that a long C2M operation will not disable interrupts for a long time
2024-07-25 14:25:19 +08:00
wanlei
3cf069c7d8 feat(esp32c61): disable unsupported build test 2024-07-16 16:06:19 +08:00
Mahavir Jain
f5349ca342
fix(esp_mm): for existing mmap region, consider new offset for virtual addr
While returning virtual address for existing memory mapped region, newly
supplied offset from the physical address was not getting considered.

This was a regression present from ESP-IDF 5.1 release.

Added test case in spi_flash component that fails without this fix.

Closes https://github.com/espressif/esp-idf/issues/13929
2024-07-10 15:54:36 +05:30
Alexey Lapshin
ed6e497c6f feat(build): add COMPILER_STATIC_ANALYZER option 2024-06-18 14:25:37 +08:00
Alexey Lapshin
505647292d fix(esp_mm): fix warnings found by GNU static analyzer 2024-06-18 14:25:37 +08:00
Jeroen Domburg
a1ba660b4a change(system): heap_caps_alloc returns aligned memory if caps indicate a need for it
The implicit promise of heap_alloc_caps() and friends is that the memory it
returns is fit for the purpose as requested in the caps field. Before
this commit, that did not happen; e.g. DMA-capable memory wass returned
from a correct region, but not aligned/sized to something the DMA subsystem
can handle.

This commit adds an API to the esp_mm component that is then used by the
heap component to adjust allocation alignment, caps and size dependent on
the hardware requirement of the requested allocation caps.
2024-05-27 12:41:18 +08:00
Armando
10d3912c70 feat(xip_psram): support xip psram feature on esp32p4 2024-05-22 15:56:07 +08:00
Armando
e36a396801 change(test): test changes for esp cache malloc 2024-04-15 15:34:51 +08:00
Armando
0df418facd change(cache): update to use heap cap malloc flags 2024-04-15 15:34:51 +08:00
Armando
b658c712e7 change(cache): change esp_cache_aligned_alloc_log_e_to_w 2024-04-15 09:49:25 +08:00
laokaiyao
65b1fd33d3 ci(esp32c5mp): disable the unsupported tests 2024-04-07 12:13:29 +08:00
Armando
f0518b3c16 feat(dma): advanced dma malloc helper 2024-04-02 14:30:14 +08:00
wanlei
20c18ac52b feat(esp32c61): final introduce helloworld support 2024-04-02 10:50:52 +08:00
Armando
be5af1c737 test(cache): added test for cache_prefer_m/calloc 2024-03-26 18:03:15 +08:00
Armando
de70ed1c84 feat(cache): added cache_prefer_m/calloc 2024-03-26 18:03:15 +08:00
Armando
905b427479 test(cache): added test for M2C with ESP_CACHE_MSYNC_FLAG_UNALIGNED 2024-03-22 15:38:50 +08:00
Armando
9e36994a7b bugfix(cache): don't allow M2C direction ESP_CACHE_MSYNC_FLAG_UNALIGNED 2024-03-22 15:38:50 +08:00
laokaiyao
c9d6a11d1d feat(esp32c5mp): support to run hello world on esp32c5 mp 2024-03-21 16:18:03 +08:00
Konstantin Kondrashov
3f89072af1 feat(all): Use PRIx macro in all logs 2024-03-12 11:15:53 +02:00
wanlei
ee02b71f1c feat(esp32c61): introduce target esp32c61 2024-03-01 21:12:25 +08:00
laokaiyao
11e19f40b9 feat(esp32c5): support to build hello world on esp32c5 beta3 2024-01-09 13:11:11 +08:00
Darian
cc34c4fc08 Merge branch 'contrib/github_pr_12481' into 'master'
Many places in the ESP_SYSTEM are using CONFIG_FREERTOS_UNICORE instead of CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE (GitHub PR)

Closes IDFGH-11333

See merge request espressif/esp-idf!27435
2023-12-01 19:33:19 +08:00
laokaiyao
bb0879b3f8 feat(esp32c5): introduce target esp32c5 2023-11-28 16:14:17 +08:00
fl0wl0w
d149c1b26f Use configuration option instead of in components not related to FreeRTOS
Mergeshttps://github.com/espressif/esp-idf/pull/12481
2023-11-28 07:49:20 +00:00
Jakob Hasse
548022fbe6 refactor(linux): excluded all non-Linux components from build
* All components which won't build (yet) on Linux are excluded.
  This enables switching to Linux in an application without
  explicitly setting COMPONENTS to main in the main
  CMakeLists.txt.
* ESP Timer provides headers for Linux now
* automatically disabling LWIP in Kconfig if it is not available

doc(linux): brought section
  "Component Linux/Mock Support Overview" up to date
2023-10-16 17:06:54 +08:00
Armando
1f8f0a5285 feat(cache): added private API to get cache alignment requirements 2023-10-10 18:09:01 +08:00
Armando
fc4b9d9507 refactor(esp_mm): reformat code with astyle_py 2 2023-10-09 15:29:31 +08:00
Armando
3d4b60afc0 refactor(esp_mm): reformat code with astyle_py 2023-10-08 10:36:04 +08:00