morris
92b25c06b3
Merge branch 'bugfix/fix_incorrect_regbase_name_of_i2s_v5.1' into 'release/v5.1'
...
fix(i2s): fixed incorrect reg base name on C3 (v5.1)
See merge request espressif/esp-idf!28630
2024-02-28 11:41:58 +08:00
Mahavir Jain
614ad494f6
fix(soc): change debug addr range to CPU subsystem range
...
For C6/H2/P4/C5, there is no SoC specific debug range. Instead the same
address range is part of CPU Subsystem range which contains debug mode
specific code and interrupt config registers (CLINT, PLIC etc.).
For now the PMP entry is provided with RWX permission for both machine
and user mode but we can save this entry and allow the access to only
machine mode for this range.
For P4/C5 case, this PMP entry can have RW permission as the debug mode
specific code is not present in this memory range.
2024-01-24 12:52:27 +05:30
laokaiyao
d7b6ebe7df
fix(i2s): fixed incorrect reg base name on C3
...
Closes https://github.com/espressif/esp-idf/issues/12643
2024-01-23 12:05:45 +08:00
Marius Vikhammer
40bea117e4
Merge branch 'bugfix/s3_irom_addr_v5.1' into 'release/v5.1'
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soc: fix SOC_IROM_MASK_HIGH for esp32s3 (v5.1)
See merge request espressif/esp-idf!27136
2023-12-20 10:00:39 +08:00
TD-er
8e0d64e94c
fix(spi): Correct REG_SPI_BASE(i) macro for all targets
...
The existing formula can never match these registers.
Closes https://github.com/espressif/esp-idf/pull/12559
Closes https://github.com/espressif/esp-idf/pull/12562
2023-12-06 16:13:01 +08:00
Ivan Grokhotkov
c43b66cd35
fix(soc): update SOC_IROM_MASK_HIGH for esp32, c6, h2 for consistency
2023-11-14 14:27:24 +01:00
zlq
7bbe19d92f
feat(volt): chip auto adjust volt for esp32c6 & esp32h2
2023-09-27 06:39:59 +00:00
wuzhenghui
5f6f20ea30
fix(esp_pm): fix bad apb_max_freq for 26mhz esp32c2
2023-07-25 13:54:24 +08:00
wuzhenghui
e0e4642ff8
Revert "fix(esp_pm): Constrains the minimum frequency of APB_MAX when the modem is working"
...
This reverts commit 9158cba846dcebbe7ee29ecbb51be1fc8a82c96d.
2023-07-25 13:51:37 +08:00
wuzhenghui
9158cba846
fix(esp_pm): Constrains the minimum frequency of APB_MAX when the modem is working
2023-07-15 01:56:55 +08:00
Mahavir Jain
b29ed0ba0b
test_apps: enable memprot tests for ESP32-H2 target
2023-03-15 13:16:26 +05:30
Armando
c56eb8646b
g0: resolve MMU_PAGE_SIZE not defined in g0 build issue
2023-02-22 12:37:40 +08:00
Song Ruo Jing
2c2a62e323
clk_tree: Add basic clock support for esp32h2
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- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
Remove FPGA build for esp32h2
2023-02-20 17:15:02 +08:00
Armando
06e7c02da7
esp_mm: h2 support
2023-02-07 20:23:53 +08:00
Song Ruo Jing
b72d759290
uart: Add support for esp32h2
2023-02-06 00:48:04 +08:00
morris
774a05399b
soc: fix wrong APB_CLK_FREQ value on esp32c6
2023-01-28 06:33:23 +00:00
wuzhenghui
05e37ba214
esp32h2 memory: update esp32h2 memory layout
2023-01-06 05:30:24 +00:00
Cao Sen Miao
4713a9a7f2
ESP32H2: Introduce new chip target esp32h2, hello_world example supported
2022-12-29 12:29:14 +08:00
Cao Sen Miao
5520e3b811
ESP32H2: Add SOC files for esp32h2
2022-11-29 18:55:12 +08:00
laokaiyao
8677216576
esp32h2: renaming esp32h2 to esp32h4
2022-11-08 17:05:33 +08:00
Omar Chebib
53c7dd4efc
WDT: implement interrupt wdt and task wdt for ESP32-C2
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ESP32-C2 has a single group timer, thus it will use it for the interrupt watchdog,
which is more critical than the task watchdog. The latter is implement in
software thanks to the `esp_timer`component.
2022-09-15 14:37:59 +08:00
wuzhenghui
7cb9304b65
Clean IRAM and DRAM address space conversion macros
2022-07-29 17:07:39 +08:00
wuzhenghui
21a4eda4d4
Use the entire sharedbuffer space as the heap of the D/IRAM attribute
2022-07-29 10:51:47 +08:00
songruojing
b3d8db3ae2
bootloader, esp_system: esp32c2 console uart to support 26MHz xtal
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Gets the XTAL frequency from the RTC storage register, remove UART_CLK_FREQ_ROM macro from soc.h
2022-07-11 12:24:58 +08:00
Ivan Grokhotkov
3973db7664
soc: make register access macros compatible with C++20
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In C++20, using the result of an assignment to a 'volatile' value is
deprecated.
Breaking change: register "setter" or modification macros can no
longer be used as expressions.
Closes https://github.com/espressif/esp-idf/issues/9170
2022-06-17 18:09:22 +02:00
wuzhenghui
4652f77a7c
esp32h2beta2:update rom layout table
2022-03-29 14:13:06 +08:00
morris
24acdf23ee
soc: move peripheral base address into reg_base.h
2022-01-06 21:43:12 +08:00
Cao Sen Miao
463cf2cf1c
ESP8684: Clean up ESP8684 code, remove useless code, update headers
2021-12-09 18:36:39 +08:00
laokaiyao
f21020ce04
esp32h2: update reg and struct for beta2
2021-11-24 12:34:17 +08:00
Wu Zheng Hui
1080e4f6a2
rename APB_CTRL ro SYS_CON
...
save
2021-09-16 20:57:57 +08:00
Michael (XIAO Xufeng)
d910d42a8d
Merge branch 'bugfix/soc_interrupt_source' into 'master'
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soc: remove outdated description of interrupts on RISCV CPUs
See merge request espressif/esp-idf!14974
2021-08-30 09:38:24 +00:00
Michael (XIAO Xufeng)
59cedcb748
soc: remove outdated description of interrupts on RISCV CPUs
2021-08-30 17:38:16 +08:00
wuzhenghui
32abe5ce42
fix apb freq err temporarily
2021-08-27 19:59:33 +08:00
wuzhenghui
6ab495b4dc
esp32h2: chip env support
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brownout init fixed
2021-08-25 11:02:47 +08:00
suda-morris
9920271c21
pcnt: update pcnt soc data for all targets
2021-08-10 17:19:21 +08:00
Konstantin Kondrashov
4972605b16
esp_common: Add API for IPC to run small pieces of code on the other CPU, in the context of the level 4 interrupt
2021-08-03 14:35:29 +08:00
Shu Chen
75bd02bd46
esp32h2: add some more fixes and TODOs
2021-07-01 20:36:39 +08:00
Shu Chen
205cd469e9
esp32h2: update driver/hal/soc components to support esp32h2
2021-07-01 19:53:11 +08:00
Shu Chen
983cca8b27
esp32h2: copy driver/hal/soc components from esp32c3
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Copy the esp32c3 code without any change:
* components/driver/esp32h2
* components/esp32h2
* components/hal/esp32h2
* components/soc/esp32h2
2021-07-01 19:53:11 +08:00
