Merge branch 'lwip/ip_napt_enable_fix' into 'master'

fix(lwip): Fixed NULL pointer dereference in ip_napt_enable; add unit tests

Closes IDFGH-12823 and IDF-8155

See merge request espressif/esp-idf!36810

COMPATIBILITY.md

@@ -97,6 +97,18 @@ Supported since ESP-IDF v5.0.
 | release/v5.2           | v5.2.2+     | v5.2     |
 | release/v5.3 and above | v5.3+       | v5.3     |
 
+#### v2.0
+
+| Release branch         | Recommended | Required |
+|------------------------|-------------|----------|
+| release/v5.0           | v5.0.8+     | v5.0.8   |
+| release/v5.1           | v5.1.5+     | v5.1.5*  |
+| release/v5.2           | v5.2.4+     | v5.2.4   |
+| release/v5.3           | v5.3.2+     | v5.3.2*  |
+| release/v5.4 and above | v5.4+       | v5.4     |
+
+Note: IDF v5.1.5 and v5.3.2 are compatible with C2 v2.0. However the chip revision check hasn't been updated on these releases. Enable `ESP32C2_REV2_DEVELOPMENT` config to bypass the outdated check.
+
 ### ESP32-C6
 
 #### v0.0, v0.1
@@ -109,6 +121,16 @@ Supported since ESP-IDF v5.1.
 
 Supported since ESP-IDF v5.1.
 
+#### v1.2
+
+| Release branch         | Recommended | Required |
+|------------------------|-------------|----------|
+| release/v5.1           | v5.1.6+     | v5.1.6   |
+| release/v5.2           | v5.2.5+     | v5.2.5   |
+| release/v5.3           | v5.3.3+     | v5.3.3   |
+| release/v5.4           | v5.4.1+     | v5.4.1   |
+| release/v5.5 and above | v5.5+       | v5.5     |
+
 ## What If the ESP-IDF Version Is Lower than the `Required` Version?
 
 Latest ESP-IDF versions can prevent from downloading to, or even execute binaries on unsupported chips. ESP-IDF of versions v4.4.5+, v5.0.1+, v5.1 and above have both esptool download check and bootloader loading check against the chip revision. While ESP-IDF v4.3.5 has only esptool downloading check.

COMPATIBILITY_CN.md

@@ -97,6 +97,18 @@
 | release/v5.2           | v5.2.2+     | v5.1     |
 | release/v5.3 及以上     | v5.3+       | v5.3     |
 
+#### v2.0
+
+| 发布分支                | 推荐版本      | 需求版本  |
+|------------------------|-------------|----------|
+| release/v5.0           | v5.0.8+     | v5.0.8   |
+| release/v5.1           | v5.1.5+     | v5.1.5*  |
+| release/v5.2           | v5.2.4+     | v5.2.4   |
+| release/v5.3           | v5.3.2+     | v5.3.2*  |
+| release/v5.4 及以上     | v5.4+       | v5.4     |
+
+提示: IDF v5.1.5 及 v5.3.2 与 C2 v2.0 兼容，但芯片版本检查尚未在这些发布版本更新。使能 `ESP32C2_REV2_DEVELOPMENT` 选项来跳过这些过时的检查。
+
 ### ESP32-C6
 
 #### v0.0, v0.1
@@ -109,6 +121,16 @@
 
 从 ESP-IDF v5.1 开始支持。
 
+#### v1.2
+
+| 发布分支                | 推荐版本      | 需求版本  |
+|------------------------|-------------|----------|
+| release/v5.1           | v5.1.6+     | v5.1.6   |
+| release/v5.2           | v5.2.5+     | v5.2.5   |
+| release/v5.3           | v5.3.3+     | v5.3.3   |
+| release/v5.4           | v5.4.1+     | v5.4.1   |
+| release/v5.5 及以上     | v5.5+       | v5.5     |
+
 
 ## 如果 ESP-IDF 版本低于 `需求版本` 会出现什么情况？
 

components/bootloader_support/src/bootloader_mem.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,14 +12,12 @@
 #include "bootloader_mem.h"
 #include "esp_cpu.h"
 
-#if SOC_APM_SUPPORTED
 #include "hal/apm_hal.h"
-#endif
 
 void bootloader_init_mem(void)
 {
 
-#if !defined(BOOTLOADER_BUILD) && defined(SOC_APM_SUPPORTED)
+#if !defined(BOOTLOADER_BUILD)
     /* By default, these access path filters are enable and allow the
      * access to masters only if they are in TEE mode. Since all masters
      * except HP CPU boots in REE mode, default setting of these filters

components/bt/CMakeLists.txt

@@ -870,12 +870,27 @@ if(CONFIG_BT_ENABLED)
 
 endif()
 
+
+set(bt_priv_requires
+    nvs_flash
+    soc
+    esp_pm
+    esp_phy
+    esp_coex
+    mbedtls
+    esp_driver_uart
+    vfs
+    esp_ringbuf
+    esp_driver_spi
+    esp_driver_gpio
+    esp_gdbstub
+)
+
 idf_component_register(SRCS "${srcs}"
                        INCLUDE_DIRS "${include_dirs}"
                        PRIV_INCLUDE_DIRS "${priv_include_dirs}"
                        REQUIRES esp_timer esp_wifi
-                       PRIV_REQUIRES nvs_flash soc esp_pm esp_phy esp_coex mbedtls esp_driver_uart vfs esp_ringbuf
+                       PRIV_REQUIRES "${bt_priv_requires}"
-                                     esp_driver_spi esp_driver_gpio
                        LDFRAGMENTS "${ldscripts}")
 
 if(CONFIG_BT_ENABLED)

components/bt/Kconfig

@@ -81,8 +81,6 @@ menu "Bluetooth"
             So this option will disable the PMP (ESP_SYSTEM_PMP_IDRAM_SPLIT)
 
     menu "Common Options"
-        visible if (BT_BLUEDROID_ENABLED || BT_NIMBLE_ENABLED)
-
         source "$IDF_PATH/components/bt/common/Kconfig.in"
     endmenu
 

components/bt/common/Kconfig.in

@@ -1,6 +1,7 @@
 config BT_ALARM_MAX_NUM
     int "Maximum number of Bluetooth alarms"
     default 50
+    depends on (BT_BLUEDROID_ENABLED || BT_NIMBLE_ENABLED)
     help
         This option decides the maximum number of alarms which
         could be used by Bluetooth host.

components/bt/common/ble_log/ble_log_spi_out.c

@@ -176,8 +176,10 @@ IRAM_ATTR static void esp_timer_cb_flushout(void)
         if (trans_head->trans.length) {
             spi_out_append_trans();
         }
-    } else {
+    }
-        // Restart flushout timer
+
+    // Restart flushout timer if not active
+    if (!esp_timer_is_active(flushout_timer_handle)) {
         esp_timer_start_once(flushout_timer_handle, SPI_OUT_FLUSHOUT_TIMEOUT);
     }
 
@@ -193,6 +195,9 @@ IRAM_ATTR static void esp_timer_cb_ts_sync(void)
     uint32_t lc_ts = 0;
     uint32_t esp_ts = 0;
 
+    // Toggle sync IO
+    sync_io_level = !sync_io_level;
+
     // Enter critical
     portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
     portENTER_CRITICAL_SAFE(&spinlock);
@@ -205,7 +210,7 @@ IRAM_ATTR static void esp_timer_cb_ts_sync(void)
     lc_ts = r_os_cputime_get32();
 #endif // CONFIG_IDF_TARGET_ESP32C2
 
-    // Toggle Sync IO
+    // Set sync IO level
     gpio_set_level(CONFIG_BT_BLE_LOG_SPI_OUT_SYNC_IO_NUM, (uint32_t)sync_io_level);
 
     // Get ESP timestamp
@@ -219,9 +224,6 @@ IRAM_ATTR static void esp_timer_cb_ts_sync(void)
     memcpy(sync_frame + 1, &lc_ts, sizeof(lc_ts));
     memcpy(sync_frame + 5, &esp_ts, sizeof(esp_ts));
     ble_log_spi_out_write(BLE_LOG_SPI_OUT_SOURCE_SYNC, sync_frame, 9);
-
-    // Update IO level
-    sync_io_level = !sync_io_level;
 }
 #endif // CONFIG_BT_BLE_LOG_SPI_OUT_TS_SYNC_ENABLED
 
@@ -351,6 +353,10 @@ void ble_log_spi_out_ts_sync_stop(void)
         if (esp_timer_is_active(ts_sync_timer_handle)) {
             esp_timer_stop(ts_sync_timer_handle);
         }
+
+        // Set sync IO to low level
+        sync_io_level = 0;
+        gpio_set_level(CONFIG_BT_BLE_LOG_SPI_OUT_SYNC_IO_NUM, (uint32_t)sync_io_level);
     }
 }
 #endif // CONFIG_BT_BLE_LOG_SPI_OUT_TS_SYNC_ENABLED

components/bt/common/ble_log/include/ble_log/ble_log_spi_out.h

@@ -6,6 +6,7 @@
 #ifndef __BT_SPI_OUT_H__
 #define __BT_SPI_OUT_H__
 
+#include <stdarg.h>
 #include <string.h>
 #include "driver/spi_master.h"
 #include "driver/gpio.h"
@@ -19,6 +20,7 @@
 #define BLE_LOG_SPI_OUT_SOURCE_NIMBLE 3
 #define BLE_LOG_SPI_OUT_SOURCE_HCI_UPSTREAM 4
 #define BLE_LOG_SPI_OUT_SOURCE_HCI_DOWNSTREAM 5
+#define BLE_LOG_SPI_OUT_SOURCE_USER 0x10
 #define BLE_LOG_SPI_OUT_SOURCE_SYNC 0xFE
 #define BLE_LOG_SPI_OUT_SOURCE_LOSS 0xFF
 

components/bt/controller/esp32c2/bt.c

@@ -393,11 +393,11 @@ void esp_bt_read_ctrl_log_from_flash(bool output)
     portENTER_CRITICAL_SAFE(&spinlock);
     esp_panic_handler_feed_wdts();
     ble_log_async_output_dump_all(true);
-    stop_write = true;
     esp_bt_ontroller_log_deinit();
-    portEXIT_CRITICAL_SAFE(&spinlock);
+    stop_write = true;
 
     buffer = (const uint8_t *)mapped_ptr;
+    esp_panic_handler_feed_wdts();
     if (is_filled) {
         read_index = next_erase_index;
     } else {
@@ -409,7 +409,7 @@ void esp_bt_read_ctrl_log_from_flash(bool output)
     while (read_index != write_index) {
         esp_rom_printf("%02x ", buffer[read_index]);
         if (print_len > max_print_len) {
-            vTaskDelay(2);
+            esp_panic_handler_feed_wdts();
             print_len = 0;
         }
 
@@ -417,6 +417,7 @@ void esp_bt_read_ctrl_log_from_flash(bool output)
         read_index = (read_index + 1) % MAX_STORAGE_SIZE;
     }
     esp_rom_printf(":DUMP_END]\r\n");
+    portEXIT_CRITICAL_SAFE(&spinlock);
     esp_partition_munmap(mmap_handle);
     err = esp_bt_controller_log_init(log_output_mode);
     assert(err == ESP_OK);
@@ -430,6 +431,9 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b
         esp_bt_controller_log_storage(len, addr, end);
 #endif //CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
     } else {
+        portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
+        portENTER_CRITICAL_SAFE(&spinlock);
+        esp_panic_handler_feed_wdts();
         for (int i = 0; i < len; i++) {
             esp_rom_printf("%02x ", addr[i]);
         }
@@ -437,6 +441,7 @@ static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, b
         if (end) {
             esp_rom_printf("\n");
         }
+        portEXIT_CRITICAL_SAFE(&spinlock);
     }
 }
 

components/bt/controller/esp32c5/Kconfig.in

@@ -396,6 +396,12 @@ menu "Controller debug features"
     config BT_LE_ASSERT_WHEN_ABNORMAL_DISCONN_ENABLED
         bool "When ACL disconnects abnormally, assertion processing is performed(Experimental)"
         default n
+
+    config BT_LE_DEBUG_REMAIN_SCENE_ENABLED
+        bool "Remain scene with GDB to capture relevant status info(Experimental)"
+        default n
+        help
+            Retain scene with GDB to capture info, requires disabling WDT (CONFIG_ESP_INT_WDT, CONFIG_ESP_TASK_WDT_EN).
 endmenu
 
 config BT_LE_LL_RESOLV_LIST_SIZE

components/bt/controller/esp32c5/bt.c

@@ -1640,6 +1640,10 @@ int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv)
 #endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
 #endif // (!CONFIG_BT_NIMBLE_ENABLED) && (CONFIG_BT_CONTROLLER_ENABLED)
 
+#if CONFIG_BT_LE_DEBUG_REMAIN_SCENE_ENABLED
+#include "esp_gdbstub.h"
+#endif // CONFIG_BT_LE_DEBUG_REMAIN_SCENE_ENABLED
+
 int IRAM_ATTR
 ble_capture_info_user_handler(uint8_t type, uint32_t reason)
 {
@@ -1650,12 +1654,16 @@ ble_capture_info_user_handler(uint8_t type, uint32_t reason)
             for (i = 0; i < 2; i++) {
                 esp_ble_controller_info_capture(0x010101);
             }
-
+#if CONFIG_BT_LE_DEBUG_REMAIN_SCENE_ENABLED
+            uintptr_t sp;
+            __asm__ volatile ("mv %0, sp" : "=r" (sp));
+            esp_gdbstub_panic_handler(&sp);
+#endif // CONFIG_BT_LE_DEBUG_REMAIN_SCENE_ENABLED
             break;
 #if CONFIG_BT_LE_ASSERT_WHEN_ABNORMAL_DISCONN_ENABLED
         case 1:
             if ((reason == 0x08) || (reason == 0x3d) || (reason == 0x28)) {
-                osi_assert_wrapper(__LINE__,__func__, type， reason);
+                osi_assert_wrapper(__LINE__,__func__, type, reason);
             }
             break;
 #endif // CONFIG_BT_LE_ASSERT_WHEN_ABNORMAL_DISCONN_ENABLED

components/bt/controller/esp32c6/Kconfig.in

@@ -428,6 +428,12 @@ menu "Controller debug features"
     config BT_LE_ASSERT_WHEN_ABNORMAL_DISCONN_ENABLED
         bool "When ACL disconnects abnormally, assertion processing is performed(Experimental)"
         default n
+
+    config BT_LE_DEBUG_REMAIN_SCENE_ENABLED
+        bool "Remain scene with GDB to capture relevant status info(Experimental)"
+        default n
+        help
+            Retain scene with GDB to capture info, requires disabling WDT (CONFIG_ESP_INT_WDT, CONFIG_ESP_TASK_WDT_EN).
 endmenu
 
 config BT_LE_LL_RESOLV_LIST_SIZE

components/bt/controller/esp32c6/bt.c

@@ -1661,6 +1661,10 @@ int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv)
 #endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
 #endif // (!CONFIG_BT_NIMBLE_ENABLED) && (CONFIG_BT_CONTROLLER_ENABLED)
 
+#if CONFIG_BT_LE_DEBUG_REMAIN_SCENE_ENABLED
+#include "esp_gdbstub.h"
+#endif // CONFIG_BT_LE_DEBUG_REMAIN_SCENE_ENABLED
+
 int IRAM_ATTR
 ble_capture_info_user_handler(uint8_t type, uint32_t reason)
 {
@@ -1671,12 +1675,16 @@ ble_capture_info_user_handler(uint8_t type, uint32_t reason)
             for (i = 0; i < 2; i++) {
                 esp_ble_controller_info_capture(0x010101);
             }
-
+#if CONFIG_BT_LE_DEBUG_REMAIN_SCENE_ENABLED
+            uintptr_t sp;
+            __asm__ volatile ("mv %0, sp" : "=r" (sp));
+            esp_gdbstub_panic_handler(&sp);
+#endif // CONFIG_BT_LE_DEBUG_REMAIN_SCENE_ENABLED
             break;
 #if CONFIG_BT_LE_ASSERT_WHEN_ABNORMAL_DISCONN_ENABLED
         case 1:
             if ((reason == 0x08) || (reason == 0x3d) || (reason == 0x28)) {
-                osi_assert_wrapper(__LINE__,__func__, type， reason);
+                osi_assert_wrapper(__LINE__,__func__, type, reason);
             }
             break;
 #endif // CONFIG_BT_LE_ASSERT_WHEN_ABNORMAL_DISCONN_ENABLED

components/bt/controller/esp32h2/Kconfig.in

@@ -419,6 +419,12 @@ menu "Controller debug features"
     config BT_LE_ASSERT_WHEN_ABNORMAL_DISCONN_ENABLED
         bool "When ACL disconnects abnormally, assertion processing is performed(Experimental)"
         default n
+
+    config BT_LE_DEBUG_REMAIN_SCENE_ENABLED
+        bool "Remain scene with GDB to capture relevant status info(Experimental)"
+        default n
+        help
+            Retain scene with GDB to capture info, requires disabling WDT (CONFIG_ESP_INT_WDT, CONFIG_ESP_TASK_WDT_EN).
 endmenu
 
 config BT_LE_LL_RESOLV_LIST_SIZE

components/bt/controller/esp32h2/bt.c

@@ -1633,6 +1633,9 @@ int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv)
 
 #endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
 #endif // (!CONFIG_BT_NIMBLE_ENABLED) && (CONFIG_BT_CONTROLLER_ENABLED)
+#if CONFIG_BT_LE_DEBUG_REMAIN_SCENE_ENABLED
+#include "esp_gdbstub.h"
+#endif // CONFIG_BT_LE_DEBUG_REMAIN_SCENE_ENABLED
 
 int IRAM_ATTR
 ble_capture_info_user_handler(uint8_t type, uint32_t reason)
@@ -1644,12 +1647,16 @@ ble_capture_info_user_handler(uint8_t type, uint32_t reason)
             for (i = 0; i < 2; i++) {
                 esp_ble_controller_info_capture(0x010101);
             }
-
+#if CONFIG_BT_LE_DEBUG_REMAIN_SCENE_ENABLED
+            uintptr_t sp;
+            __asm__ volatile ("mv %0, sp" : "=r" (sp));
+            esp_gdbstub_panic_handler(&sp);
+#endif // CONFIG_BT_LE_DEBUG_REMAIN_SCENE_ENABLED
             break;
 #if CONFIG_BT_LE_ASSERT_WHEN_ABNORMAL_DISCONN_ENABLED
         case 1:
             if ((reason == 0x08) || (reason == 0x3d) || (reason == 0x28)) {
-                osi_assert_wrapper(__LINE__,__func__, type， reason);
+                osi_assert_wrapper(__LINE__,__func__, type, reason);
             }
             break;
 #endif // CONFIG_BT_LE_ASSERT_WHEN_ABNORMAL_DISCONN_ENABLED

components/bt/controller/lib_esp32

@@ -1 +1 @@
-Subproject commit 6093909e01930f8cda6f60510f8a412c6d1814e8
+Subproject commit fbbb054cbc5c8b5aa466208dc8d12ccc10d7e08c

components/efuse/efuse_table_gen.py

@@ -495,8 +495,7 @@ def main():
     global idf_target
 
     parser = argparse.ArgumentParser(description='ESP32 eFuse Manager')
-    parser.add_argument('--idf_target', '-t', help='Target chip type', choices=['esp32', 'esp32s2', 'esp32s3', 'esp32c3',
+    parser.add_argument('--idf_target', '-t', help='Target chip type', default='esp32')
-                        'esp32c2', 'esp32c6', 'esp32h2', 'esp32p4', 'esp32c5', 'esp32c61'], default='esp32')
     parser.add_argument('--quiet', '-q', help="Don't print non-critical status messages to stderr", action='store_true')
     parser.add_argument('--debug', help='Create header file with debug info', default=False, action='store_false')
     parser.add_argument('--info', help='Print info about range of used bits', default=False, action='store_true')

components/efuse/esp32h4/esp_efuse_fields.c

@@ -0,0 +1,55 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "esp_efuse.h"
+#include "esp_efuse_utility.h"
+#include "esp_efuse_table.h"
+#include "stdlib.h"
+#include "esp_types.h"
+#include "assert.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "soc/efuse_periph.h"
+#include "sys/param.h"
+
+static __attribute__((unused)) const char *TAG = "efuse";
+
+// Contains functions that provide access to efuse fields which are often used in IDF.
+
+// Returns chip package from efuse
+uint32_t esp_efuse_get_pkg_ver(void)
+{
+    uint32_t pkg_ver = 0;
+#ifdef EFUSE_PKG_VERSION
+    esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count);
+#endif
+    return pkg_ver;
+}
+
+
+esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme)
+{
+    int cur_log_scheme = 0;
+    esp_efuse_read_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &cur_log_scheme, 2);
+    if (!cur_log_scheme) { // not burned yet
+        return esp_efuse_write_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &log_scheme, 2);
+    } else {
+        return ESP_ERR_INVALID_STATE;
+    }
+}
+
+esp_err_t esp_efuse_disable_rom_download_mode(void)
+{
+    return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE);
+}
+
+esp_err_t esp_efuse_enable_rom_secure_download_mode(void)
+{
+    if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) {
+        return ESP_ERR_INVALID_STATE;
+    }
+    return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD);
+}

components/efuse/esp32h4/esp_efuse_table.csv

@@ -0,0 +1,162 @@
+
+# field_name,       |    efuse_block, | bit_start, | bit_count, |comment #
+#                   |    (EFUSE_BLK0  | (0..255)   | (1-256)    |        #
+#                   |     EFUSE_BLK1  |            |            |        #
+#                   |        ...)     |            |            |        #
+##########################################################################
+# !!!!!!!!!!! #
+# After editing this file, run the command manually "idf.py efuse-common-table"
+# this will generate new source files, next rebuild all the sources.
+# !!!!!!!!!!! #
+
+# This file was generated by regtools.py based on the efuses.yaml file with the version: 7bc342bad0952907e1db21112d258c6b
+
+WR_DIS,                                          EFUSE_BLK0,   0,  32, [] Disable programming of individual eFuses
+WR_DIS.RD_DIS,                                   EFUSE_BLK0,   0,   1, [] wr_dis of RD_DIS
+WR_DIS.KM_DISABLE_DEPLOY_MODE,                   EFUSE_BLK0,   1,   1, [] wr_dis of KM_DISABLE_DEPLOY_MODE
+WR_DIS.KM_RND_SWITCH_CYCLE,                      EFUSE_BLK0,   1,   1, [] wr_dis of KM_RND_SWITCH_CYCLE
+WR_DIS.KM_DEPLOY_ONLY_ONCE,                      EFUSE_BLK0,   1,   1, [] wr_dis of KM_DEPLOY_ONLY_ONCE
+WR_DIS.FORCE_USE_KEY_MANAGER_KEY,                EFUSE_BLK0,   1,   1, [] wr_dis of FORCE_USE_KEY_MANAGER_KEY
+WR_DIS.FORCE_DISABLE_SW_INIT_KEY,                EFUSE_BLK0,   1,   1, [] wr_dis of FORCE_DISABLE_SW_INIT_KEY
+WR_DIS.KM_XTS_KEY_LENGTH_256,                    EFUSE_BLK0,   1,   1, [] wr_dis of KM_XTS_KEY_LENGTH_256
+WR_DIS.LOCK_KM_KEY,                              EFUSE_BLK0,   1,   1, [] wr_dis of LOCK_KM_KEY
+WR_DIS.DIS_USB_JTAG,                             EFUSE_BLK0,   2,   1, [] wr_dis of DIS_USB_JTAG
+WR_DIS.DIS_FORCE_DOWNLOAD,                       EFUSE_BLK0,   2,   1, [] wr_dis of DIS_FORCE_DOWNLOAD
+WR_DIS.SPI_DOWNLOAD_MSPI_DIS,                    EFUSE_BLK0,   2,   1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
+WR_DIS.DIS_TWAI,                                 EFUSE_BLK0,   2,   1, [] wr_dis of DIS_TWAI
+WR_DIS.JTAG_SEL_ENABLE,                          EFUSE_BLK0,   2,   1, [] wr_dis of JTAG_SEL_ENABLE
+WR_DIS.DIS_PAD_JTAG,                             EFUSE_BLK0,   2,   1, [] wr_dis of DIS_PAD_JTAG
+WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT,              EFUSE_BLK0,   2,   1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
+WR_DIS.SPI_BOOT_CRYPT_CNT,                       EFUSE_BLK0,   4,   1, [] wr_dis of SPI_BOOT_CRYPT_CNT
+WR_DIS.SECURE_BOOT_KEY_REVOKE0,                  EFUSE_BLK0,   5,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
+WR_DIS.SECURE_BOOT_KEY_REVOKE1,                  EFUSE_BLK0,   6,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
+WR_DIS.SECURE_BOOT_KEY_REVOKE2,                  EFUSE_BLK0,   7,   1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
+WR_DIS.KEY_PURPOSE_0,                            EFUSE_BLK0,   8,   1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
+WR_DIS.KEY_PURPOSE_1,                            EFUSE_BLK0,   9,   1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
+WR_DIS.KEY_PURPOSE_2,                            EFUSE_BLK0,  10,   1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
+WR_DIS.KEY_PURPOSE_3,                            EFUSE_BLK0,  11,   1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
+WR_DIS.KEY_PURPOSE_4,                            EFUSE_BLK0,  12,   1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
+WR_DIS.KEY_PURPOSE_5,                            EFUSE_BLK0,  13,   1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
+WR_DIS.SEC_DPA_LEVEL,                            EFUSE_BLK0,  14,   1, [] wr_dis of SEC_DPA_LEVEL
+WR_DIS.XTS_DPA_PSEUDO_LEVEL,                     EFUSE_BLK0,  14,   1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL
+WR_DIS.XTS_DPA_CLK_ENABLE,                       EFUSE_BLK0,  14,   1, [] wr_dis of XTS_DPA_CLK_ENABLE
+WR_DIS.ECC_FORCE_CONST_TIME,                     EFUSE_BLK0,  14,   1, [] wr_dis of ECC_FORCE_CONST_TIME
+WR_DIS.SECURE_BOOT_EN,                           EFUSE_BLK0,  15,   1, [] wr_dis of SECURE_BOOT_EN
+WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,            EFUSE_BLK0,  16,   1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
+WR_DIS.FLASH_TPUW,                               EFUSE_BLK0,  18,   1, [] wr_dis of FLASH_TPUW
+WR_DIS.DIS_DOWNLOAD_MODE,                        EFUSE_BLK0,  18,   1, [] wr_dis of DIS_DOWNLOAD_MODE
+WR_DIS.DIS_DIRECT_BOOT,                          EFUSE_BLK0,  18,   1, [] wr_dis of DIS_DIRECT_BOOT
+WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT,            EFUSE_BLK0,  18,   1, [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
+WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,        EFUSE_BLK0,  18,   1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
+WR_DIS.ENABLE_SECURITY_DOWNLOAD,                 EFUSE_BLK0,  18,   1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
+WR_DIS.UART_PRINT_CONTROL,                       EFUSE_BLK0,  18,   1, [] wr_dis of UART_PRINT_CONTROL
+WR_DIS.FORCE_SEND_RESUME,                        EFUSE_BLK0,  18,   1, [] wr_dis of FORCE_SEND_RESUME
+WR_DIS.SECURE_VERSION,                           EFUSE_BLK0,  18,   1, [] wr_dis of SECURE_VERSION
+WR_DIS.HUK_GEN_STATE,                            EFUSE_BLK0,  19,   1, [] wr_dis of HUK_GEN_STATE
+WR_DIS.MAC,                                      EFUSE_BLK0,  20,   1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
+WR_DIS.MAC_EXT,                                  EFUSE_BLK0,  20,   1, [] wr_dis of MAC_EXT
+WR_DIS.PVT_LIMIT,                                EFUSE_BLK0,  20,   1, [] wr_dis of PVT_LIMIT
+WR_DIS.PVT_CELL_SELECT,                          EFUSE_BLK0,  20,   1, [] wr_dis of PVT_CELL_SELECT
+WR_DIS.PVT_PUMP_LIMIT,                           EFUSE_BLK0,  20,   1, [] wr_dis of PVT_PUMP_LIMIT
+WR_DIS.PUMP_DRV,                                 EFUSE_BLK0,  20,   1, [] wr_dis of PUMP_DRV
+WR_DIS.WDT_DELAY_SEL,                            EFUSE_BLK0,  20,   1, [] wr_dis of WDT_DELAY_SEL
+WR_DIS.HYS_EN_PAD,                               EFUSE_BLK0,  20,   1, [] wr_dis of HYS_EN_PAD
+WR_DIS.PVT_GLITCH_CHARGE_RESET,                  EFUSE_BLK0,  20,   1, [] wr_dis of PVT_GLITCH_CHARGE_RESET
+WR_DIS.VDD_SPI_LDO_ADJUST,                       EFUSE_BLK0,  20,   1, [] wr_dis of VDD_SPI_LDO_ADJUST
+WR_DIS.FLASH_LDO_POWER_SEL,                      EFUSE_BLK0,  20,   1, [] wr_dis of FLASH_LDO_POWER_SEL
+WR_DIS.BLOCK_USR_DATA,                           EFUSE_BLK0,  22,   1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
+WR_DIS.CUSTOM_MAC,                               EFUSE_BLK0,  22,   1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
+WR_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  23,   1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
+WR_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  24,   1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
+WR_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  25,   1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
+WR_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  26,   1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
+WR_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  27,   1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
+WR_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  28,   1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
+WR_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  29,   1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
+WR_DIS.USB_EXCHG_PINS,                           EFUSE_BLK0,  30,   1, [] wr_dis of USB_EXCHG_PINS
+WR_DIS.SOFT_DIS_JTAG,                            EFUSE_BLK0,  31,   1, [] wr_dis of SOFT_DIS_JTAG
+RD_DIS,                                          EFUSE_BLK0,  32,   7, [] Disable reading from BlOCK4-10
+RD_DIS.BLOCK_KEY0,                               EFUSE_BLK0,  32,   1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
+RD_DIS.BLOCK_KEY1,                               EFUSE_BLK0,  33,   1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
+RD_DIS.BLOCK_KEY2,                               EFUSE_BLK0,  34,   1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
+RD_DIS.BLOCK_KEY3,                               EFUSE_BLK0,  35,   1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
+RD_DIS.BLOCK_KEY4,                               EFUSE_BLK0,  36,   1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
+RD_DIS.BLOCK_KEY5,                               EFUSE_BLK0,  37,   1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
+RD_DIS.BLOCK_SYS_DATA2,                          EFUSE_BLK0,  38,   1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
+DIS_USB_JTAG,                                    EFUSE_BLK0,  39,   1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled
+DIS_FORCE_DOWNLOAD,                              EFUSE_BLK0,  41,   1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled
+SPI_DOWNLOAD_MSPI_DIS,                           EFUSE_BLK0,  42,   1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled
+DIS_TWAI,                                        EFUSE_BLK0,  43,   1, [] Represents whether TWAI function is disabled or enabled. 1: disabled 0: enabled
+JTAG_SEL_ENABLE,                                 EFUSE_BLK0,  44,   1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled
+DIS_PAD_JTAG,                                    EFUSE_BLK0,  45,   1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled
+DIS_DOWNLOAD_MANUAL_ENCRYPT,                     EFUSE_BLK0,  46,   1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled
+PVT_GLITCH_EN,                                   EFUSE_BLK0,  50,   1, [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable
+PVT_GLITCH_MODE,                                 EFUSE_BLK0,  52,   2, [] Use to configure glitch mode
+DIS_CORE1,                                       EFUSE_BLK0,  54,   1, [] Represents whether the CPU-Core1 is disabled.  1: Disabled.  0: Not disable
+SPI_BOOT_CRYPT_CNT,                              EFUSE_BLK0,  55,   3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
+SECURE_BOOT_KEY_REVOKE0,                         EFUSE_BLK0,  58,   1, [] Revoke 1st secure boot key
+SECURE_BOOT_KEY_REVOKE1,                         EFUSE_BLK0,  59,   1, [] Revoke 2nd secure boot key
+SECURE_BOOT_KEY_REVOKE2,                         EFUSE_BLK0,  60,   1, [] Revoke 3rd secure boot key
+KEY_PURPOSE_0,                                   EFUSE_BLK0,  64,   5, [KEY0_PURPOSE] Represents the purpose of Key0
+KEY_PURPOSE_1,                                   EFUSE_BLK0,  69,   5, [KEY1_PURPOSE] Represents the purpose of Key1
+KEY_PURPOSE_2,                                   EFUSE_BLK0,  74,   5, [KEY2_PURPOSE] Represents the purpose of Key2
+KEY_PURPOSE_3,                                   EFUSE_BLK0,  79,   5, [KEY3_PURPOSE] Represents the purpose of Key3
+KEY_PURPOSE_4,                                   EFUSE_BLK0,  84,   5, [KEY4_PURPOSE] Represents the purpose of Key4
+KEY_PURPOSE_5,                                   EFUSE_BLK0,  89,   5, [KEY5_PURPOSE] Represents the purpose of Key5
+SEC_DPA_LEVEL,                                   EFUSE_BLK0,  94,   2, [] Represents the spa secure level by configuring the clock random divide mode
+XTS_DPA_PSEUDO_LEVEL,                            EFUSE_BLK0,  96,   2, [] Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled
+XTS_DPA_CLK_ENABLE,                              EFUSE_BLK0,  98,   1, [] Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: Disable.
+ECC_FORCE_CONST_TIME,                            EFUSE_BLK0,  99,   1, [] Represents whether to force ecc to use const-time calculation mode.  1: Enable.  0: Disable
+ECDSA_P384_ENABLE,                               EFUSE_BLK0, 100,   1, [] Represents if the chip supports ECDSA P384
+SECURE_BOOT_EN,                                  EFUSE_BLK0, 101,   1, [] Represents whether secure boot is enabled or disabled. 1: enabled 0: disabled
+SECURE_BOOT_AGGRESSIVE_REVOKE,                   EFUSE_BLK0, 102,   1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
+KM_DISABLE_DEPLOY_MODE,                          EFUSE_BLK0, 103,   5, [] Represents whether the new key deployment of key manager is disabled. Bit0: Represents whether the new ECDSA key deployment is disabled0: Enabled1: DisabledBit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is disabled0: Enabled1: DisabledBit2: Represents whether the new HMAC key deployment is disabled0: Enabled1: DisabledBit3: Represents whether the new DS key deployment is disabled0: Enabled1: Disabled
+KM_RND_SWITCH_CYCLE,                             EFUSE_BLK0, 108,   2, [] Represents the cycle at which the Key Manager switches random numbers.0: Controlled by the \hyperref[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWITCH\_CYCLE} register. For more information; please refer to Chapter \ref{mod:keymng} \textit{\nameref{mod:keymng}}1: 8 Key Manager clock cycles2: 16 Key Manager clock cycles3: 32 Key Manager clock cycles
+KM_DEPLOY_ONLY_ONCE,                             EFUSE_BLK0, 110,   5, [] Represents whether the corresponding key can be deployed only once.Bit0: Represents whether the ECDSA key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit1: Represents whether the XTS-AES (flash and PSRAM) key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit2: Represents whether the HMAC key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit3: Represents whether the DS key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only once
+FORCE_USE_KEY_MANAGER_KEY,                       EFUSE_BLK0, 115,   5, [] Represents whether the corresponding key must come from Key Manager. Bit0: Represents whether the ECDSA key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit1: Represents whether the XTS-AES (flash and PSRAM) key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit2: Represents whether the HMAC key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit3: Represents whether the DS key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key Manager
+FORCE_DISABLE_SW_INIT_KEY,                       EFUSE_BLK0, 120,   1, [] Represents whether to disable the use of the initialization key written by software and instead force use efuse\_init\_key.0: Enable1: Disable
+KM_XTS_KEY_LENGTH_256,                           EFUSE_BLK0, 121,   1, [] Represents which key flash encryption uses.0: XTS-AES-256 key1: XTS-AES-128 key
+LOCK_KM_KEY,                                     EFUSE_BLK0, 122,   1, [] Represents whether the keys in the Key Manager are locked after deployment.0: Not locked1: Locked
+FLASH_TPUW,                                      EFUSE_BLK0, 123,   3, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
+DIS_DOWNLOAD_MODE,                               EFUSE_BLK0, 127,   1, [] Represents whether Download mode is disabled or enabled. 1: disabled 0: enabled
+DIS_DIRECT_BOOT,                                 EFUSE_BLK0, 128,   1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled 0: enabled
+DIS_USB_SERIAL_JTAG_ROM_PRINT,                   EFUSE_BLK0, 129,   1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled 0: enabled
+DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE,               EFUSE_BLK0, 130,   1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable
+ENABLE_SECURITY_DOWNLOAD,                        EFUSE_BLK0, 131,   1, [] Represents whether security download is enabled or disabled. 1: enabled 0: disabled
+UART_PRINT_CONTROL,                              EFUSE_BLK0, 132,   2, [] Represents the type of UART printing. 00: force enable printing 01: enable printing when GPIO8 is reset at low level 10: enable printing when GPIO8 is reset at high level 11: force disable printing
+FORCE_SEND_RESUME,                               EFUSE_BLK0, 134,   1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced 0:not forced
+SECURE_VERSION,                                  EFUSE_BLK0, 135,  16, [] Represents the version used by ESP-IDF anti-rollback feature
+HUK_GEN_STATE,                                   EFUSE_BLK0, 151,   5, [] Represents whether the HUK generate mode is valid.Odd count of bits with a value of 1: InvalidEven count of bits with a value of 1: Valid
+FLASH_LDO_EFUSE_SEL,                             EFUSE_BLK0, 156,   1, [] Represents whether to select efuse control flash ldo default voltage.  1 : efuse 0 : strapping
+USB_EXCHG_PINS,                                  EFUSE_BLK0, 168,   1, [] Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged. 1: exchanged 0: not exchanged
+USB_OTG_FS_EXCHG_PINS,                           EFUSE_BLK0, 169,   1, [] Represents whether the D+ and D- pins of USB_OTG_FS PHY is exchanged. 1: exchanged 0: not exchanged
+USB_PHY_SEL,                                     EFUSE_BLK0, 170,   1, [] Represents whether to exchange the USB_SERIAL_JTAG PHY with USB_OTG_FS PHY.  1: exchanged.  0: not exchanged
+SOFT_DIS_JTAG,                                   EFUSE_BLK0, 171,   3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled Even number: enabled
+IO_LDO_ADJUST,                                   EFUSE_BLK0, 174,   8, [] Represents configuration of IO LDO mode and voltage.
+IO_LDO_1P8,                                      EFUSE_BLK0, 182,   1, [] Represents select IO LDO voltage to 1.8V or 3.3V. 1: 1.8V 0: 3.3V
+DCDC_CCM_EN,                                     EFUSE_BLK0, 183,   1, [] Represents whether change DCDC to CCM mode
+MAC,                                             EFUSE_BLK1,  40,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,  32,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,  24,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,  16,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,   8,   8, [MAC_FACTORY] MAC address
+,                                                EFUSE_BLK1,   0,   8, [MAC_FACTORY] MAC address
+MAC_EXT,                                         EFUSE_BLK1,  48,  16, [] Represents the extended bits of MAC address
+PVT_LIMIT,                                       EFUSE_BLK1,  64,  16, [] Power glitch monitor threthold
+PVT_CELL_SELECT,                                 EFUSE_BLK1,  80,   7, [] Power glitch monitor PVT cell select
+PVT_PUMP_LIMIT,                                  EFUSE_BLK1,  87,   8, [] Use to configure voltage monitor limit for charge pump
+PUMP_DRV,                                        EFUSE_BLK1,  96,   4, [] Use to configure charge pump voltage gain
+WDT_DELAY_SEL,                                   EFUSE_BLK1, 100,   2, [] Represents the threshold level of the RTC watchdog STG0 timeout. 0: Original threshold configuration value of STG0 *2 1: Original threshold configuration value of STG0 *4 2: Original threshold configuration value of STG0 *8 3: Original threshold configuration value of STG0 *16
+HYS_EN_PAD,                                      EFUSE_BLK1, 102,   1, [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled 0:disabled
+PVT_GLITCH_CHARGE_RESET,                         EFUSE_BLK1, 103,   1, [] Represents whether to trigger reset or charge pump when PVT power glitch happened.1:Trigger charge pump. 0:Trigger reset
+VDD_SPI_LDO_ADJUST,                              EFUSE_BLK1, 105,   8, [] Represents configuration of FLASH LDO mode and voltage.
+FLASH_LDO_POWER_SEL,                             EFUSE_BLK1, 113,   1, [] Represents which flash ldo be select: 1: FLASH LDO 1P2 0 : FLASH LDO 1P8
+USER_DATA,                                       EFUSE_BLK3,   0, 256, [BLOCK_USR_DATA] User data
+USER_DATA.MAC_CUSTOM,                            EFUSE_BLK3, 200,  48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
+KEY0,                                            EFUSE_BLK4,   0, 256, [BLOCK_KEY0] Key0 or user data
+KEY1,                                            EFUSE_BLK5,   0, 256, [BLOCK_KEY1] Key1 or user data
+KEY2,                                            EFUSE_BLK6,   0, 256, [BLOCK_KEY2] Key2 or user data
+KEY3,                                            EFUSE_BLK7,   0, 256, [BLOCK_KEY3] Key3 or user data
+KEY4,                                            EFUSE_BLK8,   0, 256, [BLOCK_KEY4] Key4 or user data
+KEY5,                                            EFUSE_BLK9,   0, 256, [BLOCK_KEY5] Key5 or user data
+SYS_DATA_PART2,                                  EFUSE_BLK10,   0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)

components/efuse/esp32h4/esp_efuse_utility.c

@@ -0,0 +1,208 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <sys/param.h>
+#include "sdkconfig.h"
+#include "esp_log.h"
+#include "assert.h"
+#include "esp_efuse_utility.h"
+#include "soc/efuse_periph.h"
+#include "hal/efuse_hal.h"
+
+static const char *TAG = "efuse";
+
+#ifdef CONFIG_EFUSE_VIRTUAL
+extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK];
+#endif // CONFIG_EFUSE_VIRTUAL
+
+/*Range addresses to read blocks*/
+const esp_efuse_range_addr_t range_read_addr_blocks[] = {
+    {EFUSE_RD_WR_DIS0_REG,       EFUSE_RD_REPEAT_DATA4_REG},      // range address of EFUSE_BLK0  REPEAT
+    {EFUSE_RD_MAC_SYS0_REG,     EFUSE_RD_MAC_SYS5_REG},      // range address of EFUSE_BLK1  MAC_SPI_8M
+    {EFUSE_RD_SYS_PART1_DATA0_REG,    EFUSE_RD_SYS_PART1_DATA7_REG},         // range address of EFUSE_BLK2  SYS_DATA
+    {EFUSE_RD_USR_DATA0_REG,    EFUSE_RD_USR_DATA7_REG},         // range address of EFUSE_BLK3  USR_DATA
+    {EFUSE_RD_KEY0_DATA0_REG,   EFUSE_RD_KEY0_DATA7_REG},        // range address of EFUSE_BLK4  KEY0
+    {EFUSE_RD_KEY1_DATA0_REG,   EFUSE_RD_KEY1_DATA7_REG},        // range address of EFUSE_BLK5  KEY1
+    {EFUSE_RD_KEY2_DATA0_REG,   EFUSE_RD_KEY2_DATA7_REG},        // range address of EFUSE_BLK6  KEY2
+    {EFUSE_RD_KEY3_DATA0_REG,   EFUSE_RD_KEY3_DATA7_REG},        // range address of EFUSE_BLK7  KEY3
+    {EFUSE_RD_KEY4_DATA0_REG,   EFUSE_RD_KEY4_DATA7_REG},        // range address of EFUSE_BLK8  KEY4
+    {EFUSE_RD_KEY5_DATA0_REG,   EFUSE_RD_KEY5_DATA7_REG},        // range address of EFUSE_BLK9  KEY5
+    {EFUSE_RD_SYS_PART2_DATA0_REG,   EFUSE_RD_SYS_PART2_DATA7_REG}         // range address of EFUSE_BLK10 KEY6
+};
+
+static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 };
+
+/*Range addresses to write blocks (it is not real regs, it is buffer) */
+const esp_efuse_range_addr_t range_write_addr_blocks[] = {
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK0][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK1][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK2][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK3][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK4][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK5][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK6][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK7][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK8][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK9][0],  (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]},
+    {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]},
+};
+
+#ifndef CONFIG_EFUSE_VIRTUAL
+// Update Efuse timing configuration
+static esp_err_t esp_efuse_set_timing(void)
+{
+    // efuse clock is fixed.
+    // An argument (0) is for compatibility and will be ignored.
+    efuse_hal_set_timing(0);
+    return ESP_OK;
+}
+#endif // ifndef CONFIG_EFUSE_VIRTUAL
+
+// Efuse read operation: copies data from physical efuses to efuse read registers.
+void esp_efuse_utility_clear_program_registers(void)
+{
+    efuse_hal_read();
+    efuse_hal_clear_program_registers();
+}
+
+esp_err_t esp_efuse_utility_check_errors(void)
+{
+    return ESP_OK;
+}
+
+// Burn values written to the efuse write registers
+esp_err_t esp_efuse_utility_burn_chip(void)
+{
+    return esp_efuse_utility_burn_chip_opt(false, true);
+}
+
+esp_err_t esp_efuse_utility_burn_chip_opt(bool ignore_coding_errors, bool verify_written_data)
+{
+    esp_err_t error = ESP_OK;
+#ifdef CONFIG_EFUSE_VIRTUAL
+    (void) ignore_coding_errors;
+    (void) verify_written_data;
+    ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses");
+    for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
+        int subblock = 0;
+        for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
+            virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block);
+        }
+    }
+#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
+    esp_efuse_utility_write_efuses_to_flash();
+#endif
+#else // CONFIG_EFUSE_VIRTUAL
+    if (esp_efuse_set_timing() != ESP_OK) {
+        ESP_LOGE(TAG, "Efuse fields are not burnt");
+    } else {
+        // Permanently update values written to the efuse write registers
+        // It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks.
+        for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) {
+            bool need_burn_block = false;
+            for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
+                if (REG_READ(addr_wr_block) != 0) {
+                    need_burn_block = true;
+                    break;
+                }
+            }
+            if (!need_burn_block) {
+                continue;
+            }
+            if (error) {
+                // It is done for a use case: BLOCK2 (Flash encryption key) could have an error (incorrect written data)
+                // in this case we can not burn any data into BLOCK0 because it might set read/write protections of BLOCK2.
+                ESP_LOGE(TAG, "BLOCK%d can not be burned because a previous block got an error, skipped.", num_block);
+                continue;
+            }
+            efuse_hal_clear_program_registers();
+            if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
+                uint8_t block_rs[12];
+                efuse_hal_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs);
+                hal_memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs));
+            }
+            unsigned r_data_len = (range_read_addr_blocks[num_block].end - range_read_addr_blocks[num_block].start) + sizeof(uint32_t);
+            unsigned data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t);
+            memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len);
+
+            uint32_t backup_write_data[8 + 3]; // 8 words are data and 3 words are RS coding data
+            hal_memcpy(backup_write_data, (void *)EFUSE_PGM_DATA0_REG, sizeof(backup_write_data));
+            int repeat_burn_op = 1;
+            bool correct_written_data;
+            bool coding_error_before = !ignore_coding_errors && efuse_hal_is_coding_error_in_block(num_block);
+            if (coding_error_before) {
+                ESP_LOGW(TAG, "BLOCK%d already has a coding error", num_block);
+            }
+            bool coding_error_occurred;
+
+            do {
+                ESP_LOGI(TAG, "BURN BLOCK%d", num_block);
+                efuse_hal_program(num_block); // BURN a block
+
+                bool coding_error_after;
+                for (unsigned i = 0; i < 5; i++) {
+                    efuse_hal_read();
+                    coding_error_after = efuse_hal_is_coding_error_in_block(num_block);
+                    if (coding_error_after == true) {
+                        break;
+                    }
+                }
+                coding_error_occurred = !ignore_coding_errors && (coding_error_before != coding_error_after) && !coding_error_before;
+                if (coding_error_occurred) {
+                    ESP_LOGW(TAG, "BLOCK%d got a coding error", num_block);
+                }
+
+                correct_written_data = (verify_written_data) ? esp_efuse_utility_is_correct_written_data(num_block, r_data_len) : true;
+                if (!correct_written_data || coding_error_occurred) {
+                    ESP_LOGW(TAG, "BLOCK%d: next retry to fix an error [%d/3]...", num_block, repeat_burn_op);
+                    hal_memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)backup_write_data, sizeof(backup_write_data));
+                }
+
+            } while ((!correct_written_data || coding_error_occurred) && repeat_burn_op++ < 3);
+
+            if (coding_error_occurred) {
+                ESP_LOGW(TAG, "Coding error was not fixed");
+                if (num_block == 0) {
+                    ESP_LOGE(TAG, "BLOCK0 got a coding error, which might be critical for security");
+                    error = ESP_FAIL;
+                }
+            }
+            if (!correct_written_data) {
+                ESP_LOGE(TAG, "Written data are incorrect");
+                error = ESP_FAIL;
+            }
+        }
+    }
+#endif // CONFIG_EFUSE_VIRTUAL
+    esp_efuse_utility_reset();
+    return error;
+}
+
+// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values.
+// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme.
+// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this.
+// They will be filled during the burn operation.
+esp_err_t esp_efuse_utility_apply_new_coding_scheme()
+{
+    // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE.
+    for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) {
+        if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) {
+            for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) {
+                if (REG_READ(addr_wr_block)) {
+                    int num_reg = 0;
+                    for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) {
+                        if (esp_efuse_utility_read_reg(num_block, num_reg)) {
+                            ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden.");
+                            return ESP_ERR_CODING;
+                        }
+                    }
+                    break;
+                }
+            }
+        }
+    }
+    return ESP_OK;
+}

components/efuse/esp32h4/include/esp_efuse_chip.h

@@ -0,0 +1,79 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Type of eFuse blocks ESP32H4
+ */
+typedef enum {
+    EFUSE_BLK0                 = 0,   /**< Number of eFuse BLOCK0. REPEAT_DATA */
+
+    EFUSE_BLK1                 = 1,   /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */
+
+    EFUSE_BLK2                 = 2,   /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
+    EFUSE_BLK_SYS_DATA_PART1   = 2,   /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */
+
+    EFUSE_BLK3                 = 3,   /**< Number of eFuse BLOCK3. USER_DATA*/
+    EFUSE_BLK_USER_DATA        = 3,   /**< Number of eFuse BLOCK3. USER_DATA*/
+
+    EFUSE_BLK4                 = 4,   /**< Number of eFuse BLOCK4. KEY0 */
+    EFUSE_BLK_KEY0             = 4,   /**< Number of eFuse BLOCK4. KEY0 */
+
+    EFUSE_BLK5                 = 5,   /**< Number of eFuse BLOCK5. KEY1 */
+    EFUSE_BLK_KEY1             = 5,   /**< Number of eFuse BLOCK5. KEY1 */
+
+    EFUSE_BLK6                 = 6,   /**< Number of eFuse BLOCK6. KEY2 */
+    EFUSE_BLK_KEY2             = 6,   /**< Number of eFuse BLOCK6. KEY2 */
+
+    EFUSE_BLK7                 = 7,   /**< Number of eFuse BLOCK7. KEY3 */
+    EFUSE_BLK_KEY3             = 7,   /**< Number of eFuse BLOCK7. KEY3 */
+
+    EFUSE_BLK8                 = 8,   /**< Number of eFuse BLOCK8. KEY4 */
+    EFUSE_BLK_KEY4             = 8,   /**< Number of eFuse BLOCK8. KEY4 */
+
+    EFUSE_BLK9                 = 9,   /**< Number of eFuse BLOCK9. KEY5 */
+    EFUSE_BLK_KEY5             = 9,   /**< Number of eFuse BLOCK9. KEY5 */
+    EFUSE_BLK_KEY_MAX          = 10,
+
+    EFUSE_BLK10                = 10,  /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
+    EFUSE_BLK_SYS_DATA_PART2   = 10,  /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */
+
+    EFUSE_BLK_MAX
+} esp_efuse_block_t;
+
+/**
+ * @brief Type of coding scheme
+ */
+typedef enum {
+    EFUSE_CODING_SCHEME_NONE    = 0,    /**< None */
+    EFUSE_CODING_SCHEME_RS      = 3,    /**< Reed-Solomon coding */
+} esp_efuse_coding_scheme_t;
+
+/**
+ * @brief Type of key purpose
+ */
+typedef enum {
+    ESP_EFUSE_KEY_PURPOSE_USER = 0,                         /**< User purposes (software-only use) */
+    ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1,                    /**< ECDSA private key (Expected in little endian order)*/
+    ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4,              /**< XTS_AES_128_KEY (flash/PSRAM encryption) */
+    ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5,                /**< HMAC Downstream mode */
+    ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6,               /**< JTAG soft enable key (uses HMAC Downstream mode) */
+    ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7,  /**< Digital Signature peripheral key (uses HMAC Downstream mode) */
+    ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8,                      /**< HMAC Upstream mode */
+    ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9,          /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */
+    ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10,         /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */
+    ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11,         /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */
+    ESP_EFUSE_KEY_PURPOSE_MAX,                              /**< MAX PURPOSE */
+} esp_efuse_purpose_t;
+
+#ifdef __cplusplus
+}
+#endif

components/efuse/esp32h4/include/esp_efuse_table.h

@@ -0,0 +1,208 @@
+/*
+ * SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "esp_efuse.h"
+
+// md5_digest_table 6bfa2ae917ac6cbce5b70a55ea6a78bd
+// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
+// If you want to change some fields, you need to change esp_efuse_table.csv file
+// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
+// To show efuse_table run the command 'show_efuse_table'.
+
+
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_XTS_KEY_LENGTH_256[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
+#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
+#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
+#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
+#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
+#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
+#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HUK_GEN_STATE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
+#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC_EXT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_LIMIT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_CELL_SELECT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_PUMP_LIMIT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PUMP_DRV[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_CHARGE_RESET[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_LDO_ADJUST[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_LDO_POWER_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
+#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
+#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
+#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
+#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
+#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
+#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
+#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
+#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
+#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
+#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
+#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
+#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
+#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
+#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
+#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
+#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
+#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
+extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CORE1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
+#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
+#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
+#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
+#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
+#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
+#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
+extern const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ECDSA_P384_ENABLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_USE_KEY_MANAGER_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[];
+extern const esp_efuse_desc_t* ESP_EFUSE_LOCK_KM_KEY[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DIRECT_BOOT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
+extern const esp_efuse_desc_t* ESP_EFUSE_HUK_GEN_STATE[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_LDO_EFUSE_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG_FS_EXCHG_PINS[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USB_PHY_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
+extern const esp_efuse_desc_t* ESP_EFUSE_IO_LDO_ADJUST[];
+extern const esp_efuse_desc_t* ESP_EFUSE_IO_LDO_1P8[];
+extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_CCM_EN[];
+extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
+#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
+extern const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PVT_LIMIT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PVT_CELL_SELECT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PVT_PUMP_LIMIT[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PUMP_DRV[];
+extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[];
+extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_CHARGE_RESET[];
+extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_LDO_ADJUST[];
+extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_LDO_POWER_SEL[];
+extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
+#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
+extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
+#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
+#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
+#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
+#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
+#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
+#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
+#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
+extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
+#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
+extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
+#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
+
+#ifdef __cplusplus
+}
+#endif

components/efuse/esp32h4/private_include/esp_efuse_utility.h

@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define COUNT_EFUSE_REG_PER_BLOCK 8      /* The number of registers per block. */
+
+#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0
+
+#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit)
+
+#ifdef __cplusplus
+}
+#endif

components/efuse/esp32h4/sources.cmake

@@ -0,0 +1,3 @@
+set(EFUSE_SOC_SRCS  "esp_efuse_table.c"
+                    "esp_efuse_fields.c"
+                    "esp_efuse_utility.c")

components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c

@@ -366,7 +366,7 @@ static void test_use_external_non_free_running_clock(parlio_tx_unit_handle_t tx_
     TEST_ESP_OK(parlio_new_tx_unit(&config, &tx_unit));
     TEST_ESP_OK(parlio_tx_unit_enable(tx_unit));
     // let core clock running for a while to update the clock divider threshold
-    esp_rom_delay_us(100);
+    esp_rom_delay_us(100 * 1000);
     parlio_transmit_config_t transmit_config = {
         .idle_value = 0xAA,
     };

components/esp_hw_support/port/esp32/include/soc/rtc.h

@@ -564,8 +564,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg);
  * used in lightsleep mode.
  *
  * @param slowclk_period re-calibrated slow clock period
+ * @param dslp true if initialize for deepsleep request
  */
-void rtc_sleep_low_init(uint32_t slowclk_period);
+void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp);
 
 #define RTC_EXT0_TRIG_EN    BIT(0)  //!< EXT0 GPIO wakeup
 #define RTC_EXT1_TRIG_EN    BIT(1)  //!< EXT1 GPIO wakeup

components/esp_hw_support/port/esp32/rtc_sleep.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -235,12 +235,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
     REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
 }
 
-void rtc_sleep_low_init(uint32_t slowclk_period)
+void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp)
 {
     // set 5 PWC state machine times to fit in main state machine time
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, dslp ? RTC_CNTL_PLL_BUF_WAIT_DEFAULT : RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, dslp ? RTC_CNTL_XTL_BUF_WAIT_DEFAULT : rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, dslp ? RTC_CNTL_CK8M_WAIT_DEFAULT : RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
 }
 
 /* Read back 'reject' status when waking from light or deep sleep */

components/esp_hw_support/port/esp32c2/include/soc/rtc.h

@@ -598,8 +598,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg);
  * used in lightsleep mode.
  *
  * @param slowclk_period re-calibrated slow clock period
+ * @param dslp true if initialize for deepsleep request
  */
-void rtc_sleep_low_init(uint32_t slowclk_period);
+void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp);
 
 #define RTC_GPIO_TRIG_EN            BIT(2)  //!< GPIO wakeup
 #define RTC_TIMER_TRIG_EN           BIT(3)  //!< Timer wakeup

components/esp_hw_support/port/esp32c2/rtc_sleep.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -193,12 +193,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
     REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu);
 }
 
-void rtc_sleep_low_init(uint32_t slowclk_period)
+void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp)
 {
     // set 5 PWC state machine times to fit in main state machine time
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, dslp ? RTC_CNTL_PLL_BUF_WAIT_DEFAULT : RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, dslp ? RTC_CNTL_XTL_BUF_WAIT_DEFAULT : rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, dslp ? RTC_CNTL_CK8M_WAIT_DEFAULT : RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
 }
 
 static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);

components/esp_hw_support/port/esp32c3/include/soc/rtc.h

@@ -644,8 +644,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg);
  * used in lightsleep mode.
  *
  * @param slowclk_period re-calibrated slow clock period
+ * @param dslp true if initialize for deepsleep request
  */
-void rtc_sleep_low_init(uint32_t slowclk_period);
+void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp);
 
 #define RTC_GPIO_TRIG_EN            BIT(2)  //!< GPIO wakeup
 #define RTC_TIMER_TRIG_EN           BIT(3)  //!< Timer wakeup

components/esp_hw_support/port/esp32c3/rtc_sleep.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -244,12 +244,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
     REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu);
 }
 
-void rtc_sleep_low_init(uint32_t slowclk_period)
+void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp)
 {
     // set 5 PWC state machine times to fit in main state machine time
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, dslp ? RTC_CNTL_PLL_BUF_WAIT_DEFAULT : RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, dslp ? RTC_CNTL_XTL_BUF_WAIT_DEFAULT : rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, dslp ? RTC_CNTL_CK8M_WAIT_DEFAULT : RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
 }
 
 static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);

components/esp_hw_support/port/esp32s2/include/soc/rtc.h

@@ -669,8 +669,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg);
  * used in lightsleep mode.
  *
  * @param slowclk_period re-calibrated slow clock period
+ * @param dslp true if initialize for deepsleep request
  */
-void rtc_sleep_low_init(uint32_t slowclk_period);
+void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp);
 
 #define RTC_EXT0_TRIG_EN    BIT(0)  //!< EXT0 GPIO wakeup
 #define RTC_EXT1_TRIG_EN    BIT(1)  //!< EXT1 GPIO wakeup

components/esp_hw_support/port/esp32s2/memprot.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -787,6 +787,13 @@ esp_err_t esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature, uin
     bool use_peri1 = required_mem_prot & MEMPROT_PERI1_RTCSLOW;
     bool use_peri2 = required_mem_prot & MEMPROT_PERI2_RTCSLOW_0 || required_mem_prot & MEMPROT_PERI2_RTCSLOW_1;
 
+    // make sure there is no pending interrupt, this may be the case if the target just rebooted
+    // after a memory protection fault.
+    memprot_ll_iram0_clear_intr();
+    memprot_ll_dram0_clear_intr();
+    memprot_ll_peri1_clear_intr();
+    memprot_ll_peri2_clear_intr();
+
     //disable protection
     if (use_iram0 && (ret = esp_memprot_intr_ena(MEMPROT_IRAM0_SRAM, false)) != ESP_OK) {
         return ret;
@@ -865,7 +872,7 @@ esp_err_t esp_memprot_set_prot(bool invoke_panic_handler, bool lock_feature, uin
             }
         }
 
-        //reenable protection (bus based)
+        //re-enable protection (bus based)
         if (use_iram0 && (ret = esp_memprot_intr_ena(MEMPROT_IRAM0_SRAM, true)) != ESP_OK) {
             return ret;
         }

components/esp_hw_support/port/esp32s2/rtc_sleep.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -249,11 +249,11 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
     REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
 }
 
-void rtc_sleep_low_init(uint32_t slowclk_period)
+void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp)
 {
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, dslp ? RTC_CNTL_PLL_BUF_WAIT_DEFAULT : RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, dslp ? RTC_CNTL_XTL_BUF_WAIT_DEFAULT : rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, dslp ? RTC_CNTL_CK8M_WAIT_DEFAULT : RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
 }
 
 /* Read back 'reject' status when waking from light or deep sleep */

components/esp_hw_support/port/esp32s3/include/soc/rtc.h

@@ -655,8 +655,9 @@ void rtc_sleep_init(rtc_sleep_config_t cfg);
  * used in lightsleep mode.
  *
  * @param slowclk_period re-calibrated slow clock period
+ * @param dslp true if initialize for deepsleep request
  */
-void rtc_sleep_low_init(uint32_t slowclk_period);
+void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp);
 
 #define RTC_EXT0_TRIG_EN    BIT(0)  //!< EXT0 GPIO wakeup
 #define RTC_EXT1_TRIG_EN    BIT(1)  //!< EXT1 GPIO wakeup

components/esp_hw_support/port/esp32s3/rtc_sleep.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -256,12 +256,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
     REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu);
 }
 
-void rtc_sleep_low_init(uint32_t slowclk_period)
+void rtc_sleep_low_init(uint32_t slowclk_period, bool dslp)
 {
     // set 5 PWC state machine times to fit in main state machine time
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, dslp ? RTC_CNTL_PLL_BUF_WAIT_DEFAULT : RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, dslp ? RTC_CNTL_XTL_BUF_WAIT_DEFAULT : rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
-    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, dslp ? RTC_CNTL_CK8M_WAIT_DEFAULT : RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
 }
 
 static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);

components/esp_hw_support/sleep_modes.c

@@ -956,9 +956,7 @@ static esp_err_t IRAM_ATTR esp_sleep_start(uint32_t sleep_flags, esp_sleep_mode_
     rtc_sleep_init(config);
 
     // Set state machine time for light sleep
-    if (!deep_sleep) {
+    rtc_sleep_low_init(s_config.rtc_clk_cal_period, deep_sleep);
-        rtc_sleep_low_init(s_config.rtc_clk_cal_period);
-    }
 #endif
 
     // Configure timer wakeup

components/esp_ringbuf/include/freertos/ringbuf.h

@@ -420,10 +420,6 @@ size_t xRingbufferGetMaxItemSize(RingbufHandle_t xRingbuffer);
  * buffer. This represents the maximum size an item/data can have if it was
  * currently sent to the ring buffer.
  *
- * @warning This API is not thread safe. So, if multiple threads are accessing
- *          the same ring buffer, it is the application's responsibility to
- *          ensure atomic access to this API and the subsequent Send
- *
  * @note    An empty no-split buffer has a max current free size for an item
  *          that is limited to ((buffer_size/2)-header_size). See API reference
  *          for xRingbufferGetMaxItemSize().

components/esp_rom/CMakeLists.txt

@@ -27,7 +27,7 @@ else()
 
     # Override regi2c implementation in ROM
     if(CONFIG_ESP_ROM_HAS_REGI2C_BUG OR CONFIG_ESP_ROM_WITHOUT_REGI2C)
-        if(target STREQUAL "esp32c6" OR target STREQUAL "esp32c5")
+        if(target STREQUAL "esp32c6" OR target STREQUAL "esp32c5" OR target STREQUAL "esp32h4")
             list(APPEND sources "patches/esp_rom_hp_regi2c_${target}.c")
         else()
             list(APPEND sources "patches/esp_rom_regi2c_${target}.c")

components/esp_rom/esp32/ld/esp32.rom.ld

@@ -663,6 +663,7 @@ PROVIDE ( ld_acl_rsw_frm_cbk = 0x40033bb0 );
 PROVIDE ( ld_sco_modify = 0x40031778 );
 PROVIDE ( lm_cmd_cmp_send = 0x40051838 );
 PROVIDE ( ld_sco_frm_cbk = 0x400349dc );
+PROVIDE ( ld_sco_evt_start_cbk = 0x40031afc );
 PROVIDE ( ld_sco_evt_stop_cbk = 0x40031d78 );
 PROVIDE ( ld_acl_rsw_evt_start_cbk = 0x40031154 );
 PROVIDE ( ld_acl_sco_rsvd_check = 0x4002fa94 );

components/esp_rom/esp32h4/Kconfig.soc_caps.in

@@ -0,0 +1,68 @@
+#####################################################
+# This file is auto-generated from SoC caps
+# using gen_soc_caps_kconfig.py, do not edit manually
+#####################################################
+
+config ESP_ROM_HAS_CRC_LE
+    bool
+    default y
+
+config ESP_ROM_HAS_CRC_BE
+    bool
+    default y
+
+config ESP_ROM_UART_CLK_IS_XTAL
+    bool
+    default y
+
+config ESP_ROM_USB_SERIAL_DEVICE_NUM
+    int
+    default 3
+
+config ESP_ROM_HAS_RETARGETABLE_LOCKING
+    bool
+    default y
+
+config ESP_ROM_GET_CLK_FREQ
+    bool
+    default y
+
+config ESP_ROM_HAS_HAL_WDT
+    bool
+    default y
+
+config ESP_ROM_HAS_HAL_SYSTIMER
+    bool
+    default y
+
+config ESP_ROM_HAS_HEAP_TLSF
+    bool
+    default y
+
+config ESP_ROM_HAS_LAYOUT_TABLE
+    bool
+    default y
+
+config ESP_ROM_HAS_SPI_FLASH
+    bool
+    default y
+
+config ESP_ROM_WITHOUT_REGI2C
+    bool
+    default y
+
+config ESP_ROM_HAS_NEWLIB
+    bool
+    default y
+
+config ESP_ROM_HAS_NEWLIB_NANO_FORMAT
+    bool
+    default y
+
+config ESP_ROM_WDT_INIT_PATCH
+    bool
+    default y
+
+config ESP_ROM_RAM_APP_NEEDS_MMU_INIT
+    bool
+    default y

components/esp_rom/esp32h4/esp_rom_caps.h

@@ -0,0 +1,24 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define ESP_ROM_HAS_CRC_LE                  (1) // ROM CRC library supports Little Endian
+#define ESP_ROM_HAS_CRC_BE                  (1) // ROM CRC library supports Big Endian
+#define ESP_ROM_UART_CLK_IS_XTAL            (1) // UART clock source is selected to XTAL in ROM
+#define ESP_ROM_USB_SERIAL_DEVICE_NUM       (3) // UART uses USB_SERIAL_JTAG port in ROM.
+#define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
+#define ESP_ROM_GET_CLK_FREQ                (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
+#define ESP_ROM_HAS_HAL_WDT                 (1) // ROM has the implementation of Watchdog HAL driver
+#define ESP_ROM_HAS_HAL_SYSTIMER            (1) // ROM has the implementation of Systimer HAL driver
+#define ESP_ROM_HAS_HEAP_TLSF               (1) // ROM has the implementation of the tlsf and multi-heap library
+#define ESP_ROM_HAS_LAYOUT_TABLE            (1) // ROM has the layout table
+#define ESP_ROM_HAS_SPI_FLASH               (1) // ROM has the implementation of SPI Flash driver
+#define ESP_ROM_WITHOUT_REGI2C              (1) // ROM has the regi2c bug or rom does not support regi2c function
+#define ESP_ROM_HAS_NEWLIB                  (1) // ROM has newlib (at least parts of it) functions included
+#define ESP_ROM_HAS_NEWLIB_NANO_FORMAT      (1) // ROM has the newlib nano versions of formatting functions
+#define ESP_ROM_WDT_INIT_PATCH              (1) // ROM version does not configure the clock
+#define ESP_ROM_RAM_APP_NEEDS_MMU_INIT      (1) // ROM doesn't init cache MMU when it's a RAM APP, needs MMU hal to init

components/esp_rom/esp32h4/include/esp32h4/rom/cache.h

@@ -0,0 +1,633 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "esp_bit_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: [ESP32H4] IDF-12289 inherit from verification branch, need check
+
+/** \defgroup cache_apis, cache operation related apis
+  * @brief cache apis
+  */
+
+/** @addtogroup cache_apis
+  * @{
+  */
+#define MIN_ICACHE_SIZE                 16384
+#define MAX_ICACHE_SIZE                 16384
+#define MIN_ICACHE_WAYS                 8
+#define MAX_ICACHE_WAYS                 8
+#define MAX_CACHE_WAYS                  8
+#define MIN_CACHE_LINE_SIZE             32
+#define TAG_SIZE                        4
+#define MIN_ICACHE_BANK_NUM             1
+#define MAX_ICACHE_BANK_NUM             1
+#define CACHE_MEMORY_BANK_NUM           1
+#define CACHE_MEMORY_IBANK_SIZE         0x4000
+
+#define MAX_ITAG_BANK_ITEMS             (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE)
+#define MAX_ITAG_BLOCK_ITEMS            (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE)
+#define MAX_ITAG_BANK_SIZE              (MAX_ITAG_BANK_ITEMS * TAG_SIZE)
+#define MAX_ITAG_BLOCK_SIZE             (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE)
+
+typedef enum {
+    CACHE_LOCK_LOCK = BIT(0),
+    CACHE_LOCK_UNLOCK = BIT(1),
+} cache_lock_t;
+
+typedef enum {
+    CACHE_SYNC_INVALIDATE = BIT(0),
+    CACHE_SYNC_CLEAN = BIT(1),
+    CACHE_SYNC_WRITEBACK = BIT(2),
+    CACHE_SYNC_WRITEBACK_INVALIDATE = BIT(3),
+} cache_sync_t;
+
+#define CACHE_MAP_ROM_CACHE   BIT(2)
+#define CACHE_MAP_FLASH_CACHE BIT(4)
+
+typedef enum {
+    CACHE_SIZE_HALF = 0,                /*!< 8KB for icache and dcache */
+    CACHE_SIZE_FULL = 1,                /*!< 16KB for icache and dcache */
+} cache_size_t;
+
+typedef enum {
+    CACHE_4WAYS_ASSOC = 0,              /*!< 4 way associated cache */
+    CACHE_8WAYS_ASSOC = 1,              /*!< 8 way associated cache */
+} cache_ways_t;
+
+typedef enum {
+    CACHE_LINE_SIZE_16B = 0,            /*!< 16 Byte cache line size */
+    CACHE_LINE_SIZE_32B = 1,            /*!< 32 Byte cache line size */
+    CACHE_LINE_SIZE_64B = 2,            /*!< 64 Byte cache line size */
+} cache_line_size_t;
+
+typedef enum {
+    CACHE_AUTOLOAD_POSITIVE = 0,        /*!< cache autoload step is positive */
+    CACHE_AUTOLOAD_NEGATIVE = 1,        /*!< cache autoload step is negative */
+} cache_autoload_order_t;
+
+#define CACHE_AUTOLOAD_STEP(i) ((i) - 1)
+
+typedef enum {
+    CACHE_AUTOLOAD_MISS_TRIGGER = 0,    /*!< autoload only triggered by cache miss */
+    CACHE_AUTOLOAD_HIT_TRIGGER  = 1,    /*!< autoload only triggered by cache hit */
+    CACHE_AUTOLOAD_BOTH_TRIGGER = 2,    /*!< autoload triggered both by cache miss and hit */
+} cache_autoload_trigger_t;
+
+typedef enum {
+    CACHE_FREEZE_ACK_BUSY = 0,          /*!< in this mode, cache ack busy to CPU if a cache miss happens*/
+    CACHE_FREEZE_ACK_ERROR  = 1,        /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */
+} cache_freeze_mode_t;
+
+typedef enum {
+    MMU_PAGE_MODE_64KB = 0,
+    MMU_PAGE_MODE_32KB = 1,
+    MMU_PAGE_MODE_16KB = 2,
+    MMU_PAGE_MODE_8KB = 3,
+    MMU_PAGE_MODE_INVALID,
+} mmu_page_mode_t;
+
+struct cache_mode {
+    uint32_t cache_size;                /*!< cache size in byte */
+    uint16_t cache_line_size;           /*!< cache line size in byte */
+    uint8_t cache_ways;                 /*!< cache ways, always 4 */
+    uint8_t ibus;                     /*!< the cache index, 0 for dcache, 1 for icache */
+};
+
+struct icache_tag_item {
+    uint32_t valid:1;                   /*!< the tag item is valid or not */
+    uint32_t lock:1;                    /*!< the cache line is locked or not */
+    uint32_t fifo_cnt:3;                /*!< fifo cnt, 0 ~ 3 for 4 ways cache */
+    uint32_t tag:13;                    /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */
+    uint32_t reserved:14;
+};
+
+struct autoload_config {
+    uint8_t order;                      /*!< autoload step is positive or negative */
+    uint8_t trigger;                    /*!< autoload trigger */
+    uint8_t ena0;                       /*!< autoload region0 enable */
+    uint8_t ena1;                       /*!< autoload region1 enable */
+    uint32_t addr0;                     /*!< autoload region0 start address */
+    uint32_t size0;                     /*!< autoload region0 size */
+    uint32_t addr1;                     /*!< autoload region1 start address */
+    uint32_t size1;                     /*!< autoload region1 size */
+};
+
+struct tag_group_info {
+    struct cache_mode mode;                         /*!< cache and cache mode */
+    uint32_t filter_addr;                           /*!< the address that used to generate the struct */
+    uint32_t vaddr_offset;                          /*!< virtual address offset of the cache ways */
+    uint32_t tag_addr[MAX_CACHE_WAYS];              /*!< tag memory address, only [0~mode.ways-1] is valid to use */
+    uint32_t cache_memory_offset[MAX_CACHE_WAYS];   /*!< cache memory address, only [0~mode.ways-1] is valid to use */
+};
+
+struct lock_config {
+    uint32_t addr;                                  /*!< manual lock address*/
+    uint16_t size;                                  /*!< manual lock size*/
+    uint16_t group;                                 /*!< manual lock group, 0 or 1*/
+};
+
+struct cache_internal_stub_table {
+    /* cache mode */
+    uint32_t (*cache_line_size)(uint32_t map);
+    uint32_t (*cache_addr)(uint32_t addr);
+    /* cache ops */
+    void (*sync_cache_items)(uint32_t type, uint32_t map, uint32_t addr, uint32_t bytes);
+    void (*lock_cache_items)(uint32_t lock, uint32_t map, uint32_t addr, uint32_t bytes);
+    // these 4 functions are likely to patch
+    uint32_t (*suspend_cache_autoload)(uint32_t map);
+    void (*resume_cache_autoload)(uint32_t autoload);
+    void (*freeze_cache_enable)(uint32_t map, cache_freeze_mode_t mode);
+    void (*freeze_cache_disable)(uint32_t map);
+    int (*op_addr)(uint32_t op_type,
+                   uint32_t map,
+                   uint32_t start_addr,
+                   uint32_t size,
+                   uint32_t cache_line_size,
+                   uint32_t max_sync_num,
+                   void (*cache_Op)(uint32_t, uint32_t, uint32_t, uint32_t));
+};
+
+/* Defined in the interface file, default value is rom_default_cache_internal_table */
+extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr;
+
+// this define is hardware register compatible, do not modify it!
+#define CACHE_MAP_ICACHE0 BIT(0)
+#define CACHE_MAP_ICACHE1 BIT(1)
+#define CACHE_MAP_DCACHE  BIT(4)
+#define CACHE_MAP_ALL     (CACHE_MAP_ICACHE0 | CACHE_MAP_ICACHE1 | CACHE_MAP_DCACHE)
+
+// keep the software flag same as map value
+#define CACHE_AUTOLOAD_ICACHE0_FLAG BIT(0)
+#define CACHE_AUTOLOAD_ICACHE1_FLAG BIT(1)
+#define CACHE_AUTOLOAD_DCACHE_FLAG  BIT(4)
+
+// keep this software flag same as map value
+#define CACHE_PRELOAD_DONE_ICACHE0_FLAG BIT(0)
+#define CACHE_PRELOAD_DONE_ICACHE1_FLAG BIT(1)
+#define CACHE_PRELOAD_DONE_DCACHE_FLAG  BIT(4)
+
+typedef void (* cache_op_start)(void);
+typedef void (* cache_op_end)(void);
+
+typedef struct {
+    cache_op_start start;
+    cache_op_end end;
+} cache_op_cb_t;
+
+/* Defined in the interface file, default value is NULL */
+extern const cache_op_cb_t* rom_cache_op_cb;
+
+#define ESP_ROM_ERR_INVALID_ARG         1
+#define MMU_SET_ADDR_ALIGNED_ERROR      2
+#define MMU_SET_PASE_SIZE_ERROR         3
+#define MMU_SET_VADDR_OUT_RANGE         4
+
+#define CACHE_OP_ICACHE_Y               1
+#define CACHE_OP_ICACHE_N               0
+
+/**
+  * @brief Initialise cache mmu, mark all entries as invalid.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void Cache_MMU_Init(void);
+
+/**
+  * @brief Init Cache for ROM boot, including resetting the Icache, initializing MMU, Enabling ICache, unmasking bus.
+  *
+  * @param None
+  *
+  * @return None
+  */
+void ROM_Boot_Cache_Init(void);
+
+/**
+  * @brief Set ICache mmu mapping.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint32_t senitive : Config this page should apply flash encryption or not
+  *
+  * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In
+  *                 esp32c6, external memory is always flash
+  *
+  * @param  uint32_t vaddr : virtual address in CPU address space.
+  *                              Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address.
+  *                              Should be aligned by psize.
+  *
+  * @param  uint32_t paddr : physical address in external memory.
+  *                              Should be aligned by psize.
+  *
+  * @param  uint32_t psize : page size of ICache, in kilobytes. Should be 64 here.
+  *
+  * @param  uint32_t num : pages to be set.
+  *
+  * @param  uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
+  *
+  * @return uint32_t: error status
+  *                   0 : mmu set success
+  *                   2 : vaddr or paddr is not aligned
+  *                   3 : psize error
+  *                   4 : vaddr is out of range
+  */
+int Cache_MSPI_MMU_Set(uint32_t sensitive, uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,  uint32_t psize, uint32_t num, uint32_t fixed);
+
+/**
+  * @brief Set DCache mmu mapping.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In
+  *                 esp32c6, external memory is always flash
+  *
+  * @param  uint32_t vaddr : virtual address in CPU address space.
+  *                              Can be DRam0, DRam1, DRom0, DPort and AHB buses address.
+  *                              Should be aligned by psize.
+  *
+  * @param  uint32_t paddr : physical address in external memory.
+  *                              Should be aligned by psize.
+  *
+  * @param  uint32_t psize : page size of DCache, in kilobytes. Should be 64 here.
+  *
+  * @param  uint32_t num : pages to be set.
+
+  * @param  uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
+  *
+  * @return uint32_t: error status
+  *                   0 : mmu set success
+  *                   2 : vaddr or paddr is not aligned
+  *                   3 : psize error
+  *                   4 : vaddr is out of range
+  */
+int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed);
+
+
+/**
+  * @brief Get cache mode of ICache or DCache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field
+  *
+  * return none
+  */
+void Cache_Get_Mode(struct cache_mode * mode);
+
+/**
+  * @brief Invalidate the cache items for ICache.
+  *        Operation will be done CACHE_LINE_SIZE aligned.
+  *        If the region is not in ICache addr room, nothing will be done.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t addr: start address to invalidate
+  *
+  * @param  uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
+  *
+  * @return None
+  */
+void Cache_Sync_Items(uint32_t type, uint32_t map, uint32_t addr, uint32_t bytes);
+
+/**
+  * @brief Invalidate the Cache items in the region from ICache or DCache.
+  *        If the region is not in Cache addr room, nothing will be done.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t addr : invalidated region start address.
+  *
+  * @param  uint32_t size : invalidated region size.
+  *
+  * @return 0 for success
+  *         1 for invalid argument
+  */
+int Cache_Invalidate_Addr(uint32_t map, uint32_t addr, uint32_t size);
+
+int Cache_Clean_Addr(uint32_t addr, uint32_t size);
+
+int Cache_WriteBack_Addr(uint32_t addr, uint32_t size);
+
+int Cache_WriteBack_Invalidate_Addr(uint32_t addr, uint32_t size);
+
+/**
+  * @brief Invalidate all cache items in ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void Cache_Invalidate_All(uint32_t map);
+
+void Cache_Clean_All(void);
+
+void Cache_WriteBack_All(void);
+
+void Cache_WriteBack_Invalidate_All(void);
+
+/**
+  * @brief Mask all buses through ICache and DCache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void Cache_Mask_All(void);
+
+/**
+  * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  None
+  *
+  * @return uint32_t : 0 for ICache not auto preload before suspend.
+  */
+uint32_t Cache_Suspend_Autoload(uint32_t map);
+
+/**
+  * @brief Resume ICache auto preload operation after some ICache operations.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint32_t autoload : 0 for ICache not auto preload before suspend.
+  *
+  * @return None.
+  */
+void Cache_Resume_Autoload(uint32_t autoload);
+
+/**
+  * @brief Start an ICache manual preload, will suspend auto preload of ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint32_t addr : start address of the preload region.
+  *
+  * @param uint32_t size : size of the preload region, should not exceed the size of ICache.
+  *
+  * @param uint32_t order : the preload order, 0 for positive, other for negative
+  *
+  * @return uint32_t : 0 for ICache not auto preload before manual preload.
+  */
+uint32_t Cache_Start_Preload(uint32_t map, uint32_t addr, uint32_t size, uint32_t order);
+
+/**
+  * @brief Return if the ICache manual preload done.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  None
+  *
+  * @return uint32_t : 0 for ICache manual preload not done.
+  */
+uint32_t Cache_Preload_Done(uint32_t map);
+
+/**
+  * @brief End the ICache manual preload to resume auto preload of ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint32_t autoload : 0 for ICache not auto preload before manual preload.
+  *
+  * @return None
+  */
+void Cache_End_Preload(uint32_t autoload);
+
+/**
+  * @brief Config autoload parameters of ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param struct autoload_config * config : autoload parameters.
+  *
+  * @return None
+  */
+void Cache_Config_Autoload(uint32_t map, const struct autoload_config * config);
+
+/**
+  * @brief Enable auto preload for ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param None
+  *
+  * @return None
+  */
+void Cache_Enable_Autoload(uint32_t map);
+
+/**
+  * @brief Disable auto preload for ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param None
+  *
+  * @return None
+  */
+void Cache_Disable_Autoload(uint32_t map);
+
+/**
+  * @brief Config a group of prelock parameters of ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param struct lock_config * config : a group of lock parameters.
+  *
+  * @return None
+  */
+
+void Cache_Enable_PreLock(uint32_t map, const struct lock_config *config);
+
+/**
+  * @brief Disable a group of prelock parameters for ICache.
+  *        However, the locked data will not be released.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint16_t group : 0 for group0, 1 for group1.
+  *
+  * @return None
+  */
+void Cache_Disable_PreLock(uint32_t map, uint16_t group);
+
+/**
+  * @brief Lock the cache items for ICache.
+  *        Operation will be done CACHE_LINE_SIZE aligned.
+  *        If the region is not in ICache addr room, nothing will be done.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t addr: start address to lock
+  *
+  * @param  uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
+  *
+  * @return None
+  */
+int Cache_Lock_Items(uint32_t lock, uint32_t map, uint32_t addr, uint32_t items);
+
+/**
+  * @brief Lock the cache items in tag memory for ICache or DCache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint32_t addr : start address of lock region.
+  *
+  * @param uint32_t size : size of lock region.
+  *
+  * @return 0 for success
+  *         1 for invalid argument
+  */
+int Cache_Lock_Addr(uint32_t map, uint32_t addr, uint32_t size);
+
+/**
+  * @brief Unlock the cache items in tag memory for ICache or DCache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint32_t addr : start address of unlock region.
+  *
+  * @param uint32_t size : size of unlock region.
+  *
+  * @return 0 for success
+  *         1 for invalid argument
+  */
+int Cache_Unlock_Addr(uint32_t map, uint32_t addr, uint32_t size);
+
+/**
+  * @brief Disable ICache access for the cpu.
+  *        This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle.
+  *        Please do not call this function in your SDK application.
+  *
+  * @return uint32_t : auto preload enabled before
+  */
+uint32_t Cache_Disable_Cache(uint32_t map);
+
+/**
+  * @brief Enable ICache access for the cpu.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t autoload : ICache will preload then.
+  *
+  * @return None
+  */
+void Cache_Enable_Cache(uint32_t map, uint32_t autoload);
+
+/**
+  * @brief Suspend ICache access for the cpu.
+  *        The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle.
+  *        Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case).
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  None
+  *
+  * @return uint32_t : auto preload enabled before
+  */
+uint32_t Cache_Suspend_Cache(uint32_t map);
+
+/**
+  * @brief Resume ICache access for the cpu.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t autoload : ICache will preload then.
+  *
+  * @return None
+  */
+void Cache_Resume_Cache(uint32_t map, uint32_t autoload);
+
+/**
+  * @brief Get ICache cache line size
+  *
+  * @param  None
+  *
+  * @return uint32_t: 16, 32, 64 Byte
+  */
+uint32_t Cache_Get_Line_Size(uint32_t map);
+
+/**
+  * @brief Enable freeze for ICache.
+  *        Any miss request will be rejected, including cpu miss and preload/autoload miss.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit
+  *
+  * @return None
+  */
+void Cache_Freeze_Enable(uint32_t map, cache_freeze_mode_t mode);
+
+/**
+  * @brief Disable freeze for ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @return None
+  */
+void Cache_Freeze_Disable(uint32_t map);
+
+/**
+  * @brief Travel tag memory to run a call back function.
+  *        ICache and DCache are suspend when doing this.
+  *        The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  struct cache_mode * mode : the cache to check and the cache mode.
+  *
+  * @param  uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function.
+  *                                0 for do not filter, all cache lines will be returned.
+  *
+  * @param  void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time.
+  *
+  * @return None
+  */
+void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *));
+
+/**
+  * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  struct cache_mode * mode : the cache to calculate the virtual address and the cache mode.
+  *
+  * @param  uint32_t tag : the tag part of a tag item, 12-14 bits.
+  *
+  * @param  uint32_t addr_offset : the virtual address offset of the cache ways.
+  *
+  * @return uint32_t : the virtual address.
+  */
+uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset);
+
+/**
+  * @}
+  */
+
+/**
+  * @brief Get the cache MMU IROM end address.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  void
+  *
+  * @return uint32_t : the word value of the address.
+  */
+uint32_t Cache_Get_IROM_MMU_End(void);
+
+/**
+  * @brief Get the cache MMU DROM end address.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  void
+  *
+  * @return uint32_t : the word value of the address.
+  */
+uint32_t Cache_Get_DROM_MMU_End(void);
+
+/**
+ * @brief Configure cache MMU page size according to instruction and rodata size
+ *
+ * @param irom_size The instruction cache MMU page size
+ * @param drom_size The rodata data cache MMU page size
+ */
+void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size);
+
+uint32_t Cache_Count_Flash_Pages(uint32_t * page0_mapped);
+
+uint32_t Cache_Flash_To_SPIRAM_Copy(uint32_t bus_start_addr, uint32_t start_page, uint32_t * page0_page);
+
+#define Cache_Dbus_MMU_Set(ext_ram, vaddr, paddr, psize, num, fixed) \
+    Cache_MSPI_MMU_Set(ets_efuse_cache_encryption_enabled() ? SOC_MMU_SENSITIVE : 0, ext_ram, vaddr, paddr, psize, num, fixed)
+
+#ifdef __cplusplus
+}
+#endif

components/esp_rom/esp32h4/include/esp32h4/rom/ecdsa.h

@@ -0,0 +1,28 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: [ESP32H4] IDF-12259 inherit from verification branch, need check
+
+#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */
+
+typedef enum {
+    ECDSA_CURVE_P192 = 1,
+    ECDSA_CURVE_P256 = 2
+} ECDSA_CURVE;
+
+int ets_ecdsa_verify(const uint8_t *key, const uint8_t *sig, ECDSA_CURVE curve_id, const uint8_t *digest, uint8_t *verified_digest);
+
+#ifdef __cplusplus
+}
+#endif

components/esp_rom/esp32h4/include/esp32h4/rom/efuse.h

@@ -0,0 +1,285 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ROM_EFUSE_H_
+#define _ROM_EFUSE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: [ESP32H4] IDF-12322 inherit from verification branch, need check
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+/** \defgroup efuse_APIs efuse APIs
+  * @brief     ESP32 efuse read/write APIs
+  * @attention
+  *
+  */
+
+/** @addtogroup efuse_APIs
+  * @{
+  */
+
+typedef enum {
+    ETS_EFUSE_KEY_PURPOSE_USER = 0,
+    ETS_EFUSE_KEY_PURPOSE_RESERVED = 1,
+    ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4,
+    ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5,
+    ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6,
+    ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7,
+    ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8,
+    ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9,
+    ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10,
+    ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11,
+    ETS_EFUSE_KEY_PURPOSE_MAX,
+} ets_efuse_purpose_t;
+
+typedef enum {
+    ETS_EFUSE_BLOCK0 = 0,
+    ETS_EFUSE_MAC_SPI_SYS_0 = 1,
+    ETS_EFUSE_BLOCK_SYS_DATA = 2,
+    ETS_EFUSE_BLOCK_USR_DATA = 3,
+    ETS_EFUSE_BLOCK_KEY0 = 4,
+    ETS_EFUSE_BLOCK_KEY1 = 5,
+    ETS_EFUSE_BLOCK_KEY2 = 6,
+    ETS_EFUSE_BLOCK_KEY3 = 7,
+    ETS_EFUSE_BLOCK_KEY4 = 8,
+    ETS_EFUSE_BLOCK_KEY5 = 9,
+    ETS_EFUSE_BLOCK_KEY6 = 10,
+    ETS_EFUSE_BLOCK_MAX,
+} ets_efuse_block_t;
+
+/**
+  * @brief  Efuse read operation: copies data from physical efuses to efuse read registers.
+  *
+  * @param  null
+  *
+  * @return : 0 if success, others if apb clock is not accepted
+  */
+int ets_efuse_read(void);
+
+/**
+  * @brief  Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time.
+  *
+  * @note This function does not update read efuses, call ets_efuse_read() once all programming is complete.
+  *
+  * @return : 0 if success, others if apb clock is not accepted
+  */
+int ets_efuse_program(ets_efuse_block_t block);
+
+/**
+ * @brief Set all Efuse program registers to zero.
+ *
+ * Call this before writing new data to the program registers.
+ */
+void ets_efuse_clear_program_registers(void);
+
+/**
+ * @brief Program a block of key data to an efuse block
+ *
+ * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused).
+ * @param purpose Purpose to set for this key. Purpose must be already unset.
+ * @param data Pointer to data to write.
+ * @param data_len Length of data to write.
+ *
+ * @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose)
+ */
+int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len);
+
+
+/* @brief Return the address of a particular efuse block's first read register
+ *
+ * @param block Index of efuse block to look up
+ *
+ * @return 0 if block is invalid, otherwise a numeric read register address
+ * of the first word in the block.
+ */
+uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block);
+
+/**
+ * @brief Return the current purpose set for an efuse key block
+ *
+ * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6.
+ */
+ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block);
+
+/**
+ * @brief Find a key block with the particular purpose set
+ *
+ * @param purpose Purpose to search for.
+ * @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists.
+ * @return true if found, false if not found. If false, value at key_block pointer is unchanged.
+ */
+bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block);
+
+/**
+ * Return true if the key block is unused, false otherwise.
+ *
+ * An unused key block is all zero content, not read or write protected,
+ * and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER)
+ *
+ * @param key_block key block to check.
+ *
+ * @return true if key block is unused, false if key block or used
+ * or the specified block index is not a key block.
+ */
+bool ets_efuse_key_block_unused(ets_efuse_block_t key_block);
+
+
+/**
+ * @brief Search for an unused key block and return the first one found.
+ *
+ * See @ref ets_efuse_key_block_unused for a description of an unused key block.
+ *
+ * @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found.
+ */
+ets_efuse_block_t ets_efuse_find_unused_key_block(void);
+
+/**
+ * @brief Return the number of unused efuse key blocks (0-6)
+ */
+unsigned ets_efuse_count_unused_key_blocks(void);
+
+/**
+ * @brief Calculate Reed-Solomon Encoding values for a block of efuse data.
+ *
+ * @param data Pointer to data buffer (length 32 bytes)
+ * @param rs_values Pointer to write encoded data to (length 12 bytes)
+ */
+void ets_efuse_rs_calculate(const void *data, void *rs_values);
+
+/**
+  * @brief  Read if download mode disabled from Efuse
+  *
+  * @return
+  * - true for efuse disable download mode.
+  * - false for efuse doesn't disable download mode.
+  */
+bool ets_efuse_download_modes_disabled(void);
+
+/**
+  * @brief  Read if uart print control value from Efuse
+  *
+  * @return
+  * - 0 for uart force print.
+  * - 1 for uart print when GPIO8 is low when digital reset.
+  *   2 for uart print when GPIO8 is high when digital reset.
+  *   3 for uart force silent
+  */
+uint32_t ets_efuse_get_uart_print_control(void);
+
+/**
+  * @brief  Read if usb download mode disabled from Efuse
+  *
+  * (Also returns true if security download mode is enabled, as this mode
+  * disables USB download.)
+  *
+  * @return
+  * - true for efuse disable usb download mode.
+  * - false for efuse doesn't disable usb download mode.
+  */
+bool ets_efuse_usb_download_mode_disabled(void);
+
+/**
+  * @brief  Read if security download modes enabled from Efuse
+  *
+  * @return
+  * - true for efuse enable security download mode.
+  * - false for efuse doesn't enable security download mode.
+  */
+bool ets_efuse_security_download_modes_enabled(void);
+
+/**
+ * @brief Return true if secure boot is enabled in EFuse
+ */
+bool ets_efuse_secure_boot_enabled(void);
+
+/**
+ * @brief Return true if secure boot aggressive revoke is enabled in EFuse
+ */
+bool ets_efuse_secure_boot_aggressive_revoke_enabled(void);
+
+/**
+ * @brief Return true if cache encryption (flash, etc) is enabled from boot via EFuse
+ */
+bool ets_efuse_cache_encryption_enabled(void);
+
+/**
+ * @brief Return true if EFuse indicates to send a flash resume command.
+ */
+bool ets_efuse_force_send_resume(void);
+
+/**
+  * @brief  return the time in us ROM boot need wait flash to power on from Efuse
+  *
+  * @return
+  * - uint32_t the time in us.
+  */
+uint32_t ets_efuse_get_flash_delay_us(void);
+
+#define EFUSE_SPICONFIG_SPI_DEFAULTS 0
+#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1
+
+#define EFUSE_SPICONFIG_RET_SPICLK_MASK         0x3f
+#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT        0
+#define EFUSE_SPICONFIG_RET_SPICLK(ret)         (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
+
+#define EFUSE_SPICONFIG_RET_SPIQ_MASK           0x3f
+#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT          6
+#define EFUSE_SPICONFIG_RET_SPIQ(ret)           (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
+
+#define EFUSE_SPICONFIG_RET_SPID_MASK           0x3f
+#define EFUSE_SPICONFIG_RET_SPID_SHIFT          12
+#define EFUSE_SPICONFIG_RET_SPID(ret)           (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
+
+#define EFUSE_SPICONFIG_RET_SPICS0_MASK         0x3f
+#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT        18
+#define EFUSE_SPICONFIG_RET_SPICS0(ret)         (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
+
+
+#define EFUSE_SPICONFIG_RET_SPIHD_MASK          0x3f
+#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT         24
+#define EFUSE_SPICONFIG_RET_SPIHD(ret)          (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
+
+/**
+ * @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into
+ * the JTAG_CTRL registers.
+ *
+ * Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse.
+ *
+ * Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match.
+ *
+ * @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user.
+ * @param key_block Index of a key block containing the source for this key.
+ *
+ * @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled.
+ */
+int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block);
+
+/**
+  * @brief  A crc8 algorithm used for MAC addresses in efuse
+  *
+  * @param  unsigned char const *p : Pointer to original data.
+  *
+  * @param  unsigned int len : Data length in byte.
+  *
+  * @return unsigned char: Crc value.
+  */
+unsigned char esp_crc8(unsigned char const *p, unsigned int len);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_EFUSE_H_ */

components/esp_rom/esp32h4/include/esp32h4/rom/esp_flash.h

@@ -0,0 +1,46 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Note: Most of esp_flash APIs in ROM are compatible with headers in ESP-IDF, this function
+   just adds ROM-specific parts
+*/
+
+struct spi_flash_chip_t;
+typedef struct esp_flash_t esp_flash_t;
+
+/* Structure to wrap "global" data used by esp_flash in ROM */
+typedef struct {
+    /* Default SPI flash chip, ie main chip attached to the MCU
+       This chip is used if the 'chip' argument passed to esp_flash_xxx API functions is ever NULL
+    */
+    esp_flash_t *default_chip;
+
+    /* Global API OS notification start/end/chip_check functions
+
+       These are used by ROM if no other host functions are configured.
+    */
+    struct {
+        esp_err_t (*start)(esp_flash_t *chip);
+        esp_err_t (*end)(esp_flash_t *chip, esp_err_t err);
+        esp_err_t (*chip_check)(esp_flash_t **inout_chip);
+    } api_funcs;
+} esp_flash_rom_global_data_t;
+
+/** Access a pointer to the global data used by the ROM spi_flash driver
+ */
+esp_flash_rom_global_data_t *esp_flash_get_rom_global_data(void);
+
+#ifdef __cplusplus
+}
+#endif

components/esp_rom/esp32h4/include/esp32h4/rom/ets_sys.h

@@ -0,0 +1,436 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ROM_ETS_SYS_H_
+#define _ROM_ETS_SYS_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: [ESP32H4] IDF-12321 inherit from verification branch, need check
+
+/** \defgroup ets_sys_apis, ets system related apis
+  * @brief ets system apis
+  */
+
+/** @addtogroup ets_sys_apis
+  * @{
+  */
+
+/************************************************************************
+  *                                NOTE
+  *   Many functions in this header files can't be run in FreeRTOS.
+  *   Please see the comment of the Functions.
+  *   There are also some functions that doesn't work on FreeRTOS
+  *   without listed in the header, such as:
+  *   xtos functions start with "_xtos_" in ld file.
+  *
+  ***********************************************************************
+  */
+
+/** \defgroup ets_apis, Espressif Task Scheduler related apis
+  * @brief ets apis
+  */
+
+/** @addtogroup ets_apis
+  * @{
+  */
+
+typedef enum {
+    ETS_OK     = 0, /**< return successful in ets*/
+    ETS_FAILED = 1, /**< return failed in ets*/
+    ETS_PENDING = 2,
+    ETS_BUSY = 3,
+    ETS_CANCEL = 4,
+} ETS_STATUS;
+
+typedef ETS_STATUS ets_status_t;
+
+typedef uint32_t ETSSignal;
+typedef uint32_t ETSParam;
+
+typedef struct ETSEventTag ETSEvent;    /**< Event transmit/receive in ets*/
+
+struct ETSEventTag {
+    ETSSignal sig;  /**< Event signal, in same task, different Event with different signal*/
+    ETSParam  par;  /**< Event parameter, sometimes without usage, then will be set as 0*/
+};
+
+typedef void (*ETSTask)(ETSEvent *e);       /**< Type of the Task processor*/
+typedef void (* ets_idle_cb_t)(void *arg);  /**< Type of the system idle callback*/
+
+
+
+
+
+/**
+  * @}
+  */
+
+/** \defgroup ets_boot_apis, Boot routing related apis
+  * @brief ets boot apis
+  */
+
+/** @addtogroup ets_apis
+  * @{
+  */
+
+extern const char *const exc_cause_table[40];   ///**< exception cause that defined by the core.*/
+
+/**
+  * @brief  Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed.
+  *         When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL.
+  *
+  * @param  uint32_t start : the PRO Entry code address value in uint32_t
+  *
+  * @return None
+  */
+void ets_set_user_start(uint32_t start);
+
+/**
+  * @}
+  */
+
+/** \defgroup ets_printf_apis, ets_printf related apis used in ets
+  * @brief ets printf apis
+  */
+
+/** @addtogroup ets_printf_apis
+  * @{
+  */
+
+/**
+  * @brief  Printf the strings to uart or other devices, similar with printf, simple than printf.
+  *         Can not print float point data format, or longlong data format.
+  *         So we maybe only use this in ROM.
+  *
+  * @param  const char *fmt : See printf.
+  *
+  * @param  ... : See printf.
+  *
+  * @return int : the length printed to the output device.
+  */
+int ets_printf(const char *fmt, ...);
+
+/**
+  * @brief Get the uart channel of ets_printf(uart_tx_one_char).
+  *
+  * @return uint8_t uart channel used by ets_printf(uart_tx_one_char).
+  */
+uint8_t ets_get_printf_channel(void);
+
+/**
+  * @brief  Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function.
+  *         Can not print float point data format, or longlong data format
+  *
+  * @param  char c : char to output.
+  *
+  * @return None
+  */
+void ets_write_char_uart(char c);
+
+/**
+  * @brief  Ets_printf have two output functions： putc1 and putc2, both of which will be called if need output.
+  *         To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode.
+  *
+  * @param  void (*)(char) p: Output function to install.
+  *
+  * @return None
+  */
+void ets_install_putc1(void (*p)(char c));
+
+/**
+  * @brief  Ets_printf have two output functions： putc1 and putc2, both of which will be called if need output.
+  *         To install putc2, which is defaulted installed as NULL.
+  *
+  * @param  void (*)(char) p: Output function to install.
+  *
+  * @return None
+  */
+void ets_install_putc2(void (*p)(char c));
+
+/**
+  * @brief  Install putc1 as ets_write_char_uart.
+  *         In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_install_uart_printf(void);
+
+#define ETS_PRINTF(...) ets_printf(...)
+
+#define ETS_ASSERT(v) do { \
+    if (!(v)) {             \
+        ets_printf("%s %u \n", __FILE__, __LINE__); \
+        while (1) {};   \
+    }                   \
+} while (0);
+
+/**
+  * @}
+  */
+
+/** \defgroup ets_timer_apis, ets_timer related apis used in ets
+  * @brief ets timer apis
+  */
+
+/** @addtogroup ets_timer_apis
+  * @{
+  */
+typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/
+
+typedef struct _ETSTIMER_ {
+    struct _ETSTIMER_    *timer_next;   /**< timer linker*/
+    uint32_t              timer_expire; /**< abstract time when timer expire*/
+    uint32_t              timer_period; /**< timer period, 0 means timer is not periodic repeated*/
+    ETSTimerFunc         *timer_func;   /**< timer handler*/
+    void                 *timer_arg;    /**< timer handler argument*/
+} ETSTimer;
+
+/**
+  * @brief  Init ets timer, this timer range is 640 us to 429496 ms
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_timer_init(void);
+
+/**
+  * @brief  In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_timer_deinit(void);
+
+/**
+  * @brief  Arm an ets timer, this timer range is 640 us to 429496 ms.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  ETSTimer *timer : Timer struct pointer.
+  *
+  * @param  uint32_t tmout : Timer value in ms, range is 1 to 429496.
+  *
+  * @param  bool repeat : Timer is periodic repeated.
+  *
+  * @return None
+  */
+void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat);
+
+/**
+  * @brief  Arm an ets timer, this timer range is 640 us to 429496 ms.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  ETSTimer *timer : Timer struct pointer.
+  *
+  * @param  uint32_t tmout : Timer value in us, range is 1 to 429496729.
+  *
+  * @param  bool repeat : Timer is periodic repeated.
+  *
+  * @return None
+  */
+void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat);
+
+/**
+  * @brief  Disarm an ets timer.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  ETSTimer *timer : Timer struct pointer.
+  *
+  * @return None
+  */
+void ets_timer_disarm(ETSTimer *timer);
+
+/**
+  * @brief  Set timer callback and argument.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  ETSTimer *timer : Timer struct pointer.
+  *
+  * @param  ETSTimerFunc *pfunction : Timer callback.
+  *
+  * @param  void *parg : Timer callback argument.
+  *
+  * @return None
+  */
+void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg);
+
+/**
+  * @brief  Unset timer callback and argument to NULL.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  ETSTimer *timer : Timer struct pointer.
+  *
+  * @return None
+  */
+void ets_timer_done(ETSTimer *ptimer);
+
+/**
+  * @brief  CPU do while loop for some time.
+  *         In FreeRTOS task, please call FreeRTOS apis.
+  *
+  * @param  uint32_t us : Delay time in us.
+  *
+  * @return None
+  */
+void ets_delay_us(uint32_t us);
+
+/**
+  * @brief  Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
+  *         Call this function when CPU frequency is changed.
+  *
+  * @param  uint32_t ticks_per_us : CPU ticks per us.
+  *
+  * @return None
+  */
+void ets_update_cpu_frequency(uint32_t ticks_per_us);
+
+
+
+/**
+  * @brief  Get the real CPU ticks per us to the ets.
+  *         This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency.
+  *
+  * @param  None
+  *
+  * @return uint32_t : CPU ticks per us record in ets.
+  */
+uint32_t ets_get_cpu_frequency(void);
+
+/**
+  * @}
+  */
+
+/** \defgroup ets_intr_apis, ets interrupt configure related apis
+  * @brief ets intr apis
+  */
+
+/** @addtogroup ets_intr_apis
+  * @{
+  */
+
+typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/
+
+/**
+  * @brief  Attach a interrupt handler to a CPU interrupt number.
+  *         This function equals to _xtos_set_interrupt_handler_arg(i, func, arg).
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  int i : CPU interrupt number.
+  *
+  * @param  ets_isr_t func : Interrupt handler.
+  *
+  * @param  void *arg : argument of the handler.
+  *
+  * @return None
+  */
+void ets_isr_attach(int i, ets_isr_t func, void *arg);
+
+/**
+  * @brief  Mask the interrupts which show in mask bits.
+  *         This function equals to _xtos_ints_off(mask).
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  uint32_t mask : BIT(i) means mask CPU interrupt number i.
+  *
+  * @return None
+  */
+void ets_isr_mask(uint32_t mask);
+
+/**
+  * @brief  Unmask the interrupts which show in mask bits.
+  *         This function equals to _xtos_ints_on(mask).
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  uint32_t mask : BIT(i) means mask CPU interrupt number i.
+  *
+  * @return None
+  */
+void ets_isr_unmask(uint32_t unmask);
+
+/**
+  * @brief  Lock the interrupt to level 2.
+  *         This function direct set the CPU registers.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_intr_lock(void);
+
+/**
+  * @brief  Unlock the interrupt to level 0.
+  *         This function direct set the CPU registers.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_intr_unlock(void);
+
+
+/**
+  * @brief  Attach an CPU interrupt to a hardware source.
+  *         We have 4 steps to use an interrupt:
+  *         1.Attach hardware interrupt source to CPU.  intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);
+  *         2.Set interrupt handler.                    xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);
+  *         3.Enable interrupt for CPU.                 xt_ints_on(1 << ETS_WMAC_INUM);
+  *         4.Enable interrupt in the module.
+  *
+  * @param  int cpu_no : The CPU which the interrupt number belongs.
+  *
+  * @param  uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table.
+  *
+  * @param  uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table.
+  *
+  * @return None
+  */
+void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
+
+void ets_set_appcpu_boot_addr(uint32_t start);
+
+/**
+  * @}
+  */
+
+#ifndef MAC2STR
+#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
+#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
+#endif
+
+#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
+
+#ifdef ESP_PLATFORM
+// Remove in IDF v6.0 (IDF-7044)
+typedef enum {
+    OK = 0,
+    FAIL,
+    PENDING,
+    BUSY,
+    CANCEL,
+} STATUS __attribute__((deprecated("Use ETS_STATUS instead")));
+#endif
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_ETS_SYS_H_ */

components/esp_rom/esp32h4/include/esp32h4/rom/gpio.h

@@ -0,0 +1,241 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+//TODO: [ESP32H4] IDF-12390 inherit from verification branch, need check
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup gpio_apis, uart configuration and communication related apis
+  * @brief gpio apis
+  */
+
+/** @addtogroup gpio_apis
+  * @{
+  */
+
+#define GPIO_REG_READ(reg)       READ_PERI_REG(reg)
+#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val)
+
+#define GPIO_FUNC_ZERO 0
+#define GPIO_FUNC_GPIO 1
+
+#define GPIO_OUTPUT_SET(gpio_no, bit_value) gpio_set_output_level(gpio_no, bit_value)
+#define GPIO_DIS_OUTPUT(gpio_no)            gpio_output_disable(gpio_no)
+#define GPIO_INPUT_GET(gpio_no)             gpio_get_input_level(gpio_no)
+
+/**
+  * @brief Set GPIO output level
+  *
+  * @param gpio_num GPIO number
+  * @param level Output level, 0:low; 1:high
+  */
+void gpio_set_output_level(uint32_t gpio_num, uint32_t level);
+
+/**
+  * @brief Get GPIO input level
+  *
+  * @param gpio_num GPIO number
+  *
+  * @return 0:the GPIO_input level is low; 1:the GPIO input level is high
+  */
+uint32_t gpio_get_input_level(uint32_t gpio_num);
+
+/**
+  * @brief set gpio input to a signal, one gpio can input to several signals.
+  *
+  * @param uint32_t gpio_num : gpio number
+  *                        gpio == GPIO_NUM_IN_FORCE_0, input 0 to signal
+  *                        gpio == GPIO_NUM_IN_FORCE_1, input 1 to signal
+  *
+  * @param uint32_t signal_idx : signal index.
+  *
+  * @param bool inv : the signal is inv or not
+  *
+  * @return None
+  */
+void gpio_matrix_in(uint32_t gpio_num, uint32_t signal_idx, bool inv);
+
+/**
+ * @brief bypass gpio matrix input to signals
+ * @param signal_idx  Internal signal index
+ */
+void gpio_bypass_matrix_in(uint32_t signal_idx);
+
+/**
+  * @brief set signal output to gpio, one signal can output to several gpios.
+  *
+  * @param uint32_t gpio_num : gpio number
+  *
+  * @param uint32_t signal_idx : signal index.
+  *                        signal_idx == 0x100, cancel output put to the gpio
+  *
+  * @param bool out_inv : the signal output is invert or not
+  *
+  * @param bool oen_inv : the signal output enable is invert or not
+  *
+  * @return None
+  */
+void gpio_matrix_out(uint32_t gpio_num, uint32_t signal_idx, bool out_inv, bool oen_inv);
+
+/**
+  * @brief enable gpio output.
+  *
+  * @param uint32_t gpio_num : gpio number
+  *
+  * @return None
+  */
+void gpio_output_enable(uint32_t gpio_num);
+
+/**
+  * @brief disable gpio output.
+  *
+  * @param uint32_t gpio_num : gpio number
+  *
+  * @return None
+  */
+void gpio_output_disable(uint32_t gpio_num);
+
+/**
+  * @brief Select pad as a gpio function from IOMUX.
+  *
+  * @param uint32_t gpio_num : gpio number
+  *
+  * @return None
+  */
+void gpio_pad_select_gpio(uint32_t gpio_num);
+
+/**
+  * @brief Select a mux for the pad(LP pad) in the IOMUX.
+  * @note This function is only for LP pad and not all chips have LP pad.
+  *
+  * @param gpio_num GPIO number should be LP GPIO
+  * @param mux_sel Select pad as LP GPIO or HP GPIO, 1:LP GPIO,0:HP GPIO
+  */
+void gpio_lppad_select_mux(uint32_t gpio_num, uint32_t mux_sel);
+
+/**
+  * @brief Set pad driver capability.
+  *
+  * @param uint32_t gpio_num : gpio number
+  *
+  * @param uint32_t drv : 0-3
+  *
+  * @return None
+  */
+void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
+
+/**
+  * @brief Set MSPI dedicated pad driver capability.
+  *
+  * @param uint32_t gpio_num : MSPI dedicated gpio number
+  *
+  * @param uint32_t drv : 0-3
+  *
+  * @return None
+  */
+void gpio_ded_pad_set_drv(uint32_t ded_gpio_num, uint32_t drv);
+
+/**
+  * @brief Pull up the pad from gpio number.
+  *
+  * @param uint32_t gpio_num : gpio number
+  *
+  * @return None
+  */
+void gpio_pad_pullup(uint32_t gpio_num);
+
+/**
+  * @brief Pull up the MSPI dedicated pad from gpio number.
+  *
+  * @param uint32_t gpio_num : MSPI dedicated gpio number
+  *
+  * @return None
+  */
+void gpio_ded_pad_pullup(uint32_t ded_gpio_num);
+
+/**
+  * @brief Pull down the pad from gpio number.
+  *
+  * @param uint32_t gpio_num : gpio number
+  *
+  * @return None
+  */
+void gpio_pad_pulldown(uint32_t gpio_num);
+
+/**
+  * @brief Pull down the MSPI dedicated pad from gpio number.
+  *
+  * @param uint32_t gpio_num : MSPI dedicated gpio number
+  *
+  * @return None
+  */
+void gpio_ded_pad_pulldown(uint32_t ded_gpio_num);
+
+/**
+  * @brief enable gpio pad input.
+  *
+  * @param uint32_t gpio_num : gpio number
+  *
+  * @return None
+  */
+void gpio_pad_input_enable(uint32_t gpio_num);
+
+/**
+  * @brief disable gpio pad input.
+  *
+  * @param uint32_t gpio_num : gpio number
+  *
+  * @return None
+  */
+void gpio_pad_input_disable(uint32_t gpio_num);
+
+/**
+  * @brief Unhold the pad from gpio number.
+  *
+  * @param uint32_t gpio_num : gpio number
+  *
+  * @return None
+  */
+void gpio_pad_unhold(uint32_t gpio_num);
+
+/**
+  * @brief Unhold the mspi dedicated pad from gpio number.
+  *
+  * @param uint32_t gpio_num : mspi dedicated gpio number
+  *
+  * @return None
+  */
+void gpio_ded_pad_unhold(uint32_t ded_gpio_num);
+
+/**
+  * @brief Hold the pad from gpio number.
+  *
+  * @param uint32_t gpio_num : gpio number
+  *
+  * @return None
+  */
+void gpio_pad_hold(uint32_t gpio_num);
+
+/**
+  * @brief Hold the mspi dedicated pad from gpio number.
+  *
+  * @param uint32_t gpio_num : mspi dedicated gpio number
+  *
+  * @return None
+  */
+void gpio_ded_pad_hold(uint32_t gpio_num);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif

components/esp_rom/esp32h4/include/esp32h4/rom/hmac.h

@@ -0,0 +1,57 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ROM_HMAC_H_
+#define _ROM_HMAC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: [ESP32H4] IDF-12257 inherit from verification branch, need check
+
+#include <stdint.h>
+#include <stdlib.h>
+#include "efuse.h"
+
+void ets_hmac_enable(void);
+
+void ets_hmac_disable(void);
+
+/* Use the "upstream" HMAC key (ETS_EFUSE_KEY_PURPOSE_HMAC_UP)
+   to digest a message.
+*/
+int ets_hmac_calculate_message(ets_efuse_block_t key_block, const void *message, size_t message_len, uint8_t *hmac);
+
+/* Calculate a downstream HMAC message to temporarily enable JTAG, or
+   to generate a Digital Signature data decryption key.
+
+   - purpose must be ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE
+     or ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG
+
+   - key_block must be in range ETS_EFUSE_BLOCK_KEY0 toETS_EFUSE_BLOCK_KEY6.
+     This efuse block must have the corresponding purpose set in "purpose", or
+     ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL.
+
+   The result of this HMAC calculation is only made available "downstream" to the
+   corresponding hardware module, and cannot be accessed by software.
+*/
+int ets_hmac_calculate_downstream(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose);
+
+/* Invalidate a downstream HMAC value previously calculated by ets_hmac_calculate_downstream().
+ *
+ * - purpose must match a previous call to ets_hmac_calculate_downstream().
+ *
+ * After this function is called, the corresponding internal operation (JTAG or DS) will no longer
+ * have access to the generated key.
+ */
+int ets_hmac_invalidate_downstream(ets_efuse_purpose_t purpose);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _ROM_HMAC_H_

components/esp_rom/esp32h4/include/esp32h4/rom/libc_stubs.h

@@ -0,0 +1,83 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _ROM_LIBC_STUBS_H_
+#define _ROM_LIBC_STUBS_H_
+
+#include <sys/lock.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdarg.h>
+#include <time.h>
+#include <reent.h>
+#include <errno.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ESP32-H4 ROM code contains implementations of some of C library functions.
+Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall
+implementation defined in the following struct.
+
+The table itself, by default, is not allocated in RAM. A global pointer syscall_table_ptr is used to
+set the address
+
+So, before using any of the C library functions (except for pure functions and memcpy/memset functions),
+application must allocate syscall table structure for each CPU being used, and populate it with pointers
+to actual implementations of corresponding syscalls.
+*/
+
+struct syscall_stub_table {
+    struct _reent *(*__getreent)(void);
+    void *(*_malloc_r)(struct _reent *r, size_t);
+    void (*_free_r)(struct _reent *r, void *);
+    void *(*_realloc_r)(struct _reent *r, void *, size_t);
+    void *(*_calloc_r)(struct _reent *r, size_t, size_t);
+    void (*_abort)(void);
+    int (*_system_r)(struct _reent *r, const char *);
+    int (*_rename_r)(struct _reent *r, const char *, const char *);
+    clock_t (*_times_r)(struct _reent *r, struct tms *);
+    int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *);
+    void (*_raise_r)(struct _reent *r);
+    int (*_unlink_r)(struct _reent *r, const char *);
+    int (*_link_r)(struct _reent *r, const char *, const char *);
+    int (*_stat_r)(struct _reent *r, const char *, struct stat *);
+    int (*_fstat_r)(struct _reent *r, int, struct stat *);
+    void *(*_sbrk_r)(struct _reent *r, ptrdiff_t);
+    int (*_getpid_r)(struct _reent *r);
+    int (*_kill_r)(struct _reent *r, int, int);
+    void (*_exit_r)(struct _reent *r, int);
+    int (*_close_r)(struct _reent *r, int);
+    int (*_open_r)(struct _reent *r, const char *, int, int);
+    int (*_write_r)(struct _reent *r, int, const void *, int);
+    int (*_lseek_r)(struct _reent *r, int, int, int);
+    int (*_read_r)(struct _reent *r, int, void *, int);
+    void (*_retarget_lock_init)(_LOCK_T *lock);
+    void (*_retarget_lock_init_recursive)(_LOCK_T *lock);
+    void (*_retarget_lock_close)(_LOCK_T lock);
+    void (*_retarget_lock_close_recursive)(_LOCK_T lock);
+    void (*_retarget_lock_acquire)(_LOCK_T lock);
+    void (*_retarget_lock_acquire_recursive)(_LOCK_T lock);
+    int (*_retarget_lock_try_acquire)(_LOCK_T lock);
+    int (*_retarget_lock_try_acquire_recursive)(_LOCK_T lock);
+    void (*_retarget_lock_release)(_LOCK_T lock);
+    void (*_retarget_lock_release_recursive)(_LOCK_T lock);
+    int (*_printf_float)(struct _reent *data, void *pdata, FILE *fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list *ap);
+    int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap);
+    void (*__assert_func) (const char *file, int line, const char *func, const char *failedexpr) __attribute__((__noreturn__));
+    void (*__sinit) (struct _reent *r);
+    void (*_cleanup_r) (struct _reent *r);
+};
+
+extern struct syscall_stub_table *syscall_table_ptr;
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif /* _ROM_LIBC_STUBS_H_ */

components/esp_rom/esp32h4/include/esp32h4/rom/rom_layout.h

@@ -0,0 +1,104 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: [ESP32H4] IDF-12321 inherit from verification branch, need check
+
+#define SUPPORT_BTDM            0
+#define SUPPORT_BTBB            0
+#define SUPPORT_WIFI            1
+#define SUPPORT_USB_DWCOTG      0
+#define SUPPORT_COEXIST         1
+#define SUPPORT_MBEDTLS         0
+
+/* Structure and functions for returning ROM global layout
+ *
+ * This is for address symbols defined in the linker script, which may change during ECOs.
+ */
+typedef struct {
+    void *dram0_stack_shared_mem_start;
+    void *dram0_rtos_reserved_start;
+    void *stack_sentry;
+    void *stack;
+
+#if SUPPORT_BTDM
+    void *data_start_btdm;
+    void *data_end_btdm;
+    void *bss_start_btdm;
+    void *bss_end_btdm;
+    void *data_start_btdm_rom;
+    void *data_start_interface_btdm;
+    void *data_end_interface_btdm;
+    void *bss_start_interface_btdm;
+    void *bss_end_interface_btdm;
+#endif
+
+#if SUPPORT_BTBB
+    void *dram_start_btbbrom;
+    void *dram_end_btbbrom;
+#endif
+
+#if SUPPORT_BTDM || SUPPORT_WIFI
+    void *dram_start_phyrom;
+    void *dram_end_phyrom;
+#endif
+
+#if SUPPORT_WIFI
+    void *dram_start_net80211;
+    void *dram_end_net80211;
+    void *data_start_interface_net80211;
+    void *data_end_interface_net80211;
+    void *bss_start_interface_net80211;
+    void *bss_end_interface_net80211;
+    void *dram_start_pp;
+    void *dram_end_pp;
+    void *data_start_interface_pp;
+    void *data_end_interface_pp;
+    void *bss_start_interface_pp;
+    void *bss_end_interface_pp;
+#endif
+
+#if SUPPORT_COEXIST
+    void *dram_start_coexist;
+    void *dram_end_coexist;
+    void *data_start_interface_coexist;
+    void *data_end_interface_coexist;
+    void *bss_start_interface_coexist;
+    void *bss_end_interface_coexist;
+#endif
+
+#if SUPPORT_MBEDTLS
+    void *dram_start_mbedtls_rom;
+    void *dram_end_mbedtls_rom;
+#endif
+
+#if SUPPORT_USB_DWCOTG
+    void *dram_start_usb_dwcotg_rom;
+    void *dram_end_usb_dwcotg_rom;
+#else
+    //Two reserved members are defined here, so the structure will not be broken,
+    //please keep in mind that there is no memory can be released between
+    //dram_start_usb_reserved_rom ~ dram_end_usb_reserved_rom.
+    void *dram_start_usb_reserved_rom;
+    void *dram_end_usb_reserved_rom;
+#endif
+
+    void *dram_start_uart_rom;
+    void *dram_end_uart_rom;
+} ets_rom_layout_t;
+
+extern const ets_rom_layout_t *const ets_rom_layout_p;
+
+#ifdef __cplusplus
+}
+#endif

components/esp_rom/esp32h4/include/esp32h4/rom/rtc.h

@@ -0,0 +1,256 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "esp_assert.h"
+
+#include "soc/soc.h"
+#include "soc/lp_aon_reg.h"
+#include "soc/reset_reasons.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: [ESP32H4] IDF-12313 inherit from verification branch, need check
+
+/** \defgroup rtc_apis, rtc registers and memory related apis
+  * @brief rtc apis
+  */
+
+/** @addtogroup rtc_apis
+  * @{
+  */
+
+/**************************************************************************************
+  *                                       Note:                                       *
+  *       Some Rtc memory and registers are used, in ROM or in internal library.      *
+  *          Please do not use reserved or used rtc memory or registers.              *
+  *                                                                                   *
+  *************************************************************************************
+  *                          LP  Memory & Store Register usage
+  *************************************************************************************
+  *     rtc memory addr         type    size            usage
+  *     0x3f421000(0x50000000)  Slow    SIZE_CP         Co-Processor code/Reset Entry
+  *     0x3f421000+SIZE_CP      Slow    8192-SIZE_CP
+  *
+  *     0x3ff80000(0x40070000)  Fast    8192            deep sleep entry code
+  *
+  *************************************************************************************
+  *     RTC store registers     usage
+  *     LP_AON_STORE0_REG       Reserved
+  *     LP_AON_STORE1_REG       RTC_SLOW_CLK calibration value
+  *     LP_AON_STORE2_REG       Boot time, low word
+  *     LP_AON_STORE3_REG       Boot time, high word
+  *     LP_AON_STORE4_REG       External XTAL frequency
+  *     LP_AON_STORE5_REG       FAST_RTC_MEMORY_LENGTH
+  *     LP_AON_STORE6_REG       FAST_RTC_MEMORY_ENTRY
+  *     LP_AON_STORE7_REG       FAST_RTC_MEMORY_CRC
+  *     LP_AON_STORE8_REG       Store light sleep wake stub addr
+  *     LP_AON_STORE9_REG       Store the sleep mode at bit[0]  (0:light sleep 1:deep sleep)
+  *************************************************************************************
+  */
+#define RTC_FIX_US_HIGH_REG                 LP_AON_STORE0_REG
+#define RTC_SLOW_CLK_CAL_REG                LP_AON_STORE1_REG
+#define RTC_BOOT_TIME_LOW_REG               LP_AON_STORE2_REG
+#define RTC_BOOT_TIME_HIGH_REG              LP_AON_STORE3_REG
+#define RTC_XTAL_FREQ_REG                   LP_AON_STORE4_REG
+#define RTC_ENTRY_LENGTH_REG                LP_AON_STORE5_REG
+#define RTC_ENTRY_ADDR_REG                  LP_AON_STORE6_REG
+#define RTC_RESET_CAUSE_REG                 LP_AON_STORE6_REG
+#define RTC_FIX_US_LOW_REG                  LP_AON_STORE7_REG
+#define LIGHT_SLEEP_WAKE_STUB_ADDR_REG      LP_AON_STORE8_REG
+#define SLEEP_MODE_REG                      LP_AON_STORE9_REG
+
+#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
+
+typedef enum {
+    AWAKE = 0,             //<CPU ON
+    LIGHT_SLEEP = BIT0,    //CPU waiti, PLL ON.  We don't need explicitly set this mode.
+    DEEP_SLEEP  = BIT1     //CPU OFF, PLL OFF, only specific timer could wake up
+} SLEEP_MODE;
+
+typedef enum {
+    NO_MEAN                =  0,
+    POWERON_RESET          =  1,    /**<1, Vbat power on reset*/
+    RTC_SW_SYS_RESET       =  3,    /**<3, Software reset digital core (hp system)*/
+    DEEPSLEEP_RESET        =  5,    /**<5, Deep Sleep reset digital core (hp system)*/
+    SDIO_RESET             =  6,    /**<6, Reset by SLC module, reset digital core (hp system)*/
+    TG0WDT_SYS_RESET       =  7,    /**<7, Timer Group0 Watch dog reset digital core (hp system)*/
+    TG1WDT_SYS_RESET       =  8,    /**<8, Timer Group1 Watch dog reset digital core (hp system)*/
+    RTCWDT_SYS_RESET       =  9,    /**<9, RTC Watch dog Reset digital core (hp system)*/
+    TG0WDT_CPU_RESET       = 11,    /**<11, Time Group0 reset CPU*/
+    RTC_SW_CPU_RESET       = 12,    /**<12, Software reset CPU*/
+    RTCWDT_CPU_RESET       = 13,    /**<13, RTC Watch dog Reset CPU*/
+    RTCWDT_BROWN_OUT_RESET = 15,    /**<15, Reset when the vdd voltage is not stable*/
+    RTCWDT_RTC_RESET       = 16,    /**<16, RTC Watch dog reset digital core and rtc module*/
+    TG1WDT_CPU_RESET       = 17,    /**<17, Time Group1 reset CPU*/
+    SUPER_WDT_RESET        = 18,    /**<18, super watchdog reset digital core and rtc module*/
+    EFUSE_RESET            = 20,    /**<20, efuse reset digital core (hp system)*/
+    USB_UART_CHIP_RESET    = 21,    /**<21, usb uart reset digital core (hp system)*/
+    USB_JTAG_CHIP_RESET    = 22,    /**<22, usb jtag reset digital core (hp system)*/
+    JTAG_RESET             = 24,    /**<24, jtag reset CPU*/
+} RESET_REASON;
+
+// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
+ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
+ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
+ESP_STATIC_ASSERT((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
+ESP_STATIC_ASSERT((soc_reset_reason_t)SDIO_RESET == RESET_REASON_CORE_SDIO, "SDIO_RESET != RESET_REASON_CORE_SDIO");
+ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
+ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
+ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
+ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
+ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
+ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
+ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
+ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
+ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
+ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
+ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
+ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
+ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
+ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG");
+
+typedef enum {
+    NO_SLEEP        = 0,
+    EXT_EVENT0_TRIG = BIT0,
+    EXT_EVENT1_TRIG = BIT1,
+    GPIO_TRIG       = BIT2,
+    TIMER_EXPIRE    = BIT3,
+    SDIO_TRIG       = BIT4,
+    MAC_TRIG        = BIT5,
+    UART0_TRIG      = BIT6,
+    UART1_TRIG      = BIT7,
+    TOUCH_TRIG      = BIT8,
+    SAR_TRIG        = BIT9,
+    BT_TRIG         = BIT10,
+    RISCV_TRIG      = BIT11,
+    XTAL_DEAD_TRIG  = BIT12,
+    RISCV_TRAP_TRIG = BIT13,
+    USB_TRIG        = BIT14
+} WAKEUP_REASON;
+
+typedef enum {
+    DISEN_WAKEUP       = NO_SLEEP,
+    EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
+    EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
+    GPIO_TRIG_EN       = GPIO_TRIG,
+    TIMER_EXPIRE_EN    = TIMER_EXPIRE,
+    SDIO_TRIG_EN       = SDIO_TRIG,
+    MAC_TRIG_EN        = MAC_TRIG,
+    UART0_TRIG_EN      = UART0_TRIG,
+    UART1_TRIG_EN      = UART1_TRIG,
+    TOUCH_TRIG_EN      = TOUCH_TRIG,
+    SAR_TRIG_EN        = SAR_TRIG,
+    BT_TRIG_EN         = BT_TRIG,
+    RISCV_TRIG_EN      = RISCV_TRIG,
+    XTAL_DEAD_TRIG_EN  = XTAL_DEAD_TRIG,
+    RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG,
+    USB_TRIG_EN        = USB_TRIG
+} WAKEUP_ENABLE;
+
+/**
+  * @brief  Get the reset reason for CPU.
+  *
+  * @param  int cpu_no : CPU no.
+  *
+  * @return RESET_REASON
+  */
+RESET_REASON rtc_get_reset_reason(int cpu_no);
+
+/**
+  * @brief  Get the wakeup cause for CPU.
+  *
+  * @param  int cpu_no : CPU no.
+  *
+  * @return WAKEUP_REASON
+  */
+WAKEUP_REASON rtc_get_wakeup_cause(void);
+
+typedef void (* esp_rom_wake_func_t)(void);
+
+/**
+  * @brief Read stored RTC wake function address
+  *
+  * Returns pointer to wake address if a value is set in RTC registers, and stored length & CRC all valid.
+  * valid means that both stored stub length and stored wake function address are four-byte aligned non-zero values
+  * and the crc check passes
+  *
+  * @param  None
+  *
+  * @return esp_rom_wake_func_t : Returns pointer to wake address if a value is set in RTC registers
+  */
+esp_rom_wake_func_t esp_rom_get_rtc_wake_addr(void);
+
+/**
+  * @brief Store new RTC wake function address
+  *
+  * Set a new RTC wake address function. If a non-NULL function pointer is set then the function
+  * memory is calculated and stored also.
+  *
+  * @param entry_addr Address of function. should be 4-bytes aligned otherwise it will not start from the stub after wake from deepsleep，
+  *                   if NULL length will be ignored and all registers are cleared to 0.
+  *
+  * @param length length of function in RTC fast memory. should be less than RTC Fast memory size and aligned to 4-bytes.
+  *               otherwise all registers are cleared to 0.
+  *
+  * @return None
+  */
+void esp_rom_set_rtc_wake_addr(esp_rom_wake_func_t entry_addr, size_t length);
+
+/**
+  * @brief Suppress ROM log by setting specific RTC control register.
+  * @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+static inline void rtc_suppress_rom_log(void)
+{
+    /* To disable logging in the ROM, only the least significant bit of the register is used,
+     * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
+     * you need to write to this register in the same format.
+     * Namely, the upper 16 bits and lower should be the same.
+     */
+    REG_SET_BIT(LP_AON_STORE4_REG, RTC_DISABLE_ROM_LOG);
+}
+
+/**
+  * @brief Software Reset digital core.
+  *
+  * It is not recommended to use this function in esp-idf, use
+  * esp_restart() instead.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void software_reset(void);
+
+/**
+  * @brief Software Reset digital core.
+  *
+  * It is not recommended to use this function in esp-idf, use
+  * esp_restart() instead.
+  *
+  * @param  int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
+  *
+  * @return None
+  */
+void software_reset_cpu(int cpu_no);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif

components/esp_rom/esp32h4/include/esp32h4/rom/secure_boot.h

@@ -0,0 +1,135 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "ets_sys.h"
+#include "ecdsa.h"
+#include "rsa_pss.h"
+#include "esp_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: [ESP32H4] IDF-12262 inherit from verification branch, need check
+
+#if CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT
+
+typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t;
+typedef struct ets_secure_boot_signature ets_secure_boot_signature_t;
+typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t;
+
+/* Anti-FI measure: use full words for success/fail, instead of
+   0/non-zero
+*/
+typedef enum {
+    SB_SUCCESS = 0x3A5A5AA5,
+    SB_FAILED = 0x7533885E,
+} ets_secure_boot_status_t;
+
+/* Verify bootloader image (reconfigures cache to map),
+   with key digests provided as parameters.)
+
+   Can be used to verify secure boot status before enabling
+   secure boot permanently.
+
+   If stage_load parameter is true, bootloader is copied into staging
+   buffer in RAM at the same time.
+
+   If result is SB_SUCCESS, the "simple hash" of the bootloader is
+   copied into verified_hash.
+*/
+ets_secure_boot_status_t ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys, bool stage_load);
+
+/* Read key digests from efuse. Any revoked/missing digests will be
+   marked as NULL
+*/
+ETS_STATUS ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys);
+
+/* Verify supplied signature against supplied digest, using
+   supplied trusted key digests.
+
+   Doesn't reconfigure cache or any other hardware access except for RSA peripheral.
+
+   If result is SB_SUCCESS, the image_digest value is copied into verified_digest.
+*/
+ets_secure_boot_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys, uint8_t *verified_digest);
+
+/* Revoke a public key digest in efuse.
+   @param index Digest to revoke. Must be 0, 1 or 2.
+ */
+void ets_secure_boot_revoke_public_key_digest(int index);
+
+#define CRC_SIGN_BLOCK_LEN 1196
+#define SIG_BLOCK_PADDING 4096
+#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7
+
+/* Secure Boot V2 signature block
+
+   (Up to 3 in a signature sector are appended to the image)
+ */
+#if CONFIG_SECURE_SIGNED_APPS_RSA_SCHEME
+
+struct ets_secure_boot_sig_block {
+    uint8_t magic_byte;
+    uint8_t version;
+    uint8_t _reserved1;
+    uint8_t _reserved2;
+    uint8_t image_digest[32];
+    ets_rsa_pubkey_t key;
+    uint8_t signature[384];
+    uint32_t block_crc;
+    uint8_t _padding[16];
+};
+
+#elif CONFIG_SECURE_SIGNED_APPS_ECDSA_V2_SCHEME
+
+struct __attribute((packed)) ets_secure_boot_sig_block {
+    uint8_t magic_byte;
+    uint8_t version;
+    uint8_t _reserved1;
+    uint8_t _reserved2;
+    uint8_t image_digest[32];
+    struct {
+        struct {
+            uint8_t curve_id; /* ETS_ECDSA_CURVE_P192 / ETS_ECDSA_CURVE_P256 */
+            uint8_t point[64]; /* X followed by Y (both little-endian), plus zero bytes if P192 */
+        } key;
+        uint8_t signature[64]; /* r followed by s (both little-endian) */
+        uint8_t padding[1031];
+    } ecdsa;
+    uint32_t block_crc; /* note: crc covers all bytes in the structure before it, regardless of version field */
+    uint8_t _padding[16];
+};
+#endif
+
+ESP_STATIC_ASSERT(sizeof(ets_secure_boot_sig_block_t) == 1216, "invalid sig block size");
+
+#define SECURE_BOOT_NUM_BLOCKS 3
+
+/* V2 Secure boot signature sector (up to 3 blocks) */
+struct ets_secure_boot_signature {
+    ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS];
+    uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)];
+};
+
+ESP_STATIC_ASSERT(sizeof(ets_secure_boot_signature_t) == 4096, "invalid sig sector size");
+
+#define MAX_KEY_DIGESTS 3
+
+struct ets_secure_boot_key_digests {
+    const void *key_digests[MAX_KEY_DIGESTS];
+    bool allow_key_revoke;
+};
+
+#endif /* CONFIG_SECURE_BOOT_V2_ENABLED || CONFIG_SECURE_SIGNED_APPS_NO_SECURE_BOOT */
+
+#ifdef __cplusplus
+}
+#endif

components/esp_rom/esp32h4/include/esp32h4/rom/sha.h

@@ -0,0 +1,60 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _ROM_SHA_H_
+#define _ROM_SHA_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "ets_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: [ESP32H4] IDF-12263 inherit from verification branch, need check
+
+typedef enum {
+    SHA1 = 0,
+    SHA2_224,
+    SHA2_256,
+    SHA2_384,
+    SHA2_512,
+    SHA2_512224,
+    SHA2_512256,
+    SHA2_512T,
+    SHA_TYPE_MAX
+} SHA_TYPE;
+
+typedef struct SHAContext {
+    bool start;
+    bool in_hardware;               // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved
+    SHA_TYPE type;
+    uint32_t state[16];             // For SHA1/SHA224/SHA256, used 8, other used 16
+    unsigned char buffer[128];      // For SHA1/SHA224/SHA256, used 64, other used 128
+    uint32_t total_bits[4];
+} SHA_CTX;
+
+void ets_sha_enable(void);
+
+void ets_sha_disable(void);
+
+ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type);
+
+ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t);
+
+void ets_sha_get_state(SHA_CTX *ctx);
+
+void ets_sha_process(SHA_CTX *ctx, const unsigned char *input);
+
+void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx);
+
+ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_SHA_H_ */

components/esp_rom/esp32h4/include/esp32h4/rom/spi_flash.h

@@ -0,0 +1,460 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "esp_attr.h"
+#include "esp_rom_spiflash.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: [ESP32H4] IDF-12388 inherit from verification branch, need check
+
+#define PERIPHS_SPI_FLASH_CMD                 SPI_MEM_CMD_REG(1)
+#define PERIPHS_SPI_FLASH_ADDR                SPI_MEM_ADDR_REG(1)
+#define PERIPHS_SPI_FLASH_CTRL                SPI_MEM_CTRL_REG(1)
+#define PERIPHS_SPI_FLASH_CTRL1               SPI_MEM_CTRL1_REG(1)
+#define PERIPHS_SPI_FLASH_STATUS              SPI_MEM_RD_STATUS_REG(1)
+#define PERIPHS_SPI_FLASH_USRREG              SPI_MEM_USER_REG(1)
+#define PERIPHS_SPI_FLASH_USRREG1             SPI_MEM_USER1_REG(1)
+#define PERIPHS_SPI_FLASH_USRREG2             SPI_MEM_USER2_REG(1)
+#define PERIPHS_SPI_FLASH_C0                  SPI_MEM_W0_REG(1)
+#define PERIPHS_SPI_FLASH_C1                  SPI_MEM_W1_REG(1)
+#define PERIPHS_SPI_FLASH_C2                  SPI_MEM_W2_REG(1)
+#define PERIPHS_SPI_FLASH_C3                  SPI_MEM_W3_REG(1)
+#define PERIPHS_SPI_FLASH_C4                  SPI_MEM_W4_REG(1)
+#define PERIPHS_SPI_FLASH_C5                  SPI_MEM_W5_REG(1)
+#define PERIPHS_SPI_FLASH_C6                  SPI_MEM_W6_REG(1)
+#define PERIPHS_SPI_FLASH_C7                  SPI_MEM_W7_REG(1)
+#define PERIPHS_SPI_FLASH_TX_CRC              SPI_MEM_TX_CRC_REG(1)
+
+#define SPI0_R_QIO_DUMMY_CYCLELEN             5
+#define SPI0_R_QIO_ADDR_BITSLEN               23
+#define SPI0_R_FAST_DUMMY_CYCLELEN            7
+#define SPI0_R_DIO_DUMMY_CYCLELEN             3
+#define SPI0_R_FAST_ADDR_BITSLEN              23
+#define SPI0_R_SIO_ADDR_BITSLEN               23
+
+#define SPI1_R_QIO_DUMMY_CYCLELEN             5
+#define SPI1_R_QIO_ADDR_BITSLEN               23
+#define SPI1_R_FAST_DUMMY_CYCLELEN            7
+#define SPI1_R_DIO_DUMMY_CYCLELEN             3
+#define SPI1_R_DIO_ADDR_BITSLEN               23
+#define SPI1_R_FAST_ADDR_BITSLEN              23
+#define SPI1_R_SIO_ADDR_BITSLEN               23
+
+#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN   23
+
+#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN   SPI_MEM_WRSR_2B
+
+//SPI address register
+#define ESP_ROM_SPIFLASH_BYTES_LEN            24
+#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM  32
+#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM   16
+#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS  0xf
+
+typedef void (* spi_flash_func_t)(void);
+typedef esp_rom_spiflash_result_t (* spi_flash_op_t)(void);
+typedef esp_rom_spiflash_result_t (* spi_flash_erase_t)(uint32_t);
+typedef esp_rom_spiflash_result_t (* spi_flash_rd_t)(uint32_t, uint32_t*, int);
+typedef esp_rom_spiflash_result_t (* spi_flash_wr_t)(uint32_t, const uint32_t*, int);
+typedef esp_rom_spiflash_result_t (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
+typedef esp_rom_spiflash_result_t (* spi_flash_wren_t)(void*);
+typedef esp_rom_spiflash_result_t (* spi_flash_erase_area_t)(uint32_t, uint32_t);
+
+typedef struct {
+    uint8_t pp_addr_bit_len;
+    uint8_t se_addr_bit_len;
+    uint8_t be_addr_bit_len;
+    uint8_t rd_addr_bit_len;
+    uint32_t read_sub_len;
+    uint32_t write_sub_len;
+    spi_flash_op_t unlock;
+    spi_flash_erase_t erase_sector;
+    spi_flash_erase_t erase_block;
+    spi_flash_rd_t read;
+    spi_flash_wr_t write;
+    spi_flash_ewr_t encrypt_write;
+    spi_flash_func_t check_sus;
+    spi_flash_wren_t wren;
+    spi_flash_op_t wait_idle;
+    spi_flash_erase_area_t erase_area;
+} spiflash_legacy_funcs_t;
+
+typedef struct {
+    uint8_t  data_length;
+    uint8_t  read_cmd0;
+    uint8_t  read_cmd1;
+    uint8_t  write_cmd;
+    uint16_t data_mask;
+    uint16_t data;
+} esp_rom_spiflash_common_cmd_t;
+
+/**
+  * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR).
+  *    Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
+  *
+  * @param  uint32_t *status : The pointer to which to return the Flash status value.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : read error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status);
+
+/**
+  * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2).
+  *        Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
+  *
+  * @param  uint32_t *status : The pointer to which to return the Flash status value.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : read error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
+
+/**
+  * @brief Write status to Flash status register.
+  *        Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
+  *
+  * @param  uint32_t status_value : Value to .
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : write error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value);
+
+/**
+  * @brief Use a command to Read Flash status register.
+  *        Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
+  *
+  * @param  uint32_t*status : The pointer to which to return the Flash status value.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : read error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd);
+
+/**
+  * @brief Config SPI Flash read mode when init.
+  *        Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
+  *
+  * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : config error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode);
+
+/**
+  * @brief Config SPI Flash clock divisor.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t freqdiv: clock divisor.
+  *
+  * @param  uint8_t spi: 0 for SPI0, 1 for SPI1.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : config error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
+
+/**
+  * @brief Clear all SR bits except QE bit.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_clear_bp(void);
+
+/**
+  * @brief Clear all SR bits except QE bit.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
+
+/**
+  * @brief Update SPI Flash parameter.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t deviceId : Device ID read from SPI, the low 32 bit.
+  *
+  * @param  uint32_t chip_size : The Flash size.
+  *
+  * @param  uint32_t block_size : The Flash block size.
+  *
+  * @param  uint32_t sector_size : The Flash sector size.
+  *
+  * @param  uint32_t page_size : The Flash page size.
+  *
+  * @param  uint32_t status_mask : The Mask used when read status from Flash(use single CMD).
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Update error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size,
+                                                        uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
+
+/**
+  * @brief Erase whole flash chip.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void);
+
+/**
+  * @brief Erase a 64KB block of flash
+  *        Uses SPI flash command D8H.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t block_num : Which block to erase.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num);
+
+/**
+  * @brief Erase a sector of flash.
+  *        Uses SPI flash command 20H.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t sector_num : Which sector to erase.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num);
+
+/**
+  * @brief Erase some sectors.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t start_addr : Start addr to erase, should be sector aligned.
+  *
+  * @param  uint32_t area_len : Length to erase, should be sector aligned.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len);
+
+/**
+  * @brief Write Data to Flash, you should Erase it yourself if need.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t dest_addr : Address to write, should be 4 bytes aligned.
+  *
+  * @param  const uint32_t *src : The pointer to data which is to write.
+  *
+  * @param  uint32_t len : Length to write, should be 4 bytes aligned.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Write error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len);
+
+/**
+  * @brief Read Data from Flash, you should Erase it yourself if need.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t src_addr : Address to read, should be 4 bytes aligned.
+  *
+  * @param  uint32_t *dest : The buf to read the data.
+  *
+  * @param  uint32_t len : Length to read, should be 4 bytes aligned.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Read error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len);
+
+/**
+  * @brief SPI1 go into encrypto mode.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void esp_rom_spiflash_write_encrypted_enable(void);
+
+/**
+  * @brief SPI1 go out of encrypto mode.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void esp_rom_spiflash_write_encrypted_disable(void);
+
+/**
+  * @brief Write data to flash with transparent encryption.
+  * @note Sectors to be written should already be erased.
+  *
+  * @note Please do not call this function in SDK.
+  *
+  * @param  uint32_t flash_addr : Address to write, should be 32 byte aligned.
+  *
+  * @param  uint32_t *data : The pointer to data to write. Note, this pointer must
+  *                          be 32 bit aligned and the content of the data will be
+  *                          modified by the encryption function.
+  *
+  * @param  uint32_t len : Length to write, should be 32 bytes aligned.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
+
+
+/** @brief Wait until SPI flash write operation is complete
+ *
+ * @note Please do not call this function in SDK.
+ *
+ * Reads the Write In Progress bit of the SPI flash status register,
+ * repeats until this bit is zero (indicating write complete).
+ *
+ * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete
+ *         ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status.
+ */
+esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi);
+
+
+/** @brief Enable Quad I/O pin functions
+ *
+ * @note Please do not call this function in SDK.
+ *
+ * Sets the HD & WP pin functions for Quad I/O modes, based on the
+ * efuse SPI pin configuration.
+ *
+ * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O.
+ *
+ * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig().
+ * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored.
+ * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored.
+ * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used
+ *   to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI).
+ *   Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral.
+ */
+void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
+
+/**
+ * @brief Clear WEL bit unconditionally.
+ *
+ * @return always ESP_ROM_SPIFLASH_RESULT_OK
+ */
+esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void);
+
+/**
+ * @brief Set WREN bit.
+ *
+ * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
+ *
+ * @return always ESP_ROM_SPIFLASH_RESULT_OK
+ */
+esp_rom_spiflash_result_t esp_rom_spiflash_write_enable(esp_rom_spiflash_chip_t *spi);
+
+/**
+  * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
+  *    Please do not call this function in SDK.
+  *
+  * @param  uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
+  *
+  * @param  uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
+  *
+  * @return None
+  */
+void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
+
+/**
+  * @brief Set SPI Flash pad drivers.
+  *    Please do not call this function in SDK.
+  *
+  * @param  uint8_t wp_gpio_num: WP gpio number.
+  *
+  * @param  uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
+  *              else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
+  *
+  * @param  uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
+  *            drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
+  *                        Values usually read from flash by rom code, function usually callde by rom code.
+  *                        if value with bit(3) set, the value is valid, bit[2:0] is the real value.
+  *
+  * @return None
+  */
+void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
+
+/**
+  * @brief Select SPI Flash function for pads.
+  *    Please do not call this function in SDK.
+  *
+  * @param  uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
+  *              else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
+  *
+  * @return None
+  */
+void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
+
+/**
+  * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
+  *        Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
+  *
+  * @return uint16_t  0 : do not send command any more.
+  *                   1 : go to the next command.
+  *                   n > 1 : skip (n - 1) commands.
+  */
+uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
+
+extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
+
+#ifdef __cplusplus
+}
+#endif

components/esp_rom/esp32h4/include/esp32h4/rom/uart.h

@@ -0,0 +1,355 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ROM_UART_H_
+#define _ROM_UART_H_
+
+#include "esp_types.h"
+#include "esp_attr.h"
+#include "ets_sys.h"
+#include "soc/soc.h"
+#include "soc/uart_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//TODO: [ESP32H4] IDF-12398 inherit from verification branch, need check
+
+/** \defgroup uart_apis, uart configuration and communication related apis
+  * @brief uart apis
+  */
+
+/** @addtogroup uart_apis
+  * @{
+  */
+
+#define RX_BUFF_SIZE                     0x400
+#define TX_BUFF_SIZE                     100
+
+//uart int enable register ctrl bits
+#define UART_RCV_INTEN                   BIT0
+#define UART_TRX_INTEN                   BIT1
+#define UART_LINE_STATUS_INTEN           BIT2
+
+//uart int identification ctrl bits
+#define UART_INT_FLAG_MASK               0x0E
+
+//uart fifo ctrl bits
+#define UART_CLR_RCV_FIFO                BIT1
+#define UART_CLR_TRX_FIFO                BIT2
+#define UART_RCVFIFO_TRG_LVL_BITS        BIT6
+
+//uart line control bits
+#define  UART_DIV_LATCH_ACCESS_BIT       BIT7
+
+//uart line status bits
+#define  UART_RCV_DATA_RDY_FLAG          BIT0
+#define  UART_RCV_OVER_FLOW_FLAG         BIT1
+#define  UART_RCV_PARITY_ERR_FLAG        BIT2
+#define  UART_RCV_FRAME_ERR_FLAG         BIT3
+#define  UART_BRK_INT_FLAG               BIT4
+#define  UART_TRX_FIFO_EMPTY_FLAG        BIT5
+#define  UART_TRX_ALL_EMPTY_FLAG         BIT6   // include fifo and shift reg
+#define  UART_RCV_ERR_FLAG               BIT7
+
+//send and receive message frame head
+#define FRAME_FLAG                       0x7E
+
+typedef enum {
+    UART_LINE_STATUS_INT_FLAG  = 0x06,
+    UART_RCV_FIFO_INT_FLAG     = 0x04,
+    UART_RCV_TMOUT_INT_FLAG    = 0x0C,
+    UART_TXBUFF_EMPTY_INT_FLAG = 0x02
+} UartIntType;   //consider bit0 for int_flag
+
+typedef enum {
+    RCV_ONE_BYTE      = 0x0,
+    RCV_FOUR_BYTE     = 0x1,
+    RCV_EIGHT_BYTE    = 0x2,
+    RCV_FOURTEEN_BYTE = 0x3
+} UartRcvFifoTrgLvl;
+
+typedef enum {
+    FIVE_BITS  = 0x0,
+    SIX_BITS   = 0x1,
+    SEVEN_BITS = 0x2,
+    EIGHT_BITS = 0x3
+} UartBitsNum4Char;
+
+typedef enum {
+    ONE_STOP_BIT      = 1,
+    ONE_HALF_STOP_BIT = 2,
+    TWO_STOP_BIT      = 3
+} UartStopBitsNum;
+
+typedef enum {
+    NONE_BITS = 0,
+    ODD_BITS  = 2,
+    EVEN_BITS = 3
+
+} UartParityMode;
+
+typedef enum {
+    STICK_PARITY_DIS = 0,
+    STICK_PARITY_EN  = 2
+} UartExistParity;
+
+typedef enum {
+    BIT_RATE_9600   = 9600,
+    BIT_RATE_19200  = 19200,
+    BIT_RATE_38400  = 38400,
+    BIT_RATE_57600  = 57600,
+    BIT_RATE_115200 = 115200,
+    BIT_RATE_230400 = 230400,
+    BIT_RATE_460800 = 460800,
+    BIT_RATE_921600 = 921600
+} UartBautRate;
+
+typedef enum {
+    NONE_CTRL,
+    HARDWARE_CTRL,
+    XON_XOFF_CTRL
+} UartFlowCtrl;
+
+typedef enum {
+    EMPTY,
+    UNDER_WRITE,
+    WRITE_OVER
+} RcvMsgBuffState;
+
+typedef struct {
+    uint8_t *pRcvMsgBuff;
+    uint8_t *pWritePos;
+    uint8_t *pReadPos;
+    uint8_t  TrigLvl;
+    RcvMsgBuffState BuffState;
+} RcvMsgBuff;
+
+typedef struct {
+    uint32_t  TrxBuffSize;
+    uint8_t  *pTrxBuff;
+} TrxMsgBuff;
+
+typedef enum {
+    BAUD_RATE_DET,
+    WAIT_SYNC_FRM,
+    SRCH_MSG_HEAD,
+    RCV_MSG_BODY,
+    RCV_ESC_CHAR,
+} RcvMsgState;
+
+typedef struct {
+    UartBautRate     baut_rate;
+    UartBitsNum4Char data_bits;
+    UartExistParity  exist_parity;
+    UartParityMode   parity;    // chip size in byte
+    UartStopBitsNum  stop_bits;
+    UartFlowCtrl     flow_ctrl;
+    uint8_t          buff_uart_no;  //indicate which uart use tx/rx buffer
+    RcvMsgBuff       rcv_buff;
+//    TrxMsgBuff       trx_buff;
+    RcvMsgState      rcv_state;
+    int              received;
+} UartDevice;
+
+/**
+  * @brief Init uart device struct value and reset uart0/uart1 rx.
+  *        Please do not call this function in SDK.
+  *
+  * @param  rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL
+  *
+  * @return None
+  */
+void uartAttach(void *rxBuffer);
+
+/**
+  * @brief Init uart0 or uart1 for UART download booting mode.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, else for UART1.
+  *
+  * @param  uint32_t clock : clock used by uart module, to adjust baudrate.
+  *
+  * @return None
+  */
+void Uart_Init(uint8_t uart_no, uint32_t clock);
+
+/**
+  * @brief Modify uart baudrate.
+  *        This function will reset RX/TX fifo for uart.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
+  *
+  * @param  uint32_t DivLatchValue : (clock << 4)/baudrate.
+  *
+  * @return None
+  */
+void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue);
+
+/**
+  * @brief Switch printf channel of uart_tx_one_char.
+  *        Please do not call this function when printf.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
+  *
+  * @return None
+  */
+void uart_tx_switch(uint8_t uart_no);
+
+/**
+  * @brief Output a char to printf channel, wait until fifo not full.
+  *
+  * @param  None
+  *
+  * @return OK.
+  */
+ETS_STATUS uart_tx_one_char(uint8_t TxChar);
+
+/**
+  * @brief Output a char to message exchange channel, wait until fifo not full.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return OK.
+  */
+ETS_STATUS uart_tx_one_char2(uint8_t TxChar);
+
+/**
+  * @brief Wait until uart tx full empty.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
+  *
+  * @return None.
+  */
+void uart_tx_flush(uint8_t uart_no);
+
+/**
+  * @brief Wait until uart tx full empty and the last char send ok.
+  *
+  * @param  uart_no : 0 for UART0, 1 for UART1
+  *
+  * The function defined in ROM code has a bug, so we define the correct version
+  * here for compatibility.
+  */
+void uart_tx_wait_idle(uint8_t uart_no);
+
+/**
+  * @brief Get an input char from message channel.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *pRxChar : the pointer to store the char.
+  *
+  * @return OK for successful.
+  *         FAIL for failed.
+  */
+ETS_STATUS uart_rx_one_char(uint8_t *pRxChar);
+
+/**
+  * @brief Get an input char from message channel, wait until successful.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return char : input char value.
+  */
+char uart_rx_one_char_block(void);
+
+/**
+  * @brief Get an input string line from message channel.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *pString : the pointer to store the string.
+  *
+  * @param  uint8_t MaxStrlen : the max string length, include '\0'.
+  *
+  * @return OK.
+  */
+ETS_STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen);
+
+/**
+  * @brief Process uart received information in the interrupt handler.
+  *        Please do not call this function in SDK.
+  *
+  * @param  void *para : the message receive buffer.
+  *
+  * @return None
+  */
+void uart_rx_intr_handler(void *para);
+
+/**
+  * @brief Get an char from receive buffer.
+  *        Please do not call this function in SDK.
+  *
+  * @param  RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer.
+  *
+  * @param  uint8_t *pRxByte : the pointer to store the char.
+  *
+  * @return OK for successful.
+  *         FAIL for failed.
+  */
+ETS_STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte);
+
+/**
+  * @brief Get all chars from receive buffer.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *pCmdLn : the pointer to store the string.
+  *
+  * @return OK for successful.
+  *         FAIL for failed.
+  */
+ETS_STATUS UartGetCmdLn(uint8_t *pCmdLn);
+
+/**
+  * @brief Get uart configuration struct.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return UartDevice * : uart configuration struct pointer.
+  */
+UartDevice *GetUartDevice(void);
+
+/**
+  * @brief Send an packet to download tool, with SLIP escaping.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *p : the pointer to output string.
+  *
+  * @param  int len : the string length.
+  *
+  * @return None.
+  */
+void send_packet(uint8_t *p, int len);
+
+/**
+  * @brief Receive an packet from download tool, with SLIP escaping.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *p : the pointer to input string.
+  *
+  * @param  int len : If string length > len, the string will be truncated.
+  *
+  * @param  uint8_t is_sync : 0, only one UART module;
+  *                           1, two UART modules.
+  *
+  * @return int : the length of the string.
+  */
+int recv_packet(uint8_t *p, int len, uint8_t is_sync);
+
+extern UartDevice UartDev;
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_UART_H_ */

components/esp_rom/esp32h4/ld/esp32h4.rom.api.ld

@@ -0,0 +1,65 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/** ROM APIs
+ */
+
+PROVIDE ( esp_rom_crc32_le = crc32_le );
+PROVIDE ( esp_rom_crc16_le = crc16_le );
+PROVIDE ( esp_rom_crc8_le  = crc8_le );
+PROVIDE ( esp_rom_crc32_be = crc32_be );
+PROVIDE ( esp_rom_crc16_be = crc16_be );
+PROVIDE ( esp_rom_crc8_be  = crc8_be );
+
+PROVIDE ( esp_rom_gpio_pad_select_gpio    = gpio_pad_select_gpio );
+PROVIDE ( esp_rom_gpio_pad_pullup_only    = gpio_pad_pullup );
+PROVIDE ( esp_rom_gpio_pad_set_drv        = gpio_pad_set_drv );
+PROVIDE ( esp_rom_gpio_pad_unhold         = gpio_pad_unhold );
+PROVIDE ( esp_rom_gpio_connect_in_signal  = gpio_matrix_in );
+PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
+
+PROVIDE ( esp_rom_efuse_mac_address_crc8       = esp_crc8 );
+PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
+
+PROVIDE ( esp_rom_uart_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_uart_tx_one_char    = uart_tx_one_char2 );
+PROVIDE ( esp_rom_uart_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_uart_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_uart_rx_string      = UartRxString );
+PROVIDE ( esp_rom_uart_set_as_console = uart_tx_switch );
+PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
+
+PROVIDE ( esp_rom_output_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_output_tx_one_char    = uart_tx_one_char );
+PROVIDE ( esp_rom_output_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_output_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_output_rx_string      = UartRxString );
+PROVIDE ( esp_rom_output_set_as_console = uart_tx_switch );
+PROVIDE ( esp_rom_output_putc           = ets_write_char_uart );
+
+PROVIDE ( esp_rom_md5_init   = MD5Init );
+PROVIDE ( esp_rom_md5_update = MD5Update );
+PROVIDE ( esp_rom_md5_final  = MD5Final );
+
+PROVIDE ( esp_rom_software_reset_system = software_reset );
+PROVIDE ( esp_rom_software_reset_cpu    = software_reset_cpu );
+
+PROVIDE ( esp_rom_printf   = ets_printf );
+PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf );
+PROVIDE ( esp_rom_delay_us = ets_delay_us );
+PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
+PROVIDE ( esp_rom_route_intr_matrix = intr_matrix_set );
+PROVIDE ( esp_rom_get_cpu_ticks_per_us = ets_get_cpu_frequency );
+PROVIDE ( esp_rom_set_cpu_ticks_per_us = ets_update_cpu_frequency );
+
+PROVIDE ( esp_rom_spiflash_attach = spi_flash_attach );
+PROVIDE ( esp_rom_spiflash_clear_bp = esp_rom_spiflash_unlock );
+PROVIDE ( esp_rom_spiflash_write_enable = SPI_write_enable );
+PROVIDE ( esp_rom_spiflash_erase_area = SPIEraseArea );
+
+PROVIDE ( esp_rom_spiflash_fix_dummylen = spi_dummy_len_fix );
+PROVIDE ( esp_rom_spiflash_set_drvs = SetSpiDrvs);
+PROVIDE ( esp_rom_spiflash_select_padsfunc = SelectSpiFunction );
+PROVIDE ( esp_rom_spiflash_common_cmd = SPI_Common_Command );

components/esp_rom/esp32h4/ld/esp32h4.rom.heap.ld

@@ -0,0 +1,79 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32h4.rom.heap.ld for esp32h4
+ *
+ *
+ * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group heap
+ ***************************************/
+
+/* Functions */
+tlsf_create = 0x400003d8;
+tlsf_create_with_pool = 0x400003dc;
+tlsf_get_pool = 0x400003e0;
+tlsf_add_pool = 0x400003e4;
+tlsf_remove_pool = 0x400003e8;
+tlsf_malloc = 0x400003ec;
+tlsf_memalign = 0x400003f0;
+tlsf_memalign_offs = 0x400003f4;
+tlsf_malloc_addr = 0x400003f8;
+tlsf_realloc = 0x400003fc;
+tlsf_free = 0x40000400;
+tlsf_block_size = 0x40000404;
+tlsf_size = 0x40000408;
+tlsf_pool_overhead = 0x4000040c;
+tlsf_alloc_overhead = 0x40000410;
+tlsf_walk_pool = 0x40000414;
+tlsf_check = 0x40000418;
+tlsf_check_pool = 0x4000041c;
+tlsf_poison_fill_pfunc_set = 0x40000420;
+tlsf_poison_check_pfunc_set = 0x40000424;
+multi_heap_get_block_address_impl = 0x40000428;
+multi_heap_get_allocated_size_impl = 0x4000042c;
+multi_heap_register_impl = 0x40000430;
+multi_heap_set_lock = 0x40000434;
+multi_heap_os_funcs_init = 0x40000438;
+multi_heap_internal_lock = 0x4000043c;
+multi_heap_internal_unlock = 0x40000440;
+multi_heap_get_first_block = 0x40000444;
+multi_heap_get_next_block = 0x40000448;
+multi_heap_is_free = 0x4000044c;
+multi_heap_malloc_impl = 0x40000450;
+multi_heap_free_impl = 0x40000454;
+multi_heap_realloc_impl = 0x40000458;
+multi_heap_aligned_alloc_impl_offs = 0x4000045c;
+multi_heap_aligned_alloc_impl = 0x40000460;
+multi_heap_check = 0x40000464;
+multi_heap_dump = 0x40000468;
+multi_heap_free_size_impl = 0x4000046c;
+multi_heap_minimum_free_size_impl = 0x40000470;
+multi_heap_get_info_impl = 0x40000474;
+/* Data (.data, .bss, .rodata) */
+heap_tlsf_table_ptr = 0x4085ffd4;
+
+PROVIDE (multi_heap_malloc = multi_heap_malloc_impl);
+PROVIDE (multi_heap_free = multi_heap_free_impl);
+PROVIDE (multi_heap_realloc = multi_heap_realloc_impl);
+PROVIDE (multi_heap_get_allocated_size = multi_heap_get_allocated_size_impl);
+PROVIDE (multi_heap_register = multi_heap_register_impl);
+PROVIDE (multi_heap_get_info = multi_heap_get_info_impl);
+PROVIDE (multi_heap_free_size = multi_heap_free_size_impl);
+PROVIDE (multi_heap_minimum_free_size = multi_heap_minimum_free_size_impl);
+PROVIDE (multi_heap_get_block_address = multi_heap_get_block_address_impl);
+PROVIDE (multi_heap_aligned_alloc = multi_heap_aligned_alloc_impl);
+PROVIDE (multi_heap_aligned_free = multi_heap_aligned_free_impl);
+PROVIDE (multi_heap_check = multi_heap_check);
+PROVIDE (multi_heap_set_lock = multi_heap_set_lock);
+PROVIDE (multi_heap_os_funcs_init = multi_heap_mutex_init);
+PROVIDE (multi_heap_internal_lock = multi_heap_internal_lock);
+PROVIDE (multi_heap_internal_unlock = multi_heap_internal_unlock);

components/esp_rom/esp32h4/ld/esp32h4.rom.ld

@@ -0,0 +1,404 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32h4.rom.ld for esp32h4
+ *
+ *
+ * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group common
+ ***************************************/
+
+/* Functions */
+rtc_get_reset_reason = 0x40000018;
+rtc_get_wakeup_cause = 0x4000001c;
+pmu_enable_unhold_pads = 0x40000020;
+ets_printf = 0x40000024;
+ets_install_putc1 = 0x40000028;
+ets_install_putc2 = 0x4000002c;
+ets_install_uart_printf = 0x40000030;
+ets_install_usb_printf = 0x40000034;
+ets_get_printf_channel = 0x40000038;
+ets_delay_us = 0x4000003c;
+ets_get_cpu_frequency = 0x40000040;
+ets_update_cpu_frequency = 0x40000044;
+ets_install_lock = 0x40000048;
+UartRxString = 0x4000004c;
+UartGetCmdLn = 0x40000050;
+uart_tx_one_char = 0x40000054;
+uart_tx_one_char2 = 0x40000058;
+uart_tx_one_char3 = 0x4000005c;
+uart_rx_one_char = 0x40000060;
+uart_rx_one_char_block = 0x40000064;
+uart_rx_intr_handler = 0x40000068;
+uart_rx_readbuff = 0x4000006c;
+uartAttach = 0x40000070;
+uart_tx_flush = 0x40000074;
+uart_tx_wait_idle = 0x40000078;
+uart_div_modify = 0x4000007c;
+ets_write_char_uart = 0x40000080;
+uart_tx_switch = 0x40000084;
+uart_buff_switch = 0x40000088;
+roundup2 = 0x4000008c;
+multofup = 0x40000090;
+software_reset = 0x40000094;
+software_reset_cpu = 0x40000098;
+ets_clk_assist_debug_clock_enable = 0x4000009c;
+clear_super_wdt_reset_flag = 0x400000a0;
+disable_default_watchdog = 0x400000a4;
+ets_set_appcpu_boot_addr = 0x400000a8;
+send_packet = 0x400000ac;
+recv_packet = 0x400000b0;
+GetUartDevice = 0x400000b4;
+UartDwnLdProc = 0x400000b8;
+GetSecurityInfoProc = 0x400000bc;
+Uart_Init = 0x400000c0;
+ets_set_user_start = 0x400000c4;
+/* Data (.data, .bss, .rodata) */
+ets_rom_layout_p = 0x4001fffc;
+ets_ops_table_ptr = 0x4085fff4;
+g_saved_pc = 0x4085fff8;
+
+
+/***************************************
+ Group miniz
+ ***************************************/
+
+/* Functions */
+mz_adler32 = 0x400000c8;
+mz_free = 0x400000cc;
+tdefl_compress = 0x400000d0;
+tdefl_compress_buffer = 0x400000d4;
+tdefl_compress_mem_to_heap = 0x400000d8;
+tdefl_compress_mem_to_mem = 0x400000dc;
+tdefl_compress_mem_to_output = 0x400000e0;
+tdefl_get_adler32 = 0x400000e4;
+tdefl_get_prev_return_status = 0x400000e8;
+tdefl_init = 0x400000ec;
+tdefl_write_image_to_png_file_in_memory = 0x400000f0;
+tdefl_write_image_to_png_file_in_memory_ex = 0x400000f4;
+tinfl_decompress = 0x400000f8;
+tinfl_decompress_mem_to_callback = 0x400000fc;
+tinfl_decompress_mem_to_heap = 0x40000100;
+tinfl_decompress_mem_to_mem = 0x40000104;
+
+
+/***************************************
+ Group spi_extmem_common
+ ***************************************/
+
+/* Functions */
+esp_rom_spi_cmd_config = 0x40000108;
+esp_rom_spi_cmd_start = 0x4000010c;
+esp_rom_spi_set_op_mode = 0x40000110;
+
+
+/***************************************
+ Group spiflash_legacy
+ ***************************************/
+
+/* Functions */
+esp_rom_spiflash_wait_idle = 0x40000114;
+esp_rom_spiflash_write_encrypted = 0x40000118;
+esp_rom_spiflash_write_encrypted_dest = 0x4000011c;
+esp_rom_spiflash_write_encrypted_enable = 0x40000120;
+esp_rom_spiflash_write_encrypted_disable = 0x40000124;
+esp_rom_spiflash_erase_chip = 0x40000128;
+_esp_rom_spiflash_erase_sector = 0x4000012c;
+_esp_rom_spiflash_erase_block = 0x40000130;
+_esp_rom_spiflash_write = 0x40000134;
+_esp_rom_spiflash_read = 0x40000138;
+_esp_rom_spiflash_unlock = 0x4000013c;
+_SPIEraseArea = 0x40000140;
+_SPI_write_enable = 0x40000144;
+esp_rom_spiflash_erase_sector = 0x40000148;
+esp_rom_spiflash_erase_block = 0x4000014c;
+esp_rom_spiflash_write = 0x40000150;
+esp_rom_spiflash_read = 0x40000154;
+esp_rom_spiflash_unlock = 0x40000158;
+SPIEraseArea = 0x4000015c;
+SPI_write_enable = 0x40000160;
+esp_rom_spiflash_config_param = 0x40000164;
+esp_rom_spiflash_read_user_cmd = 0x40000168;
+esp_rom_spiflash_select_qio_pins = 0x4000016c;
+esp_rom_spi_flash_auto_sus_res = 0x40000170;
+esp_rom_spi_flash_send_resume = 0x40000174;
+esp_rom_spi_flash_update_id = 0x40000178;
+esp_rom_spiflash_config_clk = 0x4000017c;
+esp_rom_spiflash_config_readmode = 0x40000180;
+esp_rom_spiflash_read_status = 0x40000184;
+esp_rom_spiflash_read_statushigh = 0x40000188;
+esp_rom_spiflash_write_status = 0x4000018c;
+esp_rom_spiflash_write_disable = 0x40000190;
+spi_cache_mode_switch = 0x40000194;
+spi_common_set_dummy_output = 0x40000198;
+spi_common_set_flash_cs_timing = 0x4000019c;
+esp_rom_spi_set_address_bit_len = 0x400001a0;
+SPILock = 0x400001a4;
+SPIMasterReadModeCnfig = 0x400001a8;
+SPI_Common_Command = 0x400001ac;
+SPI_WakeUp = 0x400001b0;
+SPI_block_erase = 0x400001b4;
+SPI_chip_erase = 0x400001b8;
+SPI_init = 0x400001bc;
+SPI_page_program = 0x400001c0;
+SPI_read_data = 0x400001c4;
+SPI_sector_erase = 0x400001c8;
+SelectSpiFunction = 0x400001cc;
+SetSpiDrvs = 0x400001d0;
+Wait_SPI_Idle = 0x400001d4;
+spi_dummy_len_fix = 0x400001d8;
+Disable_QMode = 0x400001dc;
+Enable_QMode = 0x400001e0;
+spi_flash_attach = 0x400001e4;
+spi_flash_get_chip_size = 0x400001e8;
+spi_flash_guard_set = 0x400001ec;
+spi_flash_guard_get = 0x400001f0;
+spi_flash_read_encrypted = 0x400001f4;
+/* Data (.data, .bss, .rodata) */
+rom_spiflash_legacy_funcs = 0x4085ffec;
+rom_spiflash_legacy_data = 0x4085ffe8;
+g_flash_guard_ops = 0x4085fff0;
+
+
+/***************************************
+ Group cache
+ ***************************************/
+
+/* Functions */
+Cache_Get_Line_Size = 0x400005d8;
+Cache_Get_Mode = 0x400005dc;
+Cache_Address_Through_Cache = 0x400005e0;
+ROM_Boot_Cache_Init = 0x400005e4;
+Cache_Sync_Items = 0x400005e8;
+Cache_Op_Addr = 0x400005ec;
+Cache_Invalidate_Addr = 0x400005f0;
+Cache_Clean_Addr = 0x400005f4;
+Cache_WriteBack_Addr = 0x400005f8;
+Cache_WriteBack_Invalidate_Addr = 0x400005fc;
+Cache_Invalidate_All = 0x40000600;
+Cache_Clean_All = 0x40000604;
+Cache_WriteBack_All = 0x40000608;
+Cache_WriteBack_Invalidate_All = 0x4000060c;
+Cache_Mask_All = 0x40000610;
+Cache_UnMask_Dram0 = 0x40000614;
+Cache_Suspend_Autoload = 0x40000618;
+Cache_Resume_Autoload = 0x4000061c;
+Cache_Start_Preload = 0x40000620;
+Cache_Preload_Done = 0x40000624;
+Cache_End_Preload = 0x40000628;
+Cache_Config_Autoload = 0x4000062c;
+Cache_Enable_Autoload = 0x40000630;
+Cache_Disable_Autoload = 0x40000634;
+Cache_Enable_PreLock = 0x40000638;
+Cache_Disable_PreLock = 0x4000063c;
+Cache_Lock_Items = 0x40000640;
+Cache_Lock_Addr = 0x40000644;
+Cache_Unlock_Addr = 0x40000648;
+Cache_Disable_Cache = 0x4000064c;
+Cache_Enable_Cache = 0x40000650;
+Cache_Suspend_Cache = 0x40000654;
+Cache_Resume_Cache = 0x40000658;
+Cache_Freeze_Enable = 0x4000065c;
+Cache_Freeze_Disable = 0x40000660;
+Cache_Set_IDROM_MMU_Size = 0x40000664;
+Cache_Get_IROM_MMU_End = 0x40000668;
+Cache_Get_DROM_MMU_End = 0x4000066c;
+Cache_MMU_Init = 0x40000670;
+Cache_MSPI_MMU_Set = 0x40000674;
+Cache_MSPI_MMU_Set_Secure = 0x40000678;
+Cache_Count_Flash_Pages = 0x4000067c;
+Cache_Travel_Tag_Memory = 0x40000680;
+Cache_Get_Virtual_Addr = 0x40000684;
+flash2spiram_instruction_offset = 0x40000688;
+flash2spiram_rodata_offset = 0x4000068c;
+flash_instr_rodata_start_page = 0x40000690;
+flash_instr_rodata_end_page = 0x40000694;
+Cache_Set_IDROM_MMU_Info = 0x40000698;
+Cache_Flash_To_SPIRAM_Copy = 0x4000069c;
+/* Data (.data, .bss, .rodata) */
+rom_cache_op_cb = 0x4085ffc8;
+rom_cache_internal_table_ptr = 0x4085ffc4;
+
+
+/***************************************
+ Group clock
+ ***************************************/
+
+/* Functions */
+ets_clk_get_xtal_freq = 0x400006a0;
+ets_clk_get_cpu_freq = 0x400006a4;
+
+
+/***************************************
+ Group gpio
+ ***************************************/
+
+/* Functions */
+gpio_set_output_level = 0x400006a8;
+gpio_get_input_level = 0x400006ac;
+gpio_matrix_in = 0x400006b0;
+gpio_matrix_out = 0x400006b4;
+gpio_bypass_matrix_in = 0x400006b8;
+/* gpio_output_disable = 0x400006bc; */
+/* gpio_output_enable = 0x400006c0; */
+gpio_pad_input_disable = 0x400006c4;
+gpio_pad_input_enable = 0x400006c8;
+gpio_pad_pulldown = 0x400006cc;
+gpio_pad_pullup = 0x400006d0;
+gpio_pad_select_gpio = 0x400006d4;
+gpio_pad_set_drv = 0x400006d8;
+gpio_pad_unhold = 0x400006dc;
+gpio_pad_hold = 0x400006e0;
+
+
+/***************************************
+ Group interrupts
+ ***************************************/
+
+/* Functions */
+esprv_intc_int_set_priority = 0x400006e4;
+esprv_intc_int_set_threshold = 0x400006e8;
+esprv_intc_int_enable = 0x400006ec;
+esprv_intc_int_disable = 0x400006f0;
+esprv_intc_int_set_type = 0x400006f4;
+PROVIDE( intr_handler_set = 0x400006f8 );
+intr_matrix_set = 0x400006fc;
+ets_intr_register_ctx = 0x40000700;
+ets_intr_lock = 0x40000704;
+ets_intr_unlock = 0x40000708;
+ets_isr_attach = 0x4000070c;
+ets_isr_mask = 0x40000710;
+ets_isr_unmask = 0x40000714;
+
+
+/***************************************
+ Group crc
+ ***************************************/
+
+/* Functions */
+crc32_le = 0x40000718;
+crc16_le = 0x4000071c;
+crc8_le = 0x40000720;
+crc32_be = 0x40000724;
+crc16_be = 0x40000728;
+crc8_be = 0x4000072c;
+esp_crc8 = 0x40000730;
+/* Data (.data, .bss, .rodata) */
+crc32_le_table_ptr = 0x4001fff8;
+crc16_le_table_ptr = 0x4001fff4;
+crc8_le_table_ptr = 0x4001fff0;
+crc32_be_table_ptr = 0x4001ffec;
+crc16_be_table_ptr = 0x4001ffe8;
+crc8_be_table_ptr = 0x4001ffe4;
+
+
+/***************************************
+ Group md5
+ ***************************************/
+
+/* Functions */
+md5_vector = 0x40000734;
+MD5Init = 0x40000738;
+MD5Update = 0x4000073c;
+MD5Final = 0x40000740;
+
+
+/***************************************
+ Group hwcrypto
+ ***************************************/
+
+/* Functions */
+ets_sha_enable = 0x40000744;
+ets_sha_disable = 0x40000748;
+ets_sha_get_state = 0x4000074c;
+ets_sha_init = 0x40000750;
+ets_sha_process = 0x40000754;
+ets_sha_starts = 0x40000758;
+ets_sha_update = 0x4000075c;
+ets_sha_finish = 0x40000760;
+ets_sha_clone = 0x40000764;
+ets_hmac_enable = 0x40000768;
+ets_hmac_disable = 0x4000076c;
+ets_hmac_calculate_message = 0x40000770;
+ets_hmac_calculate_downstream = 0x40000774;
+ets_hmac_invalidate_downstream = 0x40000778;
+ets_aes_enable = 0x4000077c;
+ets_aes_disable = 0x40000780;
+ets_aes_setkey = 0x40000784;
+ets_aes_block = 0x40000788;
+ets_aes_setkey_dec = 0x4000078c;
+ets_aes_setkey_enc = 0x40000790;
+
+
+/***************************************
+ Group efuse
+ ***************************************/
+
+/* Functions */
+ets_efuse_read = 0x40000794;
+ets_efuse_program = 0x40000798;
+ets_efuse_clear_program_registers = 0x4000079c;
+ets_efuse_write_key = 0x400007a0;
+ets_efuse_get_read_register_address = 0x400007a4;
+ets_efuse_get_key_purpose = 0x400007a8;
+ets_efuse_key_block_unused = 0x400007ac;
+ets_efuse_find_unused_key_block = 0x400007b0;
+ets_efuse_rs_calculate = 0x400007b4;
+ets_efuse_count_unused_key_blocks = 0x400007b8;
+ets_efuse_secure_boot_enabled = 0x400007bc;
+ets_efuse_secure_boot_aggressive_revoke_enabled = 0x400007c0;
+ets_efuse_cache_encryption_enabled = 0x400007c4;
+ets_efuse_download_modes_disabled = 0x400007c8;
+ets_efuse_find_purpose = 0x400007cc;
+ets_efuse_force_send_resume = 0x400007d0;
+ets_efuse_get_flash_delay_us = 0x400007d4;
+ets_efuse_get_uart_print_control = 0x400007d8;
+ets_efuse_direct_boot_mode_disabled = 0x400007dc;
+ets_efuse_security_download_modes_enabled = 0x400007e0;
+ets_efuse_jtag_disabled = 0x400007e4;
+ets_efuse_usb_print_is_disabled = 0x400007e8;
+ets_efuse_usb_download_mode_disabled = 0x400007ec;
+ets_efuse_usb_device_disabled = 0x400007f0;
+ets_jtag_enable_temporarily = 0x400007f4;
+
+
+/***************************************
+ Group key_mgr
+ ***************************************/
+
+/* Functions */
+esp_rom_check_recover_key = 0x400007f8;
+esp_rom_km_huk_conf = 0x400007fc;
+esp_rom_km_huk_risk = 0x40000800;
+
+
+/***************************************
+ Group secureboot
+ ***************************************/
+
+/* Functions */
+ets_ecdsa_verify = 0x40000804;
+ets_secure_boot_verify_bootloader_with_keys = 0x40000808;
+ets_secure_boot_verify_signature = 0x4000080c;
+ets_secure_boot_read_key_digests = 0x40000810;
+ets_secure_boot_revoke_public_key_digest = 0x40000814;
+
+
+/***************************************
+ Group usb_device_uart
+ ***************************************/
+
+/* Functions */
+usb_serial_device_rx_one_char = 0x40000944;
+usb_serial_device_rx_one_char_block = 0x40000948;
+usb_serial_device_tx_flush = 0x4000094c;
+usb_serial_device_tx_one_char = 0x40000950;

components/esp_rom/esp32h4/ld/esp32h4.rom.libc.ld

@@ -0,0 +1,65 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+esp_rom_newlib_init_common_mutexes = 0x40000478;
+memset = 0x4000047c;
+memcpy = 0x40000480;
+memmove = 0x40000484;
+memcmp = 0x40000488;
+strcpy = 0x4000048c;
+strncpy = 0x40000490;
+strcmp = 0x40000494;
+strncmp = 0x40000498;
+strlen = 0x4000049c;
+strstr = 0x400004a0;
+bzero = 0x400004a4;
+sbrk = 0x400004ac;
+isalnum = 0x400004b0;
+isalpha = 0x400004b4;
+isascii = 0x400004b8;
+isblank = 0x400004bc;
+iscntrl = 0x400004c0;
+isdigit = 0x400004c4;
+islower = 0x400004c8;
+isgraph = 0x400004cc;
+isprint = 0x400004d0;
+ispunct = 0x400004d4;
+isspace = 0x400004d8;
+isupper = 0x400004dc;
+toupper = 0x400004e0;
+tolower = 0x400004e4;
+toascii = 0x400004e8;
+memccpy = 0x400004ec;
+memchr = 0x400004f0;
+memrchr = 0x400004f4;
+strcasecmp = 0x400004f8;
+strcasestr = 0x400004fc;
+strcat = 0x40000500;
+strchr = 0x40000508;
+strcspn = 0x4000050c;
+strcoll = 0x40000510;
+strlcat = 0x40000514;
+strlcpy = 0x40000518;
+strlwr = 0x4000051c;
+strncasecmp = 0x40000520;
+strncat = 0x40000524;
+strnlen = 0x4000052c;
+strrchr = 0x40000530;
+strsep = 0x40000534;
+strspn = 0x40000538;
+strtok_r = 0x4000053c;
+strupr = 0x40000540;
+longjmp = 0x40000544;
+setjmp = 0x40000548;
+abs = 0x4000054c;
+div = 0x40000550;
+labs = 0x40000554;
+ldiv = 0x40000558;
+qsort = 0x4000055c;
+utoa = 0x4000056c;
+itoa = 0x40000570;
+/* Data (.data, .bss, .rodata) */
+syscall_table_ptr = 0x4085ffd0;
+_global_impure_ptr = 0x4085ffcc;

components/esp_rom/esp32h4/ld/esp32h4.rom.libgcc.ld

@@ -0,0 +1,95 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32h4.rom.libgcc.ld for esp32h4
+ *
+ *
+ * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group libgccdf
+ ***************************************/
+
+/* Functions */
+__absvdi2 = 0x40000818;
+__absvsi2 = 0x4000081c;
+__adddf3 = 0x40000820;
+__addvdi3 = 0x40000824;
+__addvsi3 = 0x40000828;
+__ashldi3 = 0x4000082c;
+__ashrdi3 = 0x40000830;
+__bswapdi2 = 0x40000834;
+__bswapsi2 = 0x40000838;
+__clear_cache = 0x4000083c;
+__clrsbdi2 = 0x40000840;
+__clrsbsi2 = 0x40000844;
+__clzdi2 = 0x40000848;
+__clzsi2 = 0x4000084c;
+__cmpdi2 = 0x40000850;
+__ctzdi2 = 0x40000854;
+__ctzsi2 = 0x40000858;
+__divdc3 = 0x4000085c;
+__divdf3 = 0x40000860;
+__divdi3 = 0x40000864;
+__divsc3 = 0x40000868;
+__divsi3 = 0x4000086c;
+__eqdf2 = 0x40000870;
+__extendsfdf2 = 0x40000874;
+__ffsdi2 = 0x40000878;
+__ffssi2 = 0x4000087c;
+__fixdfdi = 0x40000880;
+__fixdfsi = 0x40000884;
+__fixsfdi = 0x40000888;
+__fixunsdfsi = 0x4000088c;
+__fixunssfdi = 0x40000890;
+__fixunssfsi = 0x40000894;
+__floatdidf = 0x40000898;
+__floatdisf = 0x4000089c;
+__floatsidf = 0x400008a0;
+__floatundidf = 0x400008a4;
+__floatundisf = 0x400008a8;
+__floatunsidf = 0x400008ac;
+__gcc_bcmp = 0x400008b0;
+__gedf2 = 0x400008b4;
+__gtdf2 = 0x400008b8;
+__ledf2 = 0x400008bc;
+__lshrdi3 = 0x400008c0;
+__ltdf2 = 0x400008c4;
+__moddi3 = 0x400008c8;
+__modsi3 = 0x400008cc;
+__muldc3 = 0x400008d0;
+__muldf3 = 0x400008d4;
+__muldi3 = 0x400008d8;
+__mulsc3 = 0x400008dc;
+__mulsi3 = 0x400008e0;
+__mulvdi3 = 0x400008e4;
+__mulvsi3 = 0x400008e8;
+__nedf2 = 0x400008ec;
+__negdf2 = 0x400008f0;
+__negdi2 = 0x400008f4;
+__negvdi2 = 0x400008f8;
+__negvsi2 = 0x400008fc;
+__paritysi2 = 0x40000900;
+__popcountdi2 = 0x40000904;
+__popcountsi2 = 0x40000908;
+__powidf2 = 0x4000090c;
+__subdf3 = 0x40000910;
+__subvdi3 = 0x40000914;
+__subvsi3 = 0x40000918;
+__ucmpdi2 = 0x4000091c;
+__udivdi3 = 0x40000920;
+__udivmoddi4 = 0x40000924;
+__udivsi3 = 0x40000928;
+__udiv_w_sdiv = 0x4000092c;
+__umoddi3 = 0x40000930;
+__umodsi3 = 0x40000934;
+__unorddf2 = 0x40000938;
+__extenddftf2 = 0x4000093c;
+__trunctfdf2 = 0x40000940;

components/esp_rom/esp32h4/ld/esp32h4.rom.newlib-nano.ld

@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32h4.rom.newlib-nano.ld for esp32h4
+ *
+ *
+ * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group newlib_nano_format
+ ***************************************/
+
+/* Functions */
+__sprint_r = 0x400005a8;
+_fiprintf_r = 0x400005ac;
+_fprintf_r = 0x400005b0;
+_printf_common = 0x400005b4;
+_printf_i = 0x400005b8;
+_vfiprintf_r = 0x400005bc;
+_vfprintf_r = 0x400005c0;
+fiprintf = 0x400005c4;
+fprintf = 0x400005c8;
+printf = 0x400005cc;
+vfiprintf = 0x400005d0;
+vfprintf = 0x400005d4;

components/esp_rom/esp32h4/ld/esp32h4.rom.newlib.ld

@@ -0,0 +1,41 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32h4.rom.newlib.ld for esp32h4
+ *
+ *
+ * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. !!! BUT EDITED !!!
+ * The file was originally generated for use with newlib, but it was split into
+ * multiple files to make it compatible with picolibc.
+ */
+
+/***************************************
+ Group newlib
+ ***************************************/
+
+/* Functions */
+_isatty_r = 0x400004a8;
+strdup = 0x40000504;
+strndup = 0x40000528;
+rand_r = 0x40000560;
+rand = 0x40000564;
+srand = 0x40000568;
+atoi = 0x40000574;
+atol = 0x40000578;
+strtol = 0x4000057c;
+strtoul = 0x40000580;
+fflush = 0x40000584;
+_fflush_r = 0x40000588;
+_fwalk = 0x4000058c;
+_fwalk_reent = 0x40000590;
+__smakebuf_r = 0x40000594;
+__swhatbuf_r = 0x40000598;
+__swbuf_r = 0x4000059c;
+__swbuf = 0x400005a0;
+__swsetup_r = 0x400005a4;

components/esp_rom/esp32h4/ld/esp32h4.rom.spiflash.ld

@@ -0,0 +1,148 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32h4.rom.spiflash.ld for esp32h4
+ *
+ *
+ * Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group spi_flash_cache
+ ***************************************/
+
+/* Functions */
+spi_flash_disable_cache = 0x400001f8;
+spi_flash_restore_cache = 0x400001fc;
+spi_flash_cache_enabled = 0x40000200;
+spi_flash_enable_cache = 0x40000204;
+esp_enable_cache_flash_wrap = 0x40000208;
+
+
+/***************************************
+ Group esp_flash
+ ***************************************/
+
+/* Functions */
+esp_flash_chip_driver_initialized = 0x4000020c;
+esp_flash_read_id = 0x40000210;
+esp_flash_get_size = 0x40000214;
+esp_flash_erase_chip = 0x40000218;
+esp_flash_erase_region = 0x4000021c;
+esp_flash_get_chip_write_protect = 0x40000220;
+esp_flash_set_chip_write_protect = 0x40000224;
+esp_flash_get_protectable_regions = 0x40000228;
+esp_flash_get_protected_region = 0x4000022c;
+esp_flash_set_protected_region = 0x40000230;
+esp_flash_read = 0x40000234;
+esp_flash_write = 0x40000238;
+esp_flash_write_encrypted = 0x4000023c;
+esp_flash_read_encrypted = 0x40000240;
+esp_flash_get_io_mode = 0x40000244;
+esp_flash_set_io_mode = 0x40000248;
+spi_flash_boot_attach = 0x4000024c;
+esp_flash_read_chip_id = 0x40000250;
+detect_spi_flash_chip = 0x40000254;
+esp_flash_suspend_cmd_init = 0x40000258;
+/* Data (.data, .bss, .rodata) */
+esp_flash_default_chip = 0x4085ffe4;
+esp_flash_api_funcs = 0x4085ffe0;
+
+
+/***************************************
+ Group spi_flash_chips
+ ***************************************/
+
+/* Functions */
+spi_flash_chip_generic_probe = 0x4000025c;
+spi_flash_chip_generic_detect_size = 0x40000260;
+spi_flash_chip_generic_write = 0x40000264;
+spi_flash_chip_generic_write_encrypted = 0x40000268;
+spi_flash_chip_generic_set_write_protect = 0x4000026c;
+spi_flash_common_write_status_16b_wrsr = 0x40000270;
+spi_flash_chip_generic_reset = 0x40000274;
+spi_flash_chip_generic_erase_chip = 0x40000278;
+spi_flash_chip_generic_erase_sector = 0x4000027c;
+spi_flash_chip_generic_erase_block = 0x40000280;
+spi_flash_chip_generic_page_program = 0x40000284;
+spi_flash_chip_generic_get_write_protect = 0x40000288;
+spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x4000028c;
+spi_flash_chip_generic_read_reg = 0x40000290;
+spi_flash_chip_generic_yield = 0x40000294;
+spi_flash_generic_wait_host_idle = 0x40000298;
+spi_flash_chip_generic_wait_idle = 0x4000029c;
+spi_flash_chip_generic_config_host_io_mode = 0x400002a0;
+spi_flash_chip_generic_read = 0x400002a4;
+spi_flash_common_read_status_8b_rdsr2 = 0x400002a8;
+spi_flash_chip_generic_get_io_mode = 0x400002ac;
+spi_flash_common_read_status_8b_rdsr = 0x400002b0;
+spi_flash_common_write_status_8b_wrsr = 0x400002b4;
+spi_flash_common_write_status_8b_wrsr2 = 0x400002b8;
+spi_flash_common_set_io_mode = 0x400002bc;
+spi_flash_chip_generic_set_io_mode = 0x400002c0;
+spi_flash_chip_generic_read_unique_id = 0x400002c4;
+spi_flash_chip_generic_get_caps = 0x400002c8;
+spi_flash_chip_generic_suspend_cmd_conf = 0x400002cc;
+spi_flash_chip_gd_get_io_mode = 0x400002d0;
+spi_flash_chip_gd_probe = 0x400002d4;
+spi_flash_chip_gd_set_io_mode = 0x400002d8;
+/* Data (.data, .bss, .rodata) */
+spi_flash_chip_generic_config_data = 0x4085ffdc;
+spi_flash_encryption = 0x4085ffd8;
+
+
+/***************************************
+ Group memspi_host
+ ***************************************/
+
+/* Functions */
+memspi_host_read_id_hs = 0x400002dc;
+memspi_host_read_status_hs = 0x400002e0;
+memspi_host_flush_cache = 0x400002e4;
+memspi_host_erase_chip = 0x400002e8;
+memspi_host_erase_sector = 0x400002ec;
+memspi_host_erase_block = 0x400002f0;
+memspi_host_program_page = 0x400002f4;
+memspi_host_read = 0x400002f8;
+memspi_host_set_write_protect = 0x400002fc;
+memspi_host_set_max_read_len = 0x40000300;
+memspi_host_read_data_slicer = 0x40000304;
+memspi_host_write_data_slicer = 0x40000308;
+
+
+/***************************************
+ Group hal_spiflash
+ ***************************************/
+
+/* Functions */
+spi_flash_hal_poll_cmd_done = 0x4000030c;
+spi_flash_hal_device_config = 0x40000310;
+spi_flash_hal_configure_host_io_mode = 0x40000314;
+spi_flash_hal_common_command = 0x40000318;
+spi_flash_hal_read = 0x4000031c;
+spi_flash_hal_erase_chip = 0x40000320;
+spi_flash_hal_erase_sector = 0x40000324;
+spi_flash_hal_erase_block = 0x40000328;
+spi_flash_hal_program_page = 0x4000032c;
+spi_flash_hal_set_write_protect = 0x40000330;
+spi_flash_hal_host_idle = 0x40000334;
+spi_flash_hal_check_status = 0x40000338;
+spi_flash_hal_setup_read_suspend = 0x4000033c;
+spi_flash_hal_setup_auto_suspend_mode = 0x40000340;
+spi_flash_hal_setup_auto_resume_mode = 0x40000344;
+spi_flash_hal_disable_auto_suspend_mode = 0x40000348;
+spi_flash_hal_disable_auto_resume_mode = 0x4000034c;
+spi_flash_hal_resume = 0x40000350;
+spi_flash_hal_suspend = 0x40000354;
+spi_flash_encryption_hal_enable = 0x40000358;
+spi_flash_encryption_hal_disable = 0x4000035c;
+spi_flash_encryption_hal_prepare = 0x40000360;
+spi_flash_encryption_hal_done = 0x40000364;
+spi_flash_encryption_hal_destroy = 0x40000368;
+spi_flash_encryption_hal_check = 0x4000036c;

components/esp_rom/esp32h4/ld/esp32h4.rom.systimer.ld

@@ -0,0 +1,26 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/***************************************
+ Group hal_systimer
+ ***************************************/
+
+/* Functions */
+systimer_hal_init = 0x4000039c;
+systimer_hal_deinit = 0x400003a0;
+systimer_hal_set_tick_rate_ops = 0x400003a4;
+systimer_hal_get_counter_value = 0x400003a8;
+systimer_hal_get_time = 0x400003ac;
+systimer_hal_set_alarm_target = 0x400003b0;
+systimer_hal_set_alarm_period = 0x400003b4;
+systimer_hal_get_alarm_value = 0x400003b8;
+systimer_hal_enable_alarm_int = 0x400003bc;
+systimer_hal_on_apb_freq_update = 0x400003c0;
+systimer_hal_counter_value_advance = 0x400003c4;
+systimer_hal_enable_counter = 0x400003c8;
+systimer_hal_select_alarm_mode = 0x400003cc;
+systimer_hal_connect_alarm_counter = 0x400003d0;
+systimer_hal_counter_can_stall_by_cpu = 0x400003d4;

components/esp_rom/esp32h4/ld/esp32h4.rom.version.ld

@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM version variables for esp32h4
+ *
+ * These addresses should be compatible with any ROM version for this chip.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+_rom_chip_id = 0x40000010;
+_rom_eco_version = 0x40000014;

components/esp_rom/esp32h4/ld/esp32h4.rom.wdt.ld

@@ -0,0 +1,22 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/***************************************
+ Group hal_wdt
+ ***************************************/
+
+/* Functions */
+wdt_hal_init = 0x40000370;
+wdt_hal_deinit = 0x40000374;
+wdt_hal_config_stage = 0x40000378;
+wdt_hal_write_protect_disable = 0x4000037c;
+wdt_hal_write_protect_enable = 0x40000380;
+wdt_hal_enable = 0x40000384;
+wdt_hal_disable = 0x40000388;
+wdt_hal_handle_intr = 0x4000038c;
+wdt_hal_feed = 0x40000390;
+wdt_hal_set_flashboot_en = 0x40000394;
+wdt_hal_is_enabled = 0x40000398;

components/esp_rom/include/esp_rom_libc_stubs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -33,4 +33,6 @@
 #include "esp32p4/rom/libc_stubs.h"
 #elif CONFIG_IDF_TARGET_ESP32H21
 #include "esp32h21/rom/libc_stubs.h"
+#elif CONFIG_IDF_TARGET_ESP32H4
+#include "esp32h4/rom/libc_stubs.h"
 #endif

components/esp_rom/patches/esp_rom_hp_regi2c_esp32h4.c

@@ -0,0 +1,187 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "esp_rom_sys.h"
+#include "esp_attr.h"
+#include "soc/i2c_ana_mst_reg.h"
+
+// TODO: [ESP32H4] IDF-12315 inherit from verify code, need check
+
+/**
+ * BB    - 0x67 - BIT0
+ * TXRF  - 0x6B - BIT1
+ * SDM   - 0x63 - BIT2
+ * PLL   - 0x62 - BIT3
+ * BIAS  - 0x6A - BIT4
+ * BBPLL - 0x66 - BIT5
+ * ULP   - 0x61 - BIT6
+ * SAR   - 0x69 - BIT7
+ * PMU   - 0x6d - BIT8
+*/
+
+#define REGI2C_BIAS_MST_SEL    (BIT(8))
+#define REGI2C_BBPLL_MST_SEL   (BIT(9))
+#define REGI2C_ULP_CAL_MST_SEL (BIT(10))
+#define REGI2C_SAR_I2C_MST_SEL (BIT(11))
+#define REGI2C_DIG_REG_MST_SEL (BIT(12))
+
+#define REGI2C_BIAS_RD_MASK     (~BIT(6)    & I2C_ANA_MST_ANA_CONF1_M)
+#define REGI2C_BBPLL_RD_MASK    (~BIT(7)    & I2C_ANA_MST_ANA_CONF1_M)
+#define REGI2C_ULP_CAL_RD_MASK  (~BIT(8)    & I2C_ANA_MST_ANA_CONF1_M)
+#define REGI2C_SAR_I2C_RD_MASK  (~BIT(9)    & I2C_ANA_MST_ANA_CONF1_M)
+#define REGI2C_DIG_REG_RD_MASK  (~BIT(10)   & I2C_ANA_MST_ANA_CONF1_M)
+
+#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_ANA_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG
+
+#define REGI2C_RTC_BUSY           (BIT(25))
+#define REGI2C_RTC_BUSY_M         (BIT(25))
+#define REGI2C_RTC_BUSY_V         0x1
+#define REGI2C_RTC_BUSY_S         25
+
+#define REGI2C_RTC_WR_CNTL        (BIT(24))
+#define REGI2C_RTC_WR_CNTL_M      (BIT(24))
+#define REGI2C_RTC_WR_CNTL_V      0x1
+#define REGI2C_RTC_WR_CNTL_S      24
+
+#define REGI2C_RTC_DATA           0x000000FF
+#define REGI2C_RTC_DATA_M         ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
+#define REGI2C_RTC_DATA_V         0xFF
+#define REGI2C_RTC_DATA_S         16
+
+#define REGI2C_RTC_ADDR           0x000000FF
+#define REGI2C_RTC_ADDR_M         ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
+#define REGI2C_RTC_ADDR_V         0xFF
+#define REGI2C_RTC_ADDR_S         8
+
+#define REGI2C_RTC_SLAVE_ID       0x000000FF
+#define REGI2C_RTC_SLAVE_ID_M     ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
+#define REGI2C_RTC_SLAVE_ID_V     0xFF
+#define REGI2C_RTC_SLAVE_ID_S     0
+
+/* SLAVE */
+
+#define REGI2C_BBPLL              (0x66)
+#define REGI2C_BBPLL_HOSTID       0
+
+#define REGI2C_BIAS               (0x6a)
+#define REGI2C_BIAS_HOSTID        0
+
+#define REGI2C_DIG_REG            (0x6d)
+#define REGI2C_DIG_REG_HOSTID     0
+
+#define REGI2C_ULP_CAL            (0x61)
+#define REGI2C_ULP_CAL_HOSTID     0
+
+#define REGI2C_SAR_I2C            (0x69)
+#define REGI2C_SAR_I2C_HOSTID     0
+
+/* SLAVE END */
+
+// uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl")));
+// uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl")));
+// void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl")));
+// void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl")));
+
+// static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
+// {
+//     uint32_t i2c_sel = 0;
+
+//     /* Before config I2C register, enable corresponding slave. */
+//     switch (block) {
+//     case REGI2C_BBPLL  :
+//         i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL);
+//         REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK);
+//         break;
+//     case REGI2C_BIAS   :
+//         i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL);
+//         REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK);
+//         break;
+//     case REGI2C_DIG_REG:
+//         i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL);
+//         REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK);
+//         break;
+//     case REGI2C_ULP_CAL:
+//         i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL);
+//         REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK);
+//         break;
+//     case REGI2C_SAR_I2C:
+//         i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL);
+//         REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK);
+//         break;
+//     }
+
+//     return (uint8_t)(i2c_sel ? 0: 1);
+// }
+
+// uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add)
+// {
+//     (void)host_id;
+//     uint8_t i2c_sel = regi2c_enable_block(block);
+
+//     while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
+//     uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
+//                     | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
+//     REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
+//     while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
+//     uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
+
+//     return ret;
+// }
+
+// uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
+// {
+//     assert(msb - lsb < 8);
+//     uint8_t i2c_sel = regi2c_enable_block(block);
+
+//     (void)host_id;
+//     while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
+//     uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
+//                     | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
+//     REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
+//     while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
+//     uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
+//     uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
+
+//     return ret;
+// }
+
+// void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
+// {
+//     (void)host_id;
+//     uint8_t i2c_sel = regi2c_enable_block(block);
+
+//     while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
+//     uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
+//                     | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
+//                     | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register;
+//                     | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
+//     REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
+//     while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
+
+// }
+
+// void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
+// {
+//     (void)host_id;
+//     assert(msb - lsb < 8);
+//     uint8_t i2c_sel = regi2c_enable_block(block);
+
+//     while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
+//     /*Read the i2c bus register*/
+//     uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
+//                     | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
+//     REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
+//     while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
+//     temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
+//     /*Write the i2c bus register*/
+//     temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)));
+//     temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp;
+//     temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
+//             | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
+//             | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S)
+//             | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
+//     REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
+//     while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
+// }

components/esp_rom/patches/esp_rom_systimer.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -64,7 +64,7 @@ void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t co
 }
 #endif // CONFIG_IDF_TARGET_ESP32C2 && (CONFIG_ESP32C2_REV_MIN_FULL < 200)
 
-#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H21
+#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4
 void systimer_hal_init(systimer_hal_context_t *hal)
 {
     hal->dev = &SYSTIMER;
@@ -78,6 +78,6 @@ void systimer_hal_deinit(systimer_hal_context_t *hal)
     systimer_ll_enable_clock(hal->dev, false);
     hal->dev = NULL;
 }
-#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
+#endif // CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61  || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H21 || CONFIG_IDF_TARGET_ESP32H4
 
 #endif // CONFIG_HAL_SYSTIMER_USE_ROM_IMPL

components/esp_system/port/soc/esp32c6/clk.c

@@ -291,8 +291,11 @@ __attribute__((weak)) void esp_perip_clk_init(void)
         periph_ll_disable_clk_set_rst(PERIPH_ASSIST_DEBUG_MODULE);
 #endif
         periph_ll_disable_clk_set_rst(PERIPH_RSA_MODULE);
+#if !CONFIG_SECURE_ENABLE_TEE
+        // NOTE: [ESP-TEE] The TEE is responsible for the AES and SHA peripherals
         periph_ll_disable_clk_set_rst(PERIPH_AES_MODULE);
         periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE);
+#endif
         periph_ll_disable_clk_set_rst(PERIPH_ECC_MODULE);
         periph_ll_disable_clk_set_rst(PERIPH_HMAC_MODULE);
         periph_ll_disable_clk_set_rst(PERIPH_DS_MODULE);

components/esp_tee/include/esp_tee.h

@@ -43,9 +43,8 @@ typedef struct {
     uint32_t magic_word;
     uint32_t api_major_version;
     uint32_t api_minor_version;
-    uint32_t reserved[2];
+    uint32_t reserved[3];
     /* TEE-related fields */
-    void *s_entry_addr;
     void *s_int_handler;
     /* REE-related fields */
     void *ns_entry_addr;
@@ -85,14 +84,12 @@ uint32_t esp_tee_service_call_with_noniram_intr_disabled(int argc, ...);
 
 #if !(__DOXYGEN__)
 /* Offsets of some values in esp_tee_config_t that are used by assembly code */
-#define ESP_TEE_CFG_OFFS_S_ENTRY_ADDR      0x14
 #define ESP_TEE_CFG_OFFS_S_INTR_HANDLER    0x18
 #define ESP_TEE_CFG_OFFS_NS_ENTRY_ADDR     0x1C
 #define ESP_TEE_CFG_OFFS_NS_INTR_HANDLER   0x20
 
 #if !defined(__ASSEMBLER__)
 /* Check the offsets are correct using the C compiler */
-ESP_STATIC_ASSERT(offsetof(esp_tee_config_t, s_entry_addr) == ESP_TEE_CFG_OFFS_S_ENTRY_ADDR, "offset macro is wrong");
 ESP_STATIC_ASSERT(offsetof(esp_tee_config_t, s_int_handler) == ESP_TEE_CFG_OFFS_S_INTR_HANDLER, "offset macro is wrong");
 ESP_STATIC_ASSERT(offsetof(esp_tee_config_t, ns_entry_addr) == ESP_TEE_CFG_OFFS_NS_ENTRY_ADDR, "offset macro is wrong");
 ESP_STATIC_ASSERT(offsetof(esp_tee_config_t, ns_int_handler) == ESP_TEE_CFG_OFFS_NS_INTR_HANDLER, "offset macro is wrong");

components/esp_tee/scripts/esp32c6/sec_srv_tbl_default.yml

@@ -208,6 +208,10 @@ secure_services:
         type: IDF
         function: esp_sha_write_digest_state
         args: 2
+      - id: 132
+        type: IDF
+        function: esp_sha_enable_periph_clk
+        args: 1
   # ID: 134-149 (16) - eFuse
   - family: efuse
     entries:

components/esp_tee/src/esp_secure_service_wrapper.c

@@ -228,6 +228,11 @@ void __wrap_esp_sha_write_digest_state(esp_sha_type sha_type, void *digest_state
     esp_tee_service_call(3, SS_ESP_SHA_WRITE_DIGEST_STATE, sha_type, digest_state);
 }
 
+void __wrap_esp_sha_enable_periph_clk(bool enable)
+{
+    esp_tee_service_call(2, SS_ESP_SHA_ENABLE_PERIPH_CLK, enable);
+}
+
 /* ---------------------------------------------- MMU HAL ------------------------------------------------- */
 
 void IRAM_ATTR __wrap_mmu_hal_map_region(uint32_t mmu_id, mmu_target_t mem_type, uint32_t vaddr, uint32_t paddr, uint32_t len, uint32_t *out_len)

components/esp_tee/src/esp_tee_config.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -25,9 +25,9 @@ esp_tee_config_t esp_tee_app_config __attribute__((section(".esp_tee_app_cfg")))
     .api_major_version = ESP_TEE_API_MAJOR_VER,
     .api_minor_version = ESP_TEE_API_MINOR_VER,
 
-    /* .s_entry_addr and .s_intr_handler are NULL in the
+    /* s_intr_handler is NULL in the REE image, but will be written by
-       app binary, but will be written by the TEE before it loads the binary
+     * the TEE before it loads the binary
-    */
+     */
 
     .ns_int_handler = &_tee_interrupt_handler,
     .ns_entry_addr = &_u2m_switch,

components/esp_tee/subproject/main/CMakeLists.txt

@@ -20,8 +20,7 @@ set(srcs "core/esp_tee_init.c"
 
 # Arch specific implementation for TEE
 list(APPEND srcs "arch/${arch}/esp_tee_vectors.S"
-                 "arch/${arch}/esp_tee_vector_table.S"
+                 "arch/${arch}/esp_tee_vector_table.S")
-                 "arch/${arch}/esp_tee_secure_entry.S")
 
 # SoC specific implementation for TEE
 list(APPEND srcs "soc/${target}/esp_tee_secure_sys_cfg.c"
@@ -78,7 +77,9 @@ list(APPEND srcs "common/esp_app_desc_tee.c")
 idf_component_register(SRCS ${srcs}
                        INCLUDE_DIRS ${include})
 
-set_source_files_properties("core/esp_secure_services.c" PROPERTIES COMPILE_FLAGS -Wno-deprecated)
+# TODO: Currently only -Og optimization level works correctly at runtime
+set_source_files_properties("core/esp_secure_dispatcher.c" PROPERTIES COMPILE_FLAGS "-Og")
+
 include(${CMAKE_CURRENT_LIST_DIR}/ld/esp_tee_ld.cmake)
 
 # esp_app_desc_t configuration structure for TEE: Linking symbol and trimming project version and name

components/esp_tee/subproject/main/arch/riscv/esp_tee_secure_entry.S

@@ -1,42 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#include "soc/tee_reg.h"
-#include "soc/plic_reg.h"
-
-    .global   esp_tee_service_dispatcher
-
-/* Entry point to the secure world (i.e. M-mode) - responsible for
- * setting up the execution environment for the secure world */
-    .section .text
-    .align  4
-    .global _sec_world_entry
-    .type _sec_world_entry, @function
-_sec_world_entry:
-    /* Setup the APM for HP CPU in TEE mode */
-    li      t0, TEE_M0_MODE_CTRL_REG
-    sw      zero, 0(t0)                  /* APM_LL_SECURE_MODE_TEE = 0 */
-
-    /* Disable the U-mode delegation of all interrupts */
-    csrwi   mideleg, 0
-
-    /* Jump to the secure service dispatcher */
-    jal     esp_tee_service_dispatcher
-
-    /* Setup the APM for HP CPU in REE mode */
-    li      t0, TEE_M0_MODE_CTRL_REG
-    li      t1, 0x1                      /* APM_LL_SECURE_MODE_REE = 1 */
-    sw      t1, 0(t0)
-
-    /* Enable the U-mode delegation of all interrupts (except the TEE secure interrupt) */
-    li      t0, 0xffffbfff
-    csrw    mideleg, t0
-
-    /* Fire an M-ecall */
-    mv      a1, zero
-    ecall
-    fence
-
-    ret

components/esp_tee/subproject/main/arch/riscv/esp_tee_vectors.S

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,7 @@
 
 #include "riscv/encoding.h"
 #include "riscv/rvruntime-frames.h"
+#include "esp_private/vectors_const.h"
 
 #include "esp_tee.h"
 #include "sdkconfig.h"
@@ -25,9 +26,12 @@
     .equ ECALL_U_MODE, 0x8
     .equ ECALL_M_MODE, 0xb
     .equ TEE_APM_INTR_MASK_0, 0x00300000
-    .equ TEE_APM_INTR_MASK_1, 0x000000F8
+    .equ TEE_APM_INTR_MASK_1, 0x000000f8
+    .equ TEE_INTR_DELEG_MASK, 0xffffbfff
 
     .global esp_tee_global_interrupt_handler
+    .global   esp_tee_service_dispatcher
+
 
     .section .data
     .align 4
@@ -177,15 +181,18 @@ _panic_handler:
     addi    sp, sp, -16
     sw      t0, 0(sp)
 
-    /* Check whether the exception is an M-mode ecall */
+    /* Read mcause */
     csrr    t0, mcause
-    xori    t0, t0, ECALL_M_MODE
+    li      t1, VECTORS_MCAUSE_INTBIT_MASK | VECTORS_MCAUSE_REASON_MASK
-    beqz    t0, _machine_ecall
+    and     t0, t0, t1
+
+    /* Check whether the exception is an M-mode ecall */
+    li      t1, ECALL_M_MODE
+    beq     t0, t1, _machine_ecall
 
     /* Check whether the exception is an U-mode ecall */
-    csrr    t0, mcause
+    li      t1, ECALL_U_MODE
-    xori    t0, t0, ECALL_U_MODE
+    beq     t0, t1, _user_ecall
-    beqz    t0, _user_ecall
 
     /* Restore t0 from the stack */
     lw      t0, 0(sp)
@@ -250,6 +257,10 @@ _return_from_exception:
 _ecall_handler:
     /* M-mode ecall handler */
 _machine_ecall:
+    /* Set the privilege mode to transition to after mret to U-mode  */
+    li      t0, MSTATUS_MPP
+    csrc    mstatus, t0
+
     /* Check whether this is the first M-mode ecall (see esp_tee_init) and skip context restoration */
     lui     t0, ESP_TEE_M2U_SWITCH_MAGIC
     beq     a1, t0, _skip_ctx_restore
@@ -267,15 +278,10 @@ _machine_ecall:
     restore_general_regs RV_STK_FRMSZ
     csrrw   a0, mscratch, zero
 
-    /* This point is reached only after the first M-mode ecall, never again (see esp_tee_init) */
 _skip_ctx_restore:
     /* Copy the ra register to mepc which contains the user app entry point (i.e. call_start_cpu0) */
     csrw    mepc, ra
 
-    /* Set the privilege mode to transition to after mret to U-mode  */
-    li      t3, MSTATUS_MPP
-    csrc    mstatus, t3
-
     /* Jump to the REE */
     mret
 
@@ -291,28 +297,34 @@ _user_ecall:
     lw      t0, 0(sp)
     addi    sp, sp, 16
 
-    /* This point is reached after a secure service call is issued from the REE */
+    /* This point is reached when a secure service call is issued from the REE */
-    /* Save register context and the mepc */
+    /* Save register context and mepc */
     save_general_regs RV_STK_FRMSZ
     save_mepc
 
-    /* Saving the U-mode (i.e. REE) stack pointer */
+    /* Save the U-mode (i.e. REE) stack pointer */
     la      t0, _ns_sp
     sw      sp, 0(t0)
 
-    /* Switching to the M-mode (i.e. TEE) stack */
+    /* Switch to the M-mode (i.e. TEE) stack */
     la      sp, _tee_stack
 
-    /* Load the TEE entry point (see sec_world_entry) in the mepc */
+    /* Disable the U-mode delegation of all interrupts */
-    la      t2, esp_tee_app_config
+    csrwi   mideleg, 0
-    lw      t2, ESP_TEE_CFG_OFFS_S_ENTRY_ADDR(t2)
-    csrw    mepc, t2
 
-    /* Set the privilege mode to transition to after mret to M-mode  */
+    /* Enable interrupts */
-    li      t3, MSTATUS_MPP
+    csrsi   mstatus, MSTATUS_MIE
-    csrs    mstatus, t3
 
-    mret
+    /* Jump to the secure service dispatcher */
+    jal     esp_tee_service_dispatcher
+
+    /* Enable the U-mode delegation of all interrupts (except the TEE secure interrupt) */
+    li      t0, TEE_INTR_DELEG_MASK
+    csrs    mideleg, t0
+
+    /* Fire an M-ecall */
+    mv      a1, zero
+    ecall
 
     /* This point is reached after servicing a U-mode interrupt occurred
      * while executing a secure service */
@@ -333,7 +345,7 @@ _rtn_from_ns_int:
 
     /* Restore register context and resume the secure service */
     restore_mepc
-    restore_general_regs
+    restore_general_regs RV_STK_FRMSZ
 
     mret
 
@@ -347,7 +359,7 @@ _rtn_from_ns_int:
 _tee_ns_intr_handler:
     /* Start by saving the general purpose registers and the PC value before
      * the interrupt happened. */
-    save_general_regs
+    save_general_regs RV_STK_FRMSZ
     save_mepc
 
     /* Though it is not necessary we save GP and SP here.
@@ -357,7 +369,7 @@ _tee_ns_intr_handler:
     /* As gp register is not saved by the macro, save it here */
     sw      gp, RV_STK_GP(sp)
     /* Same goes for the SP value before trapping */
-    addi    t0, sp, CONTEXT_SIZE /* restore sp with the value when interrupt happened */
+    addi    t0, sp, RV_STK_FRMSZ /* restore sp with the value when interrupt happened */
     /* Save SP */
     sw      t0, RV_STK_SP(sp)
 
@@ -395,8 +407,8 @@ _tee_ns_intr_handler:
     csrw    mscratch, t0
 
     /* Enable the U-mode interrupt delegation (except for the TEE secure interrupt) */
-    li      t0, 0xffffbfff
+    li      t0, TEE_INTR_DELEG_MASK
-    csrw    mideleg, t0
+    csrs    mideleg, t0
 
     /* Place magic bytes in all the general registers */
     store_magic_general_regs
@@ -413,7 +425,7 @@ _tee_ns_intr_handler:
 _tee_s_intr_handler:
     /* Start by saving the general purpose registers and the PC value before
      * the interrupt happened. */
-    save_general_regs
+    save_general_regs RV_STK_FRMSZ
     save_mepc
 
     /* Though it is not necessary we save GP and SP here.
@@ -423,7 +435,7 @@ _tee_s_intr_handler:
     /* As gp register is not saved by the macro, save it here */
     sw      gp, RV_STK_GP(sp)
     /* Same goes for the SP value before trapping */
-    addi    t0, sp, CONTEXT_SIZE /* restore sp with the value when interrupt happened */
+    addi    t0, sp, RV_STK_FRMSZ /* restore sp with the value when interrupt happened */
     /* Save SP */
     sw      t0, RV_STK_SP(sp)
 
@@ -457,7 +469,7 @@ _save_reg_ctx:
 _continue:
     /* Before doing anything preserve the stack pointer */
     mv      s11, sp
-    /* Switching to the TEE interrupt stack */
+    /* Switch to the TEE interrupt stack */
     la      sp, _tee_intr_stack
     /* If this is a non-nested interrupt, SP now points to the interrupt stack */
 
@@ -527,7 +539,7 @@ _intr_hdlr_exec:
     mv      sp, s11
 
     restore_mepc
-    restore_general_regs
+    restore_general_regs RV_STK_FRMSZ
     /* exit, this will also re-enable the interrupts */
     mret
 

components/esp_tee/subproject/main/core/esp_secure_dispatcher.c

@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
+#include <string.h>
 #include <stdarg.h>
 #include "esp_log.h"
 #include "esp_tee.h"
@@ -34,13 +34,10 @@ static const secure_service_entry_t *find_service_by_id(uint32_t id)
 }
 
 /**
- * @brief Entry point to the TEE binary during secure service call. It decipher the call and dispatch it
+ * @brief Handles incoming secure service requests to the TEE.
- *        to corresponding Secure Service API in secure world.
+ *        Validates and routes each request to the appropriate
- * TODO: Fix the assembly routine here for compatibility with all levels of compiler optimizations
+ *        secure service implementation.
  */
-#pragma GCC push_options
-#pragma GCC optimize ("Og")
-
 int esp_tee_service_dispatcher(int argc, va_list ap)
 {
     if (argc > ESP_TEE_MAX_INPUT_ARG) {
@@ -50,7 +47,7 @@ int esp_tee_service_dispatcher(int argc, va_list ap)
     }
 
     int ret = -1;
-    uint32_t argv[ESP_TEE_MAX_INPUT_ARG], *argp;
+    uint32_t argv[ESP_TEE_MAX_INPUT_ARG] = {0};
 
     uint32_t sid = va_arg(ap, uint32_t);
     argc--;
@@ -58,13 +55,11 @@ int esp_tee_service_dispatcher(int argc, va_list ap)
     const secure_service_entry_t *service = find_service_by_id(sid);
     if (service == NULL) {
         ESP_LOGE(TAG, "Invalid service ID!");
-        va_end(ap);
         return ret;
     }
 
     if (argc != service->nargs) {
         ESP_LOGE(TAG, "Invalid number of arguments for service %d!", sid);
-        va_end(ap);
         return ret;
     }
 
@@ -73,65 +68,47 @@ int esp_tee_service_dispatcher(int argc, va_list ap)
     for (int i = 0; i < argc; i++) {
         argv[i] = va_arg(ap, uint32_t);
     }
-    argp = &argv[0];
+    uint32_t *argp = &argv[0];
-    va_end(ap);
 
     asm volatile(
-        "mv t0, %1 \n"
+        "mv t0, %1 \n"            // t0 = argc
-        "beqz t0, service_call \n"
+        "mv t1, %3 \n"            // t1 = argp
 
+        "li t2, 8 \n"              // t2 = 8 (max register args)
+        "ble t0, t2, load_regs \n" // If argc <= 8 (a0-a7), skip stack routine
+
+        // Store extra args (argc > 8) on stack
+        "mv t3, sp \n"
+        "addi t1, t1, 32 \n"
+
+        "stack_loop: \n"
+        "lw t4, 0(t1) \n"
+        "sw t4, 0(t3) \n"
+        "addi t1, t1, 4 \n"
+        "addi t3, t3, 4 \n"
+        "addi t0, t0, -1 \n"
+        "bge t0, t2, stack_loop \n"
+
+        // Load the first 8 arguments into a0-a7
+        "load_regs: \n"
         "lw a0, 0(%3) \n"
-        "addi t0, t0, -1 \n"
-        "beqz t0, service_call \n"
-
         "lw a1, 4(%3) \n"
-        "addi t0, t0, -1 \n"
-        "beqz t0, service_call \n"
-
         "lw a2, 8(%3) \n"
-        "addi t0, t0, -1 \n"
-        "beqz t0, service_call \n"
-
         "lw a3, 12(%3) \n"
-        "addi t0, t0, -1 \n"
-        "beqz t0, service_call \n"
-
         "lw a4, 16(%3) \n"
-        "addi t0, t0, -1 \n"
-        "beqz t0, service_call \n"
-
         "lw a5, 20(%3) \n"
-        "addi t0, t0, -1 \n"
-        "beqz t0, service_call \n"
-
         "lw a6, 24(%3) \n"
-        "addi t0, t0, -1 \n"
-        "beqz t0, service_call \n"
-
         "lw a7, 28(%3) \n"
-        "addi t0, t0, -1 \n"
+        "fence \n"
-        "beqz t0, service_call \n"
 
-        "addi %3, %3, 32 \n"
+        "mv t1, %2 \n"            // Load function pointer
-        "mv t2, sp \n"
+        "jalr 0(t1) \n"           // Call function
-        "loop: \n"
+        "mv %0, a0 \n"            // Store return value
-        "lw t1, 0(%3) \n"
-        "sw t1, 0(t2) \n"
-        "addi t0, t0, -1 \n"
-        "addi t2, t2, 4 \n"
-        "addi %3, %3, 4 \n"
-        "bnez t0, loop \n"
-
-        "service_call: \n"
-        "mv t1, %2 \n"
-        "jalr 0(t1) \n"
-        "mv %0, a0 \n"
         : "=r"(ret)
         : "r"(argc), "r"(fp_secure_service), "r"(argp)
-        : "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "t0", "t1", "t2"
+        : "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7",
+        "t0", "t1", "t2", "t3", "t4"
     );
 
     return ret;
 }
-
-#pragma GCC pop_options

components/esp_tee/subproject/main/core/esp_secure_services.c

@@ -26,6 +26,7 @@
 #include "soc/soc_caps.h"
 #include "aes/esp_aes.h"
 #include "sha/sha_core.h"
+#include "esp_sha_internal.h"
 
 #include "esp_tee.h"
 #include "esp_tee_memory_utils.h"
@@ -325,6 +326,11 @@ void _ss_esp_sha_block(esp_sha_type sha_type, const void *data_block, bool is_fi
     esp_sha_block(sha_type, data_block, is_first_block);
 }
 
+void _ss_esp_sha_enable_periph_clk(bool enable)
+{
+    esp_sha_enable_periph_clk(enable);
+}
+
 /* ---------------------------------------------- OTA ------------------------------------------------- */
 
 int _ss_esp_tee_ota_begin(void)

components/esp_tee/subproject/main/core/esp_tee_init.c

@@ -59,7 +59,6 @@ static void tee_init_app_config(void)
     esp_tee_app_config.api_minor_version = ESP_TEE_API_MINOR_VER;
 
     /* Set the TEE-related fields (from the TEE binary) that the REE will use to interface with TEE */
-    esp_tee_app_config.s_entry_addr = &_sec_world_entry;
     esp_tee_app_config.s_int_handler = &_tee_s_intr_handler;
 }
 

components/esp_tee/subproject/main/soc/esp32c6/esp_tee_apm_prot_cfg.c

@@ -11,6 +11,7 @@
 #include "soc/soc.h"
 #include "soc/spi_mem_reg.h"
 #include "soc/efuse_reg.h"
+#include "soc/pcr_reg.h"
 
 extern void tee_apm_violation_isr(void *arg);
 
@@ -91,34 +92,41 @@ apm_ctrl_region_config_data_t hp_apm_pms_data[] = {
         .regn_pms        = 0x6,
         .filter_enable   = 1,
     },
-    /* Region 5: Peripherals [RSA - TEE Controller & APM] (RW) */
+    /* Region 5/6: Peripherals [RSA - TEE Controller & APM] (RW) */
-    /* Protected: APM, TEE Controller */
+    /* Protected: AES + SHA PCR, APM, TEE Controller */
     {
         .regn_num = 5,
         .regn_start_addr = DR_REG_RSA_BASE,
+        .regn_end_addr   = (PCR_AES_CONF_REG - 0x4),
+        .regn_pms        = 0x6,
+        .filter_enable   = 1,
+    },
+    {
+        .regn_num = 6,
+        .regn_start_addr = PCR_RSA_CONF_REG,
         .regn_end_addr   = (DR_REG_TEE_BASE - 0x4),
         .regn_pms        = 0x6,
         .filter_enable   = 1,
     },
-    /* Region 6: Peripherals [Miscellaneous - PMU] (RW) */
+    /* Region 7: Peripherals [Miscellaneous - PMU] (RW) */
     {
-        .regn_num = 6,
+        .regn_num = 7,
         .regn_start_addr = DR_REG_MISC_BASE,
         .regn_end_addr   = (DR_REG_PMU_BASE - 0x04),
         .regn_pms        = 0x6,
         .filter_enable   = 1,
     },
-    /* Region 7: Peripherals [DEBUG - PWDET] (RW) */
+    /* Region 8: Peripherals [DEBUG - PWDET] (RW) */
     {
-        .regn_num = 7,
+        .regn_num = 8,
         .regn_start_addr = DR_REG_OPT_DEBUG_BASE,
         .regn_end_addr   = 0x600D0000,
         .regn_pms        = 0x6,
         .filter_enable   = 1,
     },
-    /* Region 8: REE SRAM region (RW) */
+    /* Region 9: REE SRAM region (RW) */
     {
-        .regn_num = 8,
+        .regn_num = 9,
         .regn_start_addr = SOC_NS_IRAM_START,
         .regn_end_addr   = SOC_IRAM_HIGH,
         .regn_pms        = 0x6,
@@ -164,9 +172,9 @@ apm_ctrl_secure_mode_config_t hp_apm_sec_mode_data = {
 
 /* HP_APM: TEE mode accessible regions */
 apm_ctrl_region_config_data_t hp_apm_pms_data_tee[] = {
-    /* Region 9: Entire memory region (RWX)*/
+    /* Region 10: Entire memory region (RWX)*/
     {
-        .regn_num = 9,
+        .regn_num = 10,
         .regn_start_addr = 0x0,
         .regn_end_addr   = ~0x0,
         .regn_pms        = 0x7,
@@ -303,6 +311,9 @@ void esp_tee_configure_apm_protection(void)
     /* Disable all control filter first to have full access of address rage. */
     apm_hal_apm_ctrl_filter_enable_all(false);
 
+    /* Switch HP_CPU to TEE mode */
+    apm_tee_hal_set_master_secure_mode(HP_APM_CTRL, APM_LL_MASTER_HPCORE, APM_LL_SECURE_MODE_TEE);
+
     /* LP APM0 configuration. */
     lp_apm0_sec_mode_data.regn_count = sizeof(lp_apm0_pms_data) / sizeof(apm_ctrl_region_config_data_t);
     apm_hal_apm_ctrl_master_sec_mode_config(&lp_apm0_sec_mode_data);

components/esp_tee/subproject/main/soc/esp32c6/esp_tee_secure_sys_cfg.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,7 @@
 #include "esp_cpu.h"
 #include "esp_log.h"
 #include "hal/apm_hal.h"
+#include "hal/clk_gate_ll.h"
 
 #include "esp_tee.h"
 #include "esp_tee_intr.h"
@@ -91,13 +92,14 @@ void esp_tee_soc_secure_sys_init(void)
     esp_tee_protect_intr_src(ETS_EFUSE_INTR_SOURCE);        // eFuse
     esp_tee_protect_intr_src(ETS_AES_INTR_SOURCE);          // AES
     esp_tee_protect_intr_src(ETS_SHA_INTR_SOURCE);          // SHA
+
+    /* Disable AES/SHA peripheral clocks; they will be toggled as needed when the peripheral is in use */
+    periph_ll_disable_clk_set_rst(PERIPH_AES_MODULE);
+    periph_ll_disable_clk_set_rst(PERIPH_SHA_MODULE);
 }
 
 IRAM_ATTR inline void esp_tee_switch_to_ree(uint32_t ree_entry_addr)
 {
-    /* Switch HP_CPU to REE0 mode. */
-    apm_tee_hal_set_master_secure_mode(HP_APM_CTRL, APM_LL_MASTER_HPCORE, APM_LL_SECURE_MODE_REE0);
-
     /* 2nd argument is used as magic value to detect very first M2U switch */
     /* TBD: clean this up and use proper temporary register instead of a1 */
     /* Switch to non-secure world and launch App. */

components/esp_tee/test_apps/tee_test_fw/components/test_sec_srv/include/esp_tee_test.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,16 +10,17 @@ extern "C" {
 #endif
 
 #include <stdint.h>
+#include "esp_attr.h"
 
 #define TEE_TEST_INT_COUNT 3
 
-uint32_t __attribute__((__noinline__)) esp_tee_service_add(uint32_t a, uint32_t b);
+uint32_t NOINLINE_ATTR esp_tee_service_add(uint32_t a, uint32_t b);
 
-uint32_t __attribute__((__noinline__)) esp_tee_service_sub(uint32_t a, uint32_t b);
+uint32_t NOINLINE_ATTR esp_tee_service_sub(uint32_t a, uint32_t b);
 
-uint32_t __attribute__((__noinline__)) esp_tee_service_mul(uint32_t a, uint32_t b);
+uint32_t NOINLINE_ATTR esp_tee_service_mul(uint32_t a, uint32_t b);
 
-uint32_t __attribute__((__noinline__)) esp_tee_service_div(uint32_t a, uint32_t b);
+uint32_t NOINLINE_ATTR esp_tee_service_div(uint32_t a, uint32_t b);
 
 int esp_tee_secure_int_test(void);
 
@@ -33,7 +34,7 @@ int esp_tee_test_illegal_instr(void);
 
 int esp_tee_test_instr_fetch_prohibited(uint32_t type);
 
-void dummy_secure_service(void);
+void NOINLINE_ATTR dummy_secure_service(int a, int b, int c, int d, int e, int f, int g, int h, int *i);
 
 uint32_t add_in_loop(uint32_t a, uint32_t b, uint32_t iter);
 

components/esp_tee/test_apps/tee_test_fw/components/test_sec_srv/sec_srv_tbl_test.yml

@@ -64,7 +64,7 @@ secure_services:
       - id: 215
         type: custom
         function: dummy_secure_service
-        args: 0
+        args: 9
       - id: 216
         type: custom
         function: add_in_loop

components/esp_tee/test_apps/tee_test_fw/components/test_sec_srv/src/test_dummy_srv.c

@@ -7,8 +7,10 @@
 #include "esp_tee.h"
 #include "esp_err.h"
 #include "esp_rom_sys.h"
+#include "esp_attr.h"
 
-void _ss_dummy_secure_service(void)
+void NOINLINE_ATTR _ss_dummy_secure_service(int a, int b, int c, int d, int e, int f, int g, int h, int *i)
 {
     esp_rom_printf("Dummy secure service\n");
+    *i = a + b + c + d + e + f + g + h;
 }

components/esp_tee/test_apps/tee_test_fw/components/test_sec_srv/src/test_dummy_srv_wrapper.c

@@ -8,7 +8,7 @@
 #include "esp_tee.h"
 #include "esp_err.h"
 
-void dummy_secure_service(void)
+void dummy_secure_service(int a, int b, int c, int d, int e, int f, int g, int h, int *i)
 {
-    esp_tee_service_call(1, SS_DUMMY_SECURE_SERVICE);
+    esp_tee_service_call(10, SS_DUMMY_SECURE_SERVICE, a, b, c, d, e, f, g, h, i);
 }

components/esp_tee/test_apps/tee_test_fw/components/test_sec_srv/src/test_sec_srv.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,30 +7,30 @@
 #include "esp_log.h"
 #include "esp_tee.h"
 #include "esp_tee_test.h"
-
+#include "esp_attr.h"
 static const char *TAG = "test_sec_srv";
 
 /* Sample Trusted App */
 
-uint32_t __attribute__((__noinline__)) _ss_esp_tee_service_add(uint32_t a, uint32_t b)
+uint32_t NOINLINE_ATTR _ss_esp_tee_service_add(uint32_t a, uint32_t b)
 {
     ESP_LOGD(TAG, "SS: %s", __func__);
     return (a + b);
 }
 
-uint32_t __attribute__((__noinline__)) _ss_esp_tee_service_sub(uint32_t a, uint32_t b)
+uint32_t NOINLINE_ATTR _ss_esp_tee_service_sub(uint32_t a, uint32_t b)
 {
     ESP_LOGD(TAG, "SS: %s", __func__);
     return (a - b);
 }
 
-uint32_t __attribute__((__noinline__)) _ss_esp_tee_service_mul(uint32_t a, uint32_t b)
+uint32_t NOINLINE_ATTR _ss_esp_tee_service_mul(uint32_t a, uint32_t b)
 {
     ESP_LOGD(TAG, "SS: %s", __func__);
     return (a * b);
 }
 
-uint32_t __attribute__((__noinline__)) _ss_esp_tee_service_div(uint32_t a, uint32_t b)
+uint32_t NOINLINE_ATTR _ss_esp_tee_service_div(uint32_t a, uint32_t b)
 {
     ESP_LOGD(TAG, "SS: %s", __func__);
     return (a / b);

components/esp_tee/test_apps/tee_test_fw/main/test_esp_tee_ctx_switch.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -68,7 +68,9 @@ TEST_CASE("Test multiple calls to sample app (basic services)", "[basic]")
 
 TEST_CASE("Custom secure service call", "[basic]")
 {
-    dummy_secure_service();
+    int res = -1;
+    dummy_secure_service(1, 2, 3, 4, 5, 6, 7, 8, &res);
+    TEST_ASSERT_EQUAL_UINT32(36, res);
 }
 
 void test_task(void *pvParameters)

components/esptool_py/esptool/esptool.py

@@ -1,11 +1,10 @@
 #
-# SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
 #
 # SPDX-License-Identifier: Apache-2.0
 #
-
 import subprocess
 import sys
 
 if __name__ == '__main__':
-    sys.exit(subprocess.run([sys.executable, '-m', 'esptool'] + sys.argv[1:]).returncode)
+    sys.exit(subprocess.run([sys.executable, '-u', '-m', 'esptool'] + sys.argv[1:]).returncode)

components/hal/esp32h21/include/hal/gdma_ll.h

@@ -0,0 +1,586 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stddef.h> /* Required for NULL constant */
+#include <stdint.h>
+#include <stdbool.h>
+#include "hal/gdma_types.h"
+#include "soc/gdma_struct.h"
+#include "soc/gdma_reg.h"
+#include "soc/soc_etm_source.h"
+#include "soc/pcr_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define GDMA_LL_GET_HW(id) (((id) == 0) ? (&GDMA) : NULL)
+
+#define GDMA_LL_CHANNEL_MAX_PRIORITY 5 // supported priority levels: [0,5]
+
+#define GDMA_LL_RX_EVENT_MASK       (0x7F)
+#define GDMA_LL_TX_EVENT_MASK       (0x3F)
+
+// any "dummy" peripheral ID can be used for M2M mode
+#define GDMA_LL_M2M_FREE_PERIPH_ID_MASK (0xFC32)
+#define GDMA_LL_INVALID_PERIPH_ID       (0x3F)
+
+#define GDMA_LL_EVENT_TX_FIFO_UDF   (1<<5)
+#define GDMA_LL_EVENT_TX_FIFO_OVF   (1<<4)
+#define GDMA_LL_EVENT_RX_FIFO_UDF   (1<<6)
+#define GDMA_LL_EVENT_RX_FIFO_OVF   (1<<5)
+#define GDMA_LL_EVENT_TX_TOTAL_EOF  (1<<3)
+#define GDMA_LL_EVENT_RX_DESC_EMPTY (1<<4)
+#define GDMA_LL_EVENT_TX_DESC_ERROR (1<<2)
+#define GDMA_LL_EVENT_RX_DESC_ERROR (1<<3)
+#define GDMA_LL_EVENT_TX_EOF        (1<<1)
+#define GDMA_LL_EVENT_TX_DONE       (1<<0)
+#define GDMA_LL_EVENT_RX_ERR_EOF    (1<<2)
+#define GDMA_LL_EVENT_RX_SUC_EOF    (1<<1)
+#define GDMA_LL_EVENT_RX_DONE       (1<<0)
+
+#define GDMA_LL_AHB_GROUP_START_ID    0 // AHB GDMA group ID starts from 0
+#define GDMA_LL_AHB_NUM_GROUPS        1 // Number of AHB GDMA groups
+#define GDMA_LL_AHB_PAIRS_PER_GROUP   3 // Number of GDMA pairs in each AHB group
+
+#define GDMA_LL_AHB_DESC_ALIGNMENT    4
+#define GDMA_LL_AHB_RX_BURST_NEEDS_ALIGNMENT  1
+
+#define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event)                                     \
+    (uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{                                                \
+                                              [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH0, \
+                                          },                                               \
+                                          {                                                \
+                                              [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH1, \
+                                          },                                               \
+                                          {                                                \
+                                              [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH2, \
+                                          }}}[group][chan][event]
+
+#define GDMA_LL_RX_ETM_EVENT_TABLE(group, chan, event)                                        \
+    (uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{                                                   \
+                                              [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH0, \
+                                          },                                                  \
+                                          {                                                   \
+                                              [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH1, \
+                                          },                                                  \
+                                          {                                                   \
+                                              [GDMA_ETM_EVENT_EOF] = GDMA_EVT_IN_SUC_EOF_CH2, \
+                                          }}}[group][chan][event]
+
+#define GDMA_LL_TX_ETM_TASK_TABLE(group, chan, task)                                          \
+    (uint32_t[1][3][GDMA_ETM_TASK_MAX]){{{                                                    \
+                                             [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH0, \
+                                         },                                                   \
+                                         {                                                    \
+                                             [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH1, \
+                                         },                                                   \
+                                         {                                                    \
+                                             [GDMA_ETM_TASK_START] = GDMA_TASK_OUT_START_CH2, \
+                                         }}}[group][chan][task]
+
+#define GDMA_LL_RX_ETM_TASK_TABLE(group, chan, task)                                         \
+    (uint32_t[1][3][GDMA_ETM_TASK_MAX]){{{                                                   \
+                                             [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH0, \
+                                         },                                                  \
+                                         {                                                   \
+                                             [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH1, \
+                                         },                                                  \
+                                         {                                                   \
+                                             [GDMA_ETM_TASK_START] = GDMA_TASK_IN_START_CH2, \
+                                         }}}[group][chan][task]
+
+///////////////////////////////////// Common /////////////////////////////////////////
+
+/**
+ * @brief Enable the bus clock for the DMA module
+ */
+static inline void _gdma_ll_enable_bus_clock(int group_id, bool enable)
+{
+    (void)group_id;
+    PCR.gdma_conf.gdma_clk_en = enable;
+}
+
+#define gdma_ll_enable_bus_clock(...) _gdma_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset the DMA module
+ */
+static inline void _gdma_ll_reset_register(int group_id)
+{
+    (void)group_id;
+    PCR.gdma_conf.gdma_rst_en = 1;
+    PCR.gdma_conf.gdma_rst_en = 0;
+}
+
+#define gdma_ll_reset_register(...) _gdma_ll_reset_register(__VA_ARGS__)
+
+/**
+ * @brief Force enable register clock
+ */
+static inline void gdma_ll_force_enable_reg_clock(gdma_dev_t *dev, bool enable)
+{
+    dev->misc_conf.clk_en = enable;
+}
+
+///////////////////////////////////// RX /////////////////////////////////////////
+/**
+ * @brief Get DMA RX channel interrupt status word
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_rx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
+{
+    if (raw) {
+        return dev->in_intr[channel].raw.val;
+    } else {
+        return dev->in_intr[channel].st.val;
+    }
+}
+
+/**
+ * @brief Enable DMA RX channel interrupt
+ */
+static inline void gdma_ll_rx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
+{
+    if (enable) {
+        dev->in_intr[channel].ena.val |= mask;
+    } else {
+        dev->in_intr[channel].ena.val &= ~mask;
+    }
+}
+
+/**
+ * @brief Clear DMA RX channel interrupt
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
+{
+    dev->in_intr[channel].clr.val = mask;
+}
+
+/**
+ * @brief Get DMA RX channel interrupt status register address
+ */
+static inline volatile void *gdma_ll_rx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
+{
+    return (volatile void *)(&dev->in_intr[channel].st);
+}
+
+/**
+ * @brief Enable DMA RX channel to check the owner bit in the descriptor, disabled by default
+ */
+static inline void gdma_ll_rx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf1.in_check_owner_chn = enable;
+}
+
+/**
+ * @brief Enable DMA RX channel burst reading data, disabled by default
+ */
+static inline void gdma_ll_rx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf0.in_data_burst_en_chn = enable;
+}
+
+/**
+ * @brief Enable DMA RX channel burst reading descriptor link, disabled by default
+ */
+static inline void gdma_ll_rx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf0.indscr_burst_en_chn = enable;
+}
+
+/**
+ * @brief Reset DMA RX channel FSM and FIFO pointer
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_reset_channel(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_conf0.in_rst_chn = 1;
+    dev->channel[channel].in.in_conf0.in_rst_chn = 0;
+}
+
+/**
+ * @brief Check if DMA RX FIFO is full
+ * @param fifo_level only supports level 1
+ */
+static inline bool gdma_ll_rx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].in.infifo_status.val & 0x01;
+}
+
+/**
+ * @brief Check if DMA RX FIFO is empty
+ * @param fifo_level only supports level 1
+ */
+static inline bool gdma_ll_rx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].in.infifo_status.val & 0x02;
+}
+
+/**
+ * @brief Get number of bytes in RX FIFO
+ * @param fifo_level only supports level 1
+ */
+static inline uint32_t gdma_ll_rx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].in.infifo_status.infifo_cnt_chn;
+}
+
+/**
+ * @brief Pop data from DMA RX FIFO
+ */
+static inline uint32_t gdma_ll_rx_pop_data(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_pop.infifo_pop_chn = 1;
+    return dev->channel[channel].in.in_pop.infifo_rdata_chn;
+}
+
+/**
+ * @brief Set the descriptor link base address for RX channel
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
+{
+    dev->channel[channel].in.in_link.inlink_addr_chn = addr;
+}
+
+/**
+ * @brief Start dealing with RX descriptors
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_start(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_link.inlink_start_chn = 1;
+}
+
+/**
+ * @brief Stop dealing with RX descriptors
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_stop(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_link.inlink_stop_chn = 1;
+}
+
+/**
+ * @brief Restart a new inlink right after the last descriptor
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_rx_restart(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_link.inlink_restart_chn = 1;
+}
+
+/**
+ * @brief Enable DMA RX to return the address of current descriptor when receives error
+ */
+static inline void gdma_ll_rx_enable_auto_return(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_link.inlink_auto_ret_chn = enable;
+}
+
+/**
+ * @brief Check if DMA RX descriptor FSM is in IDLE state
+ */
+static inline bool gdma_ll_rx_is_desc_fsm_idle(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_link.inlink_park_chn;
+}
+
+/**
+ * @brief Get RX success EOF descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_rx_get_success_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_suc_eof_des_addr.val;
+}
+
+/**
+ * @brief Get RX error EOF descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_rx_get_error_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_err_eof_des_addr.val;
+}
+
+/**
+ * @brief Get the pre-fetched RX descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_rx_get_prefetched_desc_addr(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].in.in_dscr.val;
+}
+
+/**
+ * @brief Set priority for DMA RX channel
+ */
+static inline void gdma_ll_rx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
+{
+    dev->channel[channel].in.in_pri.rx_pri_chn = prio;
+}
+
+/**
+ * @brief Connect DMA RX channel to a given peripheral
+ */
+static inline void gdma_ll_rx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
+{
+    dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = periph_id;
+    dev->channel[channel].in.in_conf0.mem_trans_en_chn = (periph == GDMA_TRIG_PERIPH_M2M);
+}
+
+/**
+ * @brief Disconnect DMA RX channel from peripheral
+ */
+static inline void gdma_ll_rx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].in.in_peri_sel.peri_in_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
+    dev->channel[channel].in.in_conf0.mem_trans_en_chn = false;
+}
+
+/**
+ * @brief Whether to enable the ETM subsystem for RX channel
+ *
+ * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
+ */
+static inline void gdma_ll_rx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].in.in_conf0.in_etm_en_chn = enable;
+}
+
+///////////////////////////////////// TX /////////////////////////////////////////
+/**
+ * @brief Get DMA TX channel interrupt status word
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_tx_get_interrupt_status(gdma_dev_t *dev, uint32_t channel, bool raw)
+{
+    if (raw) {
+        return dev->out_intr[channel].raw.val;
+    } else {
+        return dev->out_intr[channel].st.val;
+    }
+}
+
+/**
+ * @brief Enable DMA TX channel interrupt
+ */
+static inline void gdma_ll_tx_enable_interrupt(gdma_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
+{
+    if (enable) {
+        dev->out_intr[channel].ena.val |= mask;
+    } else {
+        dev->out_intr[channel].ena.val &= ~mask;
+    }
+}
+
+/**
+ * @brief Clear DMA TX channel interrupt
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_clear_interrupt_status(gdma_dev_t *dev, uint32_t channel, uint32_t mask)
+{
+    dev->out_intr[channel].clr.val = mask;
+}
+
+/**
+ * @brief Get DMA TX channel interrupt status register address
+ */
+static inline volatile void *gdma_ll_tx_get_interrupt_status_reg(gdma_dev_t *dev, uint32_t channel)
+{
+    return (volatile void *)(&dev->out_intr[channel].st);
+}
+
+/**
+ * @brief Enable DMA TX channel to check the owner bit in the descriptor, disabled by default
+ */
+static inline void gdma_ll_tx_enable_owner_check(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf1.out_check_owner_chn = enable;
+}
+
+/**
+ * @brief Enable DMA TX channel burst sending data, disabled by default
+ */
+static inline void gdma_ll_tx_enable_data_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf0.out_data_burst_en_chn = enable;
+}
+
+/**
+ * @brief Enable DMA TX channel burst reading descriptor link, disabled by default
+ */
+static inline void gdma_ll_tx_enable_descriptor_burst(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf0.outdscr_burst_en_chn = enable;
+}
+
+/**
+ * @brief Set TX channel EOF mode
+ */
+static inline void gdma_ll_tx_set_eof_mode(gdma_dev_t *dev, uint32_t channel, uint32_t mode)
+{
+    dev->channel[channel].out.out_conf0.out_eof_mode_chn = mode;
+}
+
+/**
+ * @brief Enable DMA TX channel automatic write results back to descriptor after all data has been sent out, disabled by default
+ */
+static inline void gdma_ll_tx_enable_auto_write_back(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf0.out_auto_wrback_chn = enable;
+}
+
+/**
+ * @brief Reset DMA TX channel FSM and FIFO pointer
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_reset_channel(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_conf0.out_rst_chn = 1;
+    dev->channel[channel].out.out_conf0.out_rst_chn = 0;
+}
+
+/**
+ * @brief Check if DMA TX FIFO is full
+ * @param fifo_level only supports level 1
+ */
+static inline bool gdma_ll_tx_is_fifo_full(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].out.outfifo_status.val & 0x01;
+}
+
+/**
+ * @brief Check if DMA TX FIFO is empty
+ * @param fifo_level only supports level 1
+ */
+static inline bool gdma_ll_tx_is_fifo_empty(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].out.outfifo_status.val & 0x02;
+}
+
+/**
+ * @brief Get number of bytes in TX FIFO
+ * @param fifo_level only supports level 1
+ */
+static inline uint32_t gdma_ll_tx_get_fifo_bytes(gdma_dev_t *dev, uint32_t channel, uint32_t fifo_level)
+{
+    return dev->channel[channel].out.outfifo_status.outfifo_cnt_chn;
+}
+
+/**
+ * @brief Push data into DMA TX FIFO
+ */
+static inline void gdma_ll_tx_push_data(gdma_dev_t *dev, uint32_t channel, uint32_t data)
+{
+    dev->channel[channel].out.out_push.outfifo_wdata_chn = data;
+    dev->channel[channel].out.out_push.outfifo_push_chn = 1;
+}
+
+/**
+ * @brief Set the descriptor link base address for TX channel
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_set_desc_addr(gdma_dev_t *dev, uint32_t channel, uint32_t addr)
+{
+    dev->channel[channel].out.out_link.outlink_addr_chn = addr;
+}
+
+/**
+ * @brief Start dealing with TX descriptors
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_start(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_link.outlink_start_chn = 1;
+}
+
+/**
+ * @brief Stop dealing with TX descriptors
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_stop(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_link.outlink_stop_chn = 1;
+}
+
+/**
+ * @brief Restart a new outlink right after the last descriptor
+ */
+__attribute__((always_inline))
+static inline void gdma_ll_tx_restart(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_link.outlink_restart_chn = 1;
+}
+
+/**
+ * @brief Check if DMA TX descriptor FSM is in IDLE state
+ */
+static inline bool gdma_ll_tx_is_desc_fsm_idle(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].out.out_link.outlink_park_chn;
+}
+
+/**
+ * @brief Get TX EOF descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_tx_get_eof_desc_addr(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].out.out_eof_des_addr.val;
+}
+
+/**
+ * @brief Get the pre-fetched TX descriptor's address
+ */
+__attribute__((always_inline))
+static inline uint32_t gdma_ll_tx_get_prefetched_desc_addr(gdma_dev_t *dev, uint32_t channel)
+{
+    return dev->channel[channel].out.out_dscr.val;
+}
+
+/**
+ * @brief Set priority for DMA TX channel
+ */
+static inline void gdma_ll_tx_set_priority(gdma_dev_t *dev, uint32_t channel, uint32_t prio)
+{
+    dev->channel[channel].out.out_pri.tx_pri_chn = prio;
+}
+
+/**
+ * @brief Connect DMA TX channel to a given peripheral
+ */
+static inline void gdma_ll_tx_connect_to_periph(gdma_dev_t *dev, uint32_t channel, gdma_trigger_peripheral_t periph, int periph_id)
+{
+    (void)periph;
+    dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = periph_id;
+}
+
+/**
+ * @brief Disconnect DMA TX channel from peripheral
+ */
+static inline void gdma_ll_tx_disconnect_from_periph(gdma_dev_t *dev, uint32_t channel)
+{
+    dev->channel[channel].out.out_peri_sel.peri_out_sel_chn = GDMA_LL_INVALID_PERIPH_ID;
+}
+
+/**
+ * @brief Whether to enable the ETM subsystem for TX channel
+ *
+ * @note When ETM_EN is 1, only ETM tasks can be used to configure the transfer direction and enable the channel.
+ */
+static inline void gdma_ll_tx_enable_etm_task(gdma_dev_t *dev, uint32_t channel, bool enable)
+{
+    dev->channel[channel].out.out_conf0.out_etm_en_chn = enable;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h21/include/hal/lp_clkrst_ll.h

@@ -0,0 +1,74 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for ESP32-H21 LP CLKRST & LP PERI register operations
+
+#pragma once
+
+#include <stdbool.h>
+#include <stdlib.h>
+#include "soc/soc.h"
+#include "soc/lp_clkrst_struct.h"
+#include "soc/lpperi_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(lp_clkrst_dev_t *hw, bool en)
+{
+    hw->lpperi.clkrst_lp_sel_osc_slow = en;
+}
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(lp_clkrst_dev_t *hw, bool en)
+{
+    hw->lpperi.clkrst_lp_sel_osc_fast = en;
+}
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(lp_clkrst_dev_t *hw, bool en)
+{
+    hw->lpperi.clkrst_lp_sel_xtal = en;
+}
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(lp_clkrst_dev_t *hw, bool en)
+{
+    hw->lpperi.clkrst_lp_sel_xtal32k = en;
+}
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_set_ble_rtc_timer_divisor_value(lp_clkrst_dev_t *hw, uint32_t value)
+{
+    hw->lpperi.clkrst_lp_bletimer_div_num = value;
+}
+
+__attribute__((always_inline))
+static inline uint32_t lp_clkrst_ll_get_ble_rtc_timer_divisor_value(lp_clkrst_dev_t *hw)
+{
+    return hw->lpperi.clkrst_lp_bletimer_div_num;
+}
+
+__attribute__((always_inline))
+static inline void lp_clkrst_ll_select_modem_32k_clock_source(lp_clkrst_dev_t *hw, uint32_t src)
+{
+    hw->lpperi.clkrst_lp_bletimer_32k_sel = src;
+}
+
+__attribute__((always_inline))
+static inline void _lp_clkrst_ll_enable_rng_clock(bool en)
+{
+    LPPERI.clk_en.rng_ck_en = en;
+}
+
+/// LPPERI.clk_en is a shared register, so this function must be used in an atomic way
+#define lp_clkrst_ll_enable_rng_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _lp_clkrst_ll_enable_rng_clock(__VA_ARGS__)
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h21/include/hal/modem_lpcon_ll.h

@@ -0,0 +1,110 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for ESP32-H21 MODEM LPCON register operations
+
+#pragma once
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include "soc/soc.h"
+#include "hal/assert.h"
+#include "modem/modem_lpcon_struct.h"
+#include "hal/modem_clock_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_test_clk(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->test_conf.clk_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_lpclk_slow_osc(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_slow = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_lpclk_fast_osc(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->coex_lp_clk_conf.clk_coex_lp_sel_osc_fast = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_lpclk_main_xtal(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_lpclk_32k_xtal(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->coex_lp_clk_conf.clk_coex_lp_sel_xtal32k = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_set_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw, uint32_t value)
+{
+    hw->coex_lp_clk_conf.clk_coex_lp_div_num = value;
+}
+
+__attribute__((always_inline))
+static inline uint32_t modem_lpcon_ll_get_coex_lpclk_divisor_value(modem_lpcon_dev_t *hw)
+{
+    return hw->coex_lp_clk_conf.clk_coex_lp_div_num;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_clock(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_coex_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_fe_mem_clock(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_fe_mem_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_coex_force_clock(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->clk_conf_force_on.clk_coex_fo = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_enable_fe_mem_force_clock(modem_lpcon_dev_t *hw, bool en)
+{
+    hw->clk_conf_force_on.clk_fe_mem_fo = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_reset_coex(modem_lpcon_dev_t *hw)
+{
+    hw->rst_conf.rst_coex = 1;
+    hw->rst_conf.rst_coex = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_lpcon_ll_reset_all(modem_lpcon_dev_t *hw)
+{
+    hw->rst_conf.val = 0xf;
+    hw->rst_conf.val = 0;
+}
+
+__attribute__((always_inline))
+static inline uint32_t modem_lpcon_ll_get_date(modem_lpcon_dev_t *hw)
+{
+    return hw->date.val;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h21/include/hal/modem_syscon_ll.h

@@ -0,0 +1,275 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The LL layer for ESP32-H21 MODEM SYSCON register operations
+
+#pragma once
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include "soc/soc.h"
+#include "hal/assert.h"
+#include "modem/modem_syscon_struct.h"
+#include "hal/modem_clock_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_test_clk(modem_syscon_dev_t *hw, bool en)
+{
+    hw->test_conf.clk_en = en;
+}
+
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_data_dump_mux_clock(modem_syscon_dev_t *hw, bool en)
+{
+    // ESP32-H21 Not Support
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_etm_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_etm_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_ieee802154_apb_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_zb_apb_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_ieee802154_mac_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_zb_mac_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_modem_sec_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_modem_sec_en = en;
+    hw->clk_conf.clk_modem_sec_ecb_en = en;
+    hw->clk_conf.clk_modem_sec_ccm_en = en;
+    hw->clk_conf.clk_modem_sec_bah_en = en;
+    hw->clk_conf.clk_modem_sec_apb_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_ble_timer_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_ble_timer_apb_en = en;
+    hw->clk_conf.clk_ble_timer_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_data_dump_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf.clk_data_dump_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_etm_force_clock(modem_syscon_dev_t *hw)
+{
+    hw->clk_conf_force_on.clk_etm_fo = 1;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_modem_sec_force_clock(modem_syscon_dev_t *hw)
+{
+    hw->clk_conf_force_on.clk_modem_sec_fo = 1;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_ble_timer_force_clock(modem_syscon_dev_t *hw)
+{
+    hw->clk_conf_force_on.clk_ble_timer_fo = 1;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_data_dump_force_clock(modem_syscon_dev_t *hw)
+{
+    hw->clk_conf_force_on.clk_data_dump_fo = 1;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_fe(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_fe = 1;
+    hw->modem_rst_conf.rst_fe = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_btmac_apb(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_btmac_apb = 1;
+    hw->modem_rst_conf.rst_btmac_apb = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_btmac(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_btmac = 1;
+    hw->modem_rst_conf.rst_btmac = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_btbb_apb(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_btbb_apb = 1;
+    hw->modem_rst_conf.rst_btbb_apb = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_btbb(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_btbb = 1;
+    hw->modem_rst_conf.rst_btbb = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_etm(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_etm = 1;
+    hw->modem_rst_conf.rst_etm = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_zbmac(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_zbmac = 1;
+    hw->modem_rst_conf.rst_zbmac = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_zbmac_apb(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_zbmac_apb = 1;
+    hw->modem_rst_conf.rst_zbmac_apb = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_modem_sec(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_modem_ecb = 1;
+    hw->modem_rst_conf.rst_modem_ccm = 1;
+    hw->modem_rst_conf.rst_modem_bah = 1;
+    hw->modem_rst_conf.rst_modem_sec = 1;
+    hw->modem_rst_conf.rst_modem_ecb = 0;
+    hw->modem_rst_conf.rst_modem_ccm = 0;
+    hw->modem_rst_conf.rst_modem_bah = 0;
+    hw->modem_rst_conf.rst_modem_sec = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_ble_timer(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_ble_timer = 1;
+    hw->modem_rst_conf.rst_ble_timer = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_data_dump(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.rst_data_dump = 1;
+    hw->modem_rst_conf.rst_data_dump = 0;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_reset_all(modem_syscon_dev_t *hw)
+{
+    hw->modem_rst_conf.val = 0xffffffff;
+    hw->modem_rst_conf.val = 0;
+}
+
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_clk_conf1_configure(modem_syscon_dev_t *hw, bool en, uint32_t mask)
+{
+    if(en){
+        hw->clk_conf1.val = hw->clk_conf1.val | mask;
+    } else {
+        hw->clk_conf1.val = hw->clk_conf1.val & ~mask;
+    }
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_txlogain_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_txlogain_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_16m_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_16m_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_32m_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_32m_en = en;
+}
+
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_sdm_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_sdm_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_adc_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_adc_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_apb_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_fe_apb_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_bt_apb_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_bt_apb_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_bt_mac_clock(modem_syscon_dev_t *hw, bool en)
+{
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_bt_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1.clk_bt_en = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_fe_force_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1_force_on.clk_fe_fo = en;
+}
+
+__attribute__((always_inline))
+static inline void modem_syscon_ll_enable_bt_force_clock(modem_syscon_dev_t *hw, bool en)
+{
+    hw->clk_conf1_force_on.clk_bt_fo = en;
+}
+
+__attribute__((always_inline))
+static inline uint32_t modem_syscon_ll_get_date(modem_syscon_dev_t *hw)
+{
+    return hw->date.val;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h21/modem_clock_hal.c

@@ -0,0 +1,125 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// The HAL layer for MODEM CLOCK (ESP32-H21 specific part)
+#include <stdbool.h>
+#include "esp_attr.h"
+#include "soc/soc.h"
+#include "hal/modem_clock_hal.h"
+#include "hal/lp_clkrst_ll.h"
+#include "hal/modem_clock_types.h"
+#include "hal/assert.h"
+
+typedef enum {
+    MODEM_CLOCK_XTAL32K_CODE = 0,
+    MODEM_CLOCK_RC32K_CODE   = 1,
+    MODEM_CLOCK_EXT32K_CODE  = 2
+} modem_clock_32k_clk_src_code_t;
+
+void IRAM_ATTR modem_clock_hal_enable_modem_common_fe_clock(modem_clock_hal_context_t *hal, bool enable)
+{
+    modem_syscon_ll_enable_fe_apb_clock(hal->syscon_dev, enable);
+    modem_syscon_ll_enable_fe_32m_clock(hal->syscon_dev, enable);
+}
+
+void IRAM_ATTR modem_clock_hal_enable_modem_private_fe_clock(modem_clock_hal_context_t *hal, bool enable)
+{
+    modem_lpcon_ll_enable_fe_mem_clock(hal->lpcon_dev, enable);
+    modem_syscon_ll_enable_fe_sdm_clock(hal->syscon_dev, enable);
+    modem_syscon_ll_enable_fe_adc_clock(hal->syscon_dev, enable);
+    modem_syscon_ll_enable_fe_txlogain_clock(hal->syscon_dev, enable);
+    modem_syscon_ll_enable_fe_16m_clock(hal->syscon_dev, enable);
+}
+
+void modem_clock_hal_set_ble_rtc_timer_divisor_value(modem_clock_hal_context_t *hal, uint32_t divider)
+{
+    lp_clkrst_ll_set_ble_rtc_timer_divisor_value(&LP_CLKRST, divider);
+}
+
+void modem_clock_hal_enable_ble_rtc_timer_clock(modem_clock_hal_context_t *hal, bool enable)
+{
+    // BLE RTC Timer has bees moved to LP_AON domain, No clock gate on ESP32-H21
+}
+
+void modem_clock_hal_deselect_all_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal)
+{
+    lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, false);
+    lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(&LP_CLKRST, false);
+    lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(&LP_CLKRST, false);
+    lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, false);
+}
+
+void modem_clock_hal_select_ble_rtc_timer_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src)
+{
+    HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX);
+
+    switch (src)
+    {
+    case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
+        lp_clkrst_ll_enable_ble_rtc_timer_slow_osc(&LP_CLKRST, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_RC_FAST:
+        lp_clkrst_ll_enable_ble_rtc_timer_fast_osc(&LP_CLKRST, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
+        lp_clkrst_ll_enable_ble_rtc_timer_main_xtal(&LP_CLKRST, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_RC32K:
+        lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
+        lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_EXT32K:
+        lp_clkrst_ll_enable_ble_rtc_timer_32k_xtal(&LP_CLKRST, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
+        break;
+    default:
+        HAL_ASSERT(0);
+    }
+}
+
+void modem_clock_hal_deselect_all_coex_lpclk_source(modem_clock_hal_context_t *hal)
+{
+    modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, false);
+    modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, false);
+    modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, false);
+    modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, false);
+}
+
+void modem_clock_hal_select_coex_lpclk_source(modem_clock_hal_context_t *hal, modem_clock_lpclk_src_t src)
+{
+    HAL_ASSERT(src < MODEM_CLOCK_LPCLK_SRC_MAX);
+
+    switch (src)
+    {
+    case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
+        modem_lpcon_ll_enable_coex_lpclk_slow_osc(hal->lpcon_dev, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_RC_FAST:
+        modem_lpcon_ll_enable_coex_lpclk_fast_osc(hal->lpcon_dev, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
+        modem_lpcon_ll_enable_coex_lpclk_main_xtal(hal->lpcon_dev, true);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_RC32K:
+        modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_RC32K_CODE);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
+        modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_XTAL32K_CODE);
+        break;
+    case MODEM_CLOCK_LPCLK_SRC_EXT32K:
+        modem_lpcon_ll_enable_coex_lpclk_32k_xtal(hal->lpcon_dev, true);
+        lp_clkrst_ll_select_modem_32k_clock_source(&LP_CLKRST, MODEM_CLOCK_EXT32K_CODE);
+        break;
+    default:
+        HAL_ASSERT(0);
+    }
+}

components/hal/esp32p4/include/hal/usb_dwc_ll.h

@@ -362,7 +362,7 @@ static inline unsigned usb_dwc_ll_ghwcfg_get_hsphy_type(usb_dwc_dev_t *hw)
 
 static inline unsigned usb_dwc_ll_ghwcfg_get_channel_num(usb_dwc_dev_t *hw)
 {
-    return hw->ghwcfg2_reg.numhstchnl;
+    return hw->ghwcfg2_reg.numhstchnl + 1;
 }
 
 // --------------------------- HPTXFSIZ Register -------------------------------

components/hal/esp32s2/include/hal/usb_dwc_ll.h

@@ -361,7 +361,7 @@ static inline unsigned usb_dwc_ll_ghwcfg_get_hsphy_type(usb_dwc_dev_t *hw)
 
 static inline unsigned usb_dwc_ll_ghwcfg_get_channel_num(usb_dwc_dev_t *hw)
 {
-    return hw->ghwcfg2_reg.numhstchnl;
+    return hw->ghwcfg2_reg.numhstchnl + 1;
 }
 
 // --------------------------- HPTXFSIZ Register -------------------------------

components/hal/esp32s3/include/hal/usb_dwc_ll.h

@@ -361,7 +361,7 @@ static inline unsigned usb_dwc_ll_ghwcfg_get_hsphy_type(usb_dwc_dev_t *hw)
 
 static inline unsigned usb_dwc_ll_ghwcfg_get_channel_num(usb_dwc_dev_t *hw)
 {
-    return hw->ghwcfg2_reg.numhstchnl;
+    return hw->ghwcfg2_reg.numhstchnl + 1;
 }
 
 // --------------------------- HPTXFSIZ Register -------------------------------

components/hal/include/hal/apm_hal.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -250,7 +250,17 @@ int apm_hal_apm_ctrl_get_int_src_num(apm_ctrl_path_t *apm_path);
 
 #endif //CONFIG_IDF_TARGET_ESP32P4
 
-#endif //SOC_APM_SUPPORTED
+#elif SOC_APM_CTRL_FILTER_SUPPORTED //!SOC_APM_SUPPORTED
+#include "soc/hp_apm_reg.h"
+#include "soc/lp_apm_reg.h"
+#include "soc/lp_apm0_reg.h"
+
+#define apm_hal_apm_ctrl_filter_enable_all(en) \
+    REG_WRITE(LP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); \
+    REG_WRITE(LP_APM0_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0); \
+    REG_WRITE(HP_APM_FUNC_CTRL_REG, en ? 0xFFFFFFFF : 0);
+
+#endif
 
 #ifdef __cplusplus
 }