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esp-idf/components/efuse/esp32c5/esp_efuse_table.csv
Konstantin Kondrashov 7397c159cb feat(efuse): Adds efuse ADC calib data for ESP32-C5
2024-11-01 23:08:53 +08:00

26 KiB
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1# field_name, | efuse_block, | bit_start, | bit_count, |comment #
2# | (EFUSE_BLK0 | (0..255) | (1-256) | #
3# | EFUSE_BLK1 | | | #
4# | ...) | | | #
5##########################################################################
6# !!!!!!!!!!! #
7# this will generate new source files, next rebuild all the sources.
8# !!!!!!!!!!! #
9# This file was generated by regtools.py based on the efuses.yaml file with the version: 287a0ed4951aba84b9571a5f31000275
10WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
11WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
12WR_DIS.KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DISABLE_DEPLOY_MODE
13WR_DIS.KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_RND_SWITCH_CYCLE
14WR_DIS.KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DEPLOY_ONLY_ONCE
15WR_DIS.FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_USE_KEY_MANAGER_KEY
16WR_DIS.FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_DISABLE_SW_INIT_KEY
17WR_DIS.KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 1, 1, [] wr_dis of KM_XTS_KEY_LENGTH_256
18WR_DIS.LOCK_KM_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of LOCK_KM_KEY
19WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
20WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG
21WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD
22WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
23WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_TWAI
24WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE
25WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG
26WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
27WR_DIS.HYS_EN_PAD, EFUSE_BLK0, 2, 1, [] wr_dis of HYS_EN_PAD
28WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL
29WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
30WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
31WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
32WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
33WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
34WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
35WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
36WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
37WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
38WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
39WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL
40WR_DIS.XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL
41WR_DIS.XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_CLK_ENABLE
42WR_DIS.ECDSA_DISABLE_P192, EFUSE_BLK0, 14, 1, [] wr_dis of ECDSA_DISABLE_P192
43WR_DIS.ECC_FORCE_CONST_TIME, EFUSE_BLK0, 14, 1, [] wr_dis of ECC_FORCE_CONST_TIME
44WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
45WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
46WR_DIS.XTAL_48M_SEL, EFUSE_BLK0, 17, 1, [] wr_dis of XTAL_48M_SEL
47WR_DIS.XTAL_48M_SEL_MODE, EFUSE_BLK0, 17, 1, [] wr_dis of XTAL_48M_SEL_MODE
48WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
49WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE
50WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT
51WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
52WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
53WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
54WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL
55WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME
56WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION
57WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE
58WR_DIS.HUK_GEN_STATE, EFUSE_BLK0, 19, 1, [] wr_dis of HUK_GEN_STATE
59WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1
60WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
61WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT
62WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR
63WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR
64WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
65WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
66WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
67WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR
68WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP
69WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR
70WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP
71WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR
72WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP
73WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
74WR_DIS.PA_TRIM_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PA_TRIM_VERSION
75WR_DIS.TRIM_N_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of TRIM_N_BIAS
76WR_DIS.TRIM_P_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of TRIM_P_BIAS
77WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
78WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS
79WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS
80WR_DIS.LSLP_HP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBG
81WR_DIS.LSLP_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBIAS
82WR_DIS.DSLP_LP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBG
83WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS
84WR_DIS.LP_HP_DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of LP_HP_DBIAS_VOL_GAP
85WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
86WR_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 21, 1, [] wr_dis of TEMPERATURE_SENSOR
87WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
88WR_DIS.ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
89WR_DIS.ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
90WR_DIS.ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
91WR_DIS.ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
92WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
93WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
94WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
95WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
96WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
97WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
98WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
99WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
100WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
101WR_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
102WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
103WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
104WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
105WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
106WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
107WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
108WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
109WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
110WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
111WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS
112WR_DIS.VDD_SPI_AS_GPIO, EFUSE_BLK0, 30, 1, [] wr_dis of VDD_SPI_AS_GPIO
113WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG
114RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10
115RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
116RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
117RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
118RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
119RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
120RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
121RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
122DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Represents whether icache is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
123DIS_USB_JTAG, EFUSE_BLK0, 41, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
124DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
125SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
126DIS_TWAI, EFUSE_BLK0, 46, 1, [] Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
127JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
128SOFT_DIS_JTAG, EFUSE_BLK0, 48, 3, [] Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even number: enabled\\
129DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ 0: enabled\\
130DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode).\\ 1: disabled\\ 0: enabled\\
131USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Represents whether the D+ and D- pins is exchanged.\\ 1: exchanged\\ 0: not exchanged\\
132VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Represents whether vdd spi pin is functioned as gpio.\\ 1: functioned\\ 0: not functioned\\
133KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 64, 4, [] Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled \\ 0: enabled.\\
134KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 68, 2, [] Set the bits to control key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles
135KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 70, 4, [] Set each bit to control whether corresponding key can only be deployed once. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds
136FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 74, 4, [] Set each bit to control whether corresponding key must come from key manager. 1 is true; 0 is false. bit 0: ecsda; bit 1: xts; bit2: hmac; bit3: ds
137FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 78, 1, [] Set this bit to disable software written init key; and force use efuse_init_key
138WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] Represents the threshold level of the RTC watchdog STG0 timeout.\\ 0: Original threshold configuration value of STG0 *2 \\1: Original threshold configuration value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: Original threshold configuration value of STG0 *16 \\
139SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key
140SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key
141SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key
142KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Represents the purpose of Key0
143KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Represents the purpose of Key1
144KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Represents the purpose of Key2
145KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Represents the purpose of Key3
146KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Represents the purpose of Key4
147KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Represents the purpose of Key5
148SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, [] Represents the spa secure level by configuring the clock random divide mode
149SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
150SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: enabled.\\ 0: disabled\\
151KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 123, 1, [] Set this bitto configure flash encryption use xts-128 key. else use xts-256 key
152FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
153DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
154DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
155DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 130, 1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: enabled\\
156LOCK_KM_KEY, EFUSE_BLK0, 131, 1, [] Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock\\
157DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ 1: Disable\\ 0: Enable\\
158ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
159FORCE_SEND_RESUME, EFUSE_BLK0, 136, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot.\\ 1: forced\\ 0:not forced\\
160SECURE_VERSION, EFUSE_BLK0, 137, 16, [] Represents the version used by ESP-IDF anti-rollback feature
161SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 153, 1, [] Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is enabled.\\ 1: disabled\\ 0: enabled\\
162HYS_EN_PAD, EFUSE_BLK0, 154, 1, [] Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: enabled\\ 0:disabled\\
163XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 155, 2, [] Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2: Moderate 1. Low\\ 0: Disabled\\
164XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 157, 1, [] Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0: Disable.\\
165HUK_GEN_STATE, EFUSE_BLK0, 160, 9, [] Set the bits to control validation of HUK generate mode.\\ Odd of 1 is invalid.\\ Even of 1 is valid.\\
166XTAL_48M_SEL, EFUSE_BLK0, 169, 3, [] Represents whether XTAL frequency is 48MHz or not. If not; 40MHz XTAL will be used. If this field contains Odd number bit 1: Enable 48MHz XTAL\ Even number bit 1: Enable 40MHz XTAL
167XTAL_48M_SEL_MODE, EFUSE_BLK0, 172, 1, [] Specify the XTAL frequency selection is decided by eFuse or strapping-PAD-state. 1: eFuse\\ 0: strapping-PAD-state
168ECDSA_DISABLE_P192, EFUSE_BLK0, 173, 1, [] Represents whether to disable P192 curve in ECDSA.\\ 1: Disabled.\\ 0: Not disable
169ECC_FORCE_CONST_TIME, EFUSE_BLK0, 174, 1, [] Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable. \\ 0: Disable
170MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address
171, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address
172, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address
173, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address
174, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address
175, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address
176MAC_EXT, EFUSE_BLK1, 48, 16, [] Represents the extended bits of MAC address
177WAFER_VERSION_MINOR, EFUSE_BLK1, 64, 4, [] Minor chip version
178WAFER_VERSION_MAJOR, EFUSE_BLK1, 68, 2, [] Minor chip version
179DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 70, 1, [] Disables check of wafer version major
180DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 71, 1, [] Disables check of blk version major
181BLK_VERSION_MINOR, EFUSE_BLK1, 72, 3, [] BLK_VERSION_MINOR of BLOCK2
182BLK_VERSION_MAJOR, EFUSE_BLK1, 75, 2, [] BLK_VERSION_MAJOR of BLOCK2
183FLASH_CAP, EFUSE_BLK1, 77, 3, [] Flash capacity
184FLASH_VENDOR, EFUSE_BLK1, 80, 3, [] Flash vendor
185PSRAM_CAP, EFUSE_BLK1, 83, 3, [] Psram capacity
186PSRAM_VENDOR, EFUSE_BLK1, 86, 2, [] Psram vendor
187TEMP, EFUSE_BLK1, 88, 2, [] Temp (die embedded inside)
188PKG_VERSION, EFUSE_BLK1, 90, 3, [] Package version
189PA_TRIM_VERSION, EFUSE_BLK1, 93, 3, [] PADC CAL PA trim version
190TRIM_N_BIAS, EFUSE_BLK1, 96, 5, [] PADC CAL N bias
191TRIM_P_BIAS, EFUSE_BLK1, 101, 5, [] PADC CAL P bias
192ACTIVE_HP_DBIAS, EFUSE_BLK1, 106, 4, [] Active HP DBIAS of fixed voltage
193ACTIVE_LP_DBIAS, EFUSE_BLK1, 110, 4, [] Active LP DBIAS of fixed voltage
194LSLP_HP_DBG, EFUSE_BLK1, 114, 2, [] LSLP HP DBG of fixed voltage
195LSLP_HP_DBIAS, EFUSE_BLK1, 116, 4, [] LSLP HP DBIAS of fixed voltage
196DSLP_LP_DBG, EFUSE_BLK1, 120, 4, [] DSLP LP DBG of fixed voltage
197DSLP_LP_DBIAS, EFUSE_BLK1, 124, 5, [] DSLP LP DBIAS of fixed voltage
198LP_HP_DBIAS_VOL_GAP, EFUSE_BLK1, 129, 5, [] DBIAS gap between LP and HP
199OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
200TEMPERATURE_SENSOR, EFUSE_BLK2, 128, 9, [] Temperature calibration data
201OCODE, EFUSE_BLK2, 137, 8, [] ADC OCode
202ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 145, 10, [] Average initcode of ADC1 atten0
203ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 155, 10, [] Average initcode of ADC1 atten0
204ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 165, 10, [] Average initcode of ADC1 atten0
205ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 175, 10, [] Average initcode of ADC1 atten0
206ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 185, 10, [] HI DOUT of ADC1 atten0
207ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 195, 10, [] HI DOUT of ADC1 atten1
208ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 205, 10, [] HI DOUT of ADC1 atten2
209ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 215, 10, [] HI DOUT of ADC1 atten3
210ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 225, 4, [] Gap between ADC1 CH0 and average initcode
211ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 229, 4, [] Gap between ADC1 CH1 and average initcode
212ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 233, 4, [] Gap between ADC1 CH2 and average initcode
213ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 237, 4, [] Gap between ADC1 CH3 and average initcode
214ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 241, 4, [] Gap between ADC1 CH4 and average initcode
215ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 245, 4, [] Gap between ADC1 CH5 and average initcode
216USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
217USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
218KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
219KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data
220KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data
221KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data
222KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data
223KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data
224SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)